JPS6320913A - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPS6320913A JPS6320913A JP61165907A JP16590786A JPS6320913A JP S6320913 A JPS6320913 A JP S6320913A JP 61165907 A JP61165907 A JP 61165907A JP 16590786 A JP16590786 A JP 16590786A JP S6320913 A JPS6320913 A JP S6320913A
- Authority
- JP
- Japan
- Prior art keywords
- output
- transistor
- gate
- circuit
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 11
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＮ−ＭＯＳ ＬＳＩの出力回路に関し。[Detailed description of the invention] [Industrial application field] The present invention relates to an N-MOS LSI output circuit.
特に出力電圧、出力駆動電流、出力スイッチングスピー
ドを改善する回路技術に関する。In particular, it relates to circuit technology that improves output voltage, output drive current, and output switching speed.
従来Ｎ−ＭＯ８ＬＳＩの出力回路はＮチャ、ネルトラン
ジスタを電源・グランド間に２つ縦積みに配し、電源側
・グランド側各々のトランジスタのゲートを互いに相補
な信号で駆動する構成を取シ、信号の振幅レベルがグラ
ンド電位から電源電位までであシ２つのトランジスタの
共通のドレイン・ソースを出力端子に接続する構成とな
っていた。Conventional N-MO8LSI output circuits have a configuration in which two N-channel channel transistors are stacked vertically between the power supply and the ground, and the gates of the transistors on the power supply side and the ground side are driven with mutually complementary signals. The amplitude level of the signal ranged from the ground potential to the power supply potential, and the common drain and source of the two transistors were connected to the output terminal.
上述した従来の技術では電源側のＮチャネルトランジス
タのゲート電位はグランドから電源電圧までとなってい
るので、ハイレベル出力時に出力端子にあられれる電位
は電源電圧からＮチャネルトランスタのパックゲート特
性を含む実効のしきい値だけ低下した電位でアリ、さら
に出力駆動電流を取シ出すことによるドロップが加わシ
次式で表わされる。In the conventional technology described above, the gate potential of the N-channel transistor on the power supply side is from the ground to the power supply voltage, so the potential that appears at the output terminal during high-level output varies from the power supply voltage to the packed gate characteristics of the N-channel transistor. The potential is lowered by the effective threshold value included, and the drop caused by extracting the output drive current is added, and is expressed by the following equation.
ｖｏＨ＝ ｖｃｃ ＶＴＮ ＶＩＯＵＴこの項のう
ちＶＴＮはトランジスタ構造の微細化に伴ないイオン注
入エネルギーを上げ耐圧を向上させる対束がなされるの
でバックゲート特性が悪化し大きくなる。ＶＯＨの規格
を満足するために出力トランジスタを別イオン注入で作
成する対策が取られるのでウェハー前処理工程に於ける
ＰＲ数が増加するという欠点がある。また製造のバラツ
キによ’） ＶＯＨ％性が劣化した場合規格割れによシ
ネ良になる欠点がある。voH=vcc VTN VIOUT Among these terms, VTN increases as the transistor structure becomes finer and the ion implantation energy is increased to improve the withstand voltage, so the back gate characteristics deteriorate and increase. In order to satisfy the VOH standard, a measure is taken to fabricate the output transistor by separate ion implantation, which has the disadvantage that the number of PRs in the wafer pretreatment process increases. In addition, if the VOH% property deteriorates due to manufacturing variations, there is a drawback that the cine quality may deteriorate due to cracking of the specifications.
上述した従来のＮ−Ｍ、０８ ＬＳＩの出力回路に対
し、本発明は出力最終段電源［Ｎチャネルトランジスタ
のゲートを電源電圧以上に昇圧することによシ出力信号
をグランド電位から電源電位の範囲でフルスイングさせ
ることが可能になるという独創的内容を有する。In contrast to the above-mentioned conventional N-M, 08 LSI output circuit, the present invention improves the output signal within the range from the ground potential to the power supply potential by boosting the output final stage power supply [the gate of the N channel transistor] above the power supply voltage. It has an original content that makes it possible to make a full swing.
本発明の出力回路は出力端子のプルアップ用トランジス
タのゲート信号にａ、押し上げ回路す、リーク補償回路
とＣ，ダイオードを付加して構成され、ａ、押し上げ回
路はプルアップ用トランジスタのゲート信号を入力とす
る遅延回路と遅延回路の出力を入力とする増幅回路を有
し、増幅回路の出力を容量を介してプルアップ用トラン
ジスタのゲートに接続することで構成され、ｂ、リーク
補償回路はプルアップ用トランジスタのゲート信号がバ
イ状態に限９動作を可能とするスイッチトランジスタと
ゲート、ドレイン共通のトランジスタをダイオードとし
て使用しクロック信号に一端を接続する容量の別の一端
が電源電位よシ低い場合に電荷を電源から供給するダイ
オードを接続し、またプルアップ用トランジスタのゲー
ト電位が容量の別の一端より低い場合に容量からプルア
ップ用トランジスタのゲートに電荷を供給するダイオー
ドを接続することで構成され、へダイオードはゲート。The output circuit of the present invention is configured by adding a push-up circuit, a leak compensation circuit, and a diode to the gate signal of the pull-up transistor of the output terminal. It has a delay circuit as an input and an amplifier circuit as an input with the output of the delay circuit, and the output of the amplifier circuit is connected to the gate of a pull-up transistor via a capacitor. A switch transistor that can operate only when the gate signal of the up transistor is in a by state, and a transistor with a common gate and drain is used as a diode, and one end of the capacitor is connected to the clock signal.When the other end of the capacitor is lower than the power supply potential. A diode is connected to supply charge from the power supply to the terminal, and a diode is connected to supply charge from the capacitor to the gate of the pull-up transistor when the gate potential of the pull-up transistor is lower than the other end of the capacitor. and the diode is gated.
ドレイン共通のトランジスタをアノードとし、ソースを
カソードとし、７ノードをプルアップ用トランジスタの
ゲートに接続しカソードを電源に接続することで構成さ
れる。It is constructed by using a transistor with a common drain as an anode, a source as a cathode, a seventh node connected to the gate of a pull-up transistor, and a cathode connected to a power source.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明のブロック図である。１０６．Ｍｌは１
０８．ＮＯＲで駆動され１０８．ＮＯＲの入力は１０１
、（ｊと出力端子ハイインピーダンス信号１ｏ２゜ｏｂ
で、１０７．Ｍ２は１０９．ＮＯＲで駆動され１０９゜
ＮＯＲの入力は１０３．４と１０２．ｏｂである。１１
１゜押し上げ回路は１１２．遅延回路と１１３．増幅器
と１１４、容量のカスケード接続で構成されその入出力
は共に１０８．ＮＯＲの出′力若しくは１０６．Ｍｌの
ゲートに接続される。１２１．リーク補償回路は１２２
、クロックを入力としておシ、１０８．ＮＯＲ出力若し
くは１０６．Ｍｌのゲート電位がノ１イであることを検
出して動作を開始し、１０８．ＮＯＲ出力若しくは１０
Ｇ、Ｍｌのゲート電位に出力を接続している。１３１．
ダイオードはアノードを１０８゜ＮＯＲ出力若しくは１
０６ 、 Ｉｖｉ ｌゲートに接続し、カンードを電源
に接続している。FIG. 1 is a block diagram of the present invention. 106. Ml is 1
08. Driven by NOR 108. NOR input is 101
, (j and output terminal high impedance signal 1o2゜ob
So, 107. M2 is 109. Driven by a NOR, the inputs of the 109° NOR are 103.4 and 102. It is ob. 11
The 1° push-up circuit is 112. delay circuit and 113. It consists of a cascade connection of an amplifier 114 and a capacitor, and its input and output are both 108. NOR output or 106. Connected to the gate of Ml. 121. The leak compensation circuit is 122
, with the clock as input, 108. NOR output or 106. Detecting that the gate potential of Ml is No. 1, the operation is started; 108. NOR output or 10
The output is connected to the gate potential of G and Ml. 131.
The diode has an anode of 108°NOR output or 1
06, Ivi I is connected to the gate, and the cand is connected to the power supply.
第２図は本発明の動作タイミングチャートである。２０
１．ｄと２０２．ｄはＮＯＲ入力信号２０３゜ＡＦｉＮ
ＯＲ出力若しくは出力プルアップトランジスタゲート信
号２０４．ＢはＮＯＲ出力若しくは出力タンクトランジ
スタブート信号２０５．Ｃは押し上げ回路単独動作時の
出力波形、２０６．φはリーク補償回路の入力となるク
ロック信号２０７．Ｅはリーク補償回路単独動作時の出
力波形で、図中Ｆはダイオードによシフランプされる電
位である。FIG. 2 is an operation timing chart of the present invention. 20
1. d and 202. d is the NOR input signal 203°AFiN
OR output or output pull-up transistor gate signal 204. B is the NOR output or output tank transistor boot signal 205. C is the output waveform when the push-up circuit operates alone, 206. φ is a clock signal 207. that is input to the leakage compensation circuit. E is the output waveform when the leakage compensation circuit operates alone, and F in the figure is the potential shifted by the diode.
２０３、Ａは２０１．ｄ入力によジグランド電位から電
源電位までスイッチングし、一定遅延時間後動作する２
０５．０押し上げ回路出力によシ電ｔｉｌｔ位のＶＴＮ
上まで押し上げられ、その後ジャンクシｌンリーク等に
よシ逃げていくチャージを補償するリーク補償回路の出
力２０７．Ｈによって電源電位のＶＴＮ上のレベルが保
持される。出力端子２０８゜Ｄは電源電位までフルスイ
ングし、そのレベルを保持する。203, A is 201. Switches from the di-ground potential to the power supply potential using the d input, and operates after a certain delay time 2
05.0 VTN of voltage tilt due to push-up circuit output
The output 207 of the leakage compensation circuit compensates for the charge that is pushed up to the top and then escapes due to junk leakage, etc. H maintains the level of the power supply potential above VTN. The output terminal 208°D fully swings to the power supply potential and maintains that level.
第３図は本発明をトランジスタレベルで記ｒした一実施
例の回路図である。３２１．押し上げ回路と３３１．リ
ーク補償回路と３４１．ダイオードをＮチャネルエンハ
ンスメントトランジスタとＮチャネルデプリーショント
ランジスタで構成した一実施例を示す。FIG. 3 is a circuit diagram of an embodiment in which the present invention is described at the transistor level. 321. Push-up circuit and 331. Leak compensation circuit and 341. An example will be shown in which the diode is configured with an N-channel enhancement transistor and an N-channel depletion transistor.
以上説明したように本発明はＮ ＭＯＳ ＬＳＩに
於て出力端子を駆動するＮチャネルプルアップトランジ
スタのゲートを押し上げ回路とリーク補償回路とダイオ
ードによって電源電圧以上ｖｃｃ＋ＶＴＮまで昇圧する
ことによシＮ−ＭＯ８ＬＳＩの出力特性のうちハイレベ
ル出力特性がＶＯＨ〜ＶＣＣまで改前されまた出力駆動
電流特性が改善され大負荷駆動が可能にな夛また出力が
フルスイングすることから出力ハイ判定電位まで上昇す
るスピードが速くなシ結果的に電ｙＡｔ圧が低い場合の
スイッチングスピード改善がなされるという効果を有す
る。As explained above, the present invention can be applied to an N-MOS LSI by boosting the gate of an N-channel pull-up transistor that drives an output terminal in an N-MOS LSI by boosting the gate to a voltage higher than the power supply voltage to vcc+VTN using a circuit, a leak compensation circuit, and a diode. Of the output characteristics, the high level output characteristics have been revised from VOH to VCC, and the output drive current characteristics have been improved, making it possible to drive large loads.Furthermore, since the output is full swing, the speed at which the output rises to the output high judgment potential has been increased. This has the effect of improving the switching speed when the voltage yAt voltage is low.
第１図は本発明、のブロック図、第２図は本発明の動作
タイミングチャート図、第３図は本発明をトランジスタ
レベルで記述した一実施例である。
１０１、ｄ・・・・・・出力負論理信号、１０２．ｏｂ
・・・・・・出力ハイインピーダンス信号、１０３．ｄ
・・・・・・出力正論理信号、１０４．Ｖｃｃ・・・・
・・電源、１０５．Ｄ・・・・・・出力端子、１０６．
Ｍｌ・・・・・・出力プルアップ用トランジスタ、１０
７．Ｍ２・・・・・・出力シンク用トランジスタ、１０
８．ＮＯＲ・・・・・・Ｍ１駆動回路、１０９．ＮＯＲ
・・・・・・Ｍ２駆動回路、２０１．ｄ・・・・・・出
力正論理信号、２０２、ｄ・・・・・・出力負論理信号
、２０３．Ａ・・・・・・Ｍ１ゲート信号、２０５．Ｃ
・・・・・・押し上げ回路単独の場合の出力波形、２０
６．φ・・−・・・リーク保償回路の入力になるクロッ
ク信号１．２０７．Ｅ・・・・・・リーク保償回路の出
力波形、２０８．Ｄ・・・・・・出力波形、３０１．ｄ
・・・・・・出力正論理信号、３０２．ｄ・・・・・・
出力負論理信号、３０３．ｏｂ・・・・・・出力ハイイ
ンピーダンス正論理信号、３０４．ｏｂ・・・・・・出
力ハイイイピーダンス負論理信号、３０５．Ｖｃｃ・・
・・・・電源、３０６．Ｃ８・・・・・・チップセレク
ト信号、３０８．φ・・・・・・クロック信号、３０９
．Ｍｌ・・・・・・出力プルアップ用トランジスタ、３
１０．Ｍ２・・・・・・出力シンク用トランジスタ、３
１１、Ｄ・・・・・・出力端子。
１）１鳴 ）
＼ 〜 勺
を 発 艶
ａンｄ
乙４Ｂ
１！７２図FIG. 1 is a block diagram of the present invention, FIG. 2 is an operation timing chart of the present invention, and FIG. 3 is an embodiment of the present invention described at the transistor level. 101, d... Output negative logic signal, 102. ob
...Output high impedance signal, 103. d
. . . Output positive logic signal, 104. Vcc...
...Power supply, 105. D...Output terminal, 106.
Ml...Output pull-up transistor, 10
7. M2... Output sink transistor, 10
8. NOR...M1 drive circuit, 109. NOR
...M2 drive circuit, 201. d... Output positive logic signal, 202, d... Output negative logic signal, 203. A...M1 gate signal, 205. C
...Output waveform in case of push-up circuit alone, 20
6. φ...--Clock signal 1.207 which becomes the input of the leakage guarantee circuit. E... Output waveform of leak guarantee circuit, 208. D... Output waveform, 301. d
...Output positive logic signal, 302. d・・・・・・
Output negative logic signal, 303. ob...Output high impedance positive logic signal, 304. ob...Output high impedance negative logic signal, 305. Vcc...
...Power supply, 306. C8...Chip select signal, 308. φ...Clock signal, 309
．． Ml...Output pull-up transistor, 3
10. M2...Output sink transistor, 3
11, D... Output terminal. 1) 1 ring) ＼ 〜 庺 う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う う や 和 和 和 am 4 B 1!72 fig.
Claims (1)
トランジスタと出力端子とグランドとの間に接続した出
力シンク用トランジスタと、出力プルアップ用トランジ
スタのゲートを駆動するＮＯＲ回路と出力シンク用トラ
ンジスタのゲートを駆動するＮＯＲ回路と、出力プルア
ップ用トランジスタのゲート信号を入力とする遅延信号
を容量を介して出力プルアップ用トランジスタのゲート
信号に接続してなる押し上げ回路と、クロック信号によ
り出力プルアップ用トランジスタのゲート電位を保持す
るリーク保償回路と、出力プルアップ用トランジスタの
ゲートをアノードとし電源をカソードとするダイオード
を含むことを特徴とする出力回路。 ２、押し上げ回路はインバータ若しくはＮＡＮＤの奇数
段接続からなる遅延回路とソースをグランド、ゲートを
遅延回路の出力とする第１のトランジスタと、第１のト
ランジスタのドレインをソースとしゲートを出力プルア
ップ用トランジスタのゲートに接続する第２のトランジ
スタと遅延回路の出力に接続するインバータ若しくはＮ
ＡＮＤと出力をゲート信号としてドレインを電源、ソー
スを第２のトランジスタのドレインに接続する第３のト
ランジスタからなり、第１と第２のトランジスタの接続
点を出力とすることを特徴とする特許請求の範囲第１項
記載の出力回路。 ３、リーク補償回路はクロック信号をドレインとし、出
力プルアップ用トランジスタのゲートをゲートとする第
４のトランジスタと第４のトランジスタのソースを容量
に接続し容量の一端を第５のトランジスタのゲート、ド
レインに接続しソースを出力プルアップ用トランジスタ
のゲート信号に接続し、前記容量の一端はまた第６のト
ランジスタのソースに接続しゲートを電源にドレインを
第７のトランジスタのソースに接続し、ゲートを出力プ
ルアップ用トランジスタのゲート信号としドレインを電
源に接続するトランジスタを有してなる特許請求の範囲
第１項、第２項記載の出力回路。[Claims] 1. Drives the output pull-up transistor connected between the power supply and the output terminal, the output sink transistor connected between the output terminal and ground, and the gate of the output pull-up transistor. A push-up circuit consisting of a NOR circuit that drives the gate of the output sink transistor, and a delayed signal that receives the gate signal of the output pull-up transistor as input and connects it to the gate signal of the output pull-up transistor via a capacitor. an output circuit comprising: a leak guarantee circuit that maintains the gate potential of the output pull-up transistor according to a clock signal; and a diode whose anode is the gate of the output pull-up transistor and whose cathode is the power supply. 2. The push-up circuit consists of a delay circuit consisting of an odd number of inverters or NANDs connected, a first transistor whose source is the ground and whose gate is the output of the delay circuit, and whose drain is the source and whose gate is the output for pull-up. A second transistor connected to the gate of the transistor and an inverter or N connected to the output of the delay circuit.
A patent claim comprising a third transistor whose drain is connected to a power source and whose source is connected to the drain of a second transistor using AND and an output as a gate signal, and the connection point between the first and second transistors is the output. The output circuit according to the range 1 above. 3. The leakage compensation circuit has a clock signal as the drain, a fourth transistor whose gate is the gate of the output pull-up transistor, a source of the fourth transistor connected to a capacitor, and one end of the capacitor connected to the gate of the fifth transistor, The drain is connected to the drain, the source is connected to the gate signal of the output pull-up transistor, one end of the capacitor is also connected to the source of the sixth transistor, the gate is connected to the power supply, the drain is connected to the source of the seventh transistor, and the gate is connected to the source of the seventh transistor. 3. The output circuit according to claim 1, further comprising a transistor whose drain is connected to a power supply and whose gate signal is a gate signal of an output pull-up transistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61165907A JPS6320913A (en) | 1986-07-14 | 1986-07-14 | Output circuit |
| US07/073,130 US4806798A (en) | 1986-07-14 | 1987-07-14 | Output circuit having a broad dynamic range |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61165907A JPS6320913A (en) | 1986-07-14 | 1986-07-14 | Output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6320913A true JPS6320913A (en) | 1988-01-28 |
Family
ID=15821268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61165907A Pending JPS6320913A (en) | 1986-07-14 | 1986-07-14 | Output circuit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4806798A (en) |
| JP (1) | JPS6320913A (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6437797A (en) * | 1987-08-03 | 1989-02-08 | Oki Electric Ind Co Ltd | Eprom device |
| USRE35745E (en) * | 1988-10-28 | 1998-03-17 | Sgs-Thomson Microelectronics S.R.L. | Device for generating a reference voltage for a switching circuit including a capacitive bootstrap circuit |
| IT1228509B (en) * | 1988-10-28 | 1991-06-19 | Sgs Thomson Microelectronics | DEVICE TO GENERATE A FLOATING POWER SUPPLY VOLTAGE FOR A CAPACITIVE BOOTSTRAP CIRCUIT |
| US5117130A (en) * | 1990-06-01 | 1992-05-26 | At&T Bell Laboratories | Integrated circuits which compensate for local conditions |
| US5128563A (en) * | 1990-11-28 | 1992-07-07 | Micron Technology, Inc. | CMOS bootstrapped output driver method and circuit |
| KR940005509B1 (en) * | 1992-02-14 | 1994-06-20 | 삼성전자 주식회사 | Voltage up inhibition circuit and output buffer circuit with it |
| US5274276A (en) * | 1992-06-26 | 1993-12-28 | Micron Technology, Inc. | Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit |
| US5324996A (en) * | 1993-02-16 | 1994-06-28 | Ast Research, Inc. | Floating fault tolerant input buffer circuit |
| JPH0738410A (en) * | 1993-07-21 | 1995-02-07 | Oki Electric Ind Co Ltd | Output buffer circuit |
| US5457433A (en) * | 1993-08-25 | 1995-10-10 | Motorola, Inc. | Low-power inverter for crystal oscillator buffer or the like |
| JP3238826B2 (en) * | 1994-04-13 | 2001-12-17 | 富士通株式会社 | Output circuit |
| KR0154157B1 (en) * | 1994-04-29 | 1998-12-15 | 김주용 | Boots trap circuit |
| US5519340A (en) * | 1994-11-01 | 1996-05-21 | Motorola Inc. | Line driver having maximum output voltage capacity |
| US5495195A (en) * | 1994-11-17 | 1996-02-27 | Advanced Micro Devices, Inc. | Output buffer for a high density programmable logic device |
| JPH08148986A (en) * | 1994-11-21 | 1996-06-07 | Mitsubishi Electric Corp | Output buffer circuit |
| KR960043524A (en) * | 1995-05-23 | 1996-12-23 | 홍-치우 후 | Output buffering device |
| KR101548242B1 (en) * | 2008-07-21 | 2015-09-04 | 삼성전자주식회사 | Output driving device in semiconductor device method thereof and electronic processing device having the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4585958A (en) * | 1983-12-30 | 1986-04-29 | At&T Bell Laboratories | IC chip with noise suppression circuit |
-
1986
- 1986-07-14 JP JP61165907A patent/JPS6320913A/en active Pending
-
1987
- 1987-07-14 US US07/073,130 patent/US4806798A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4806798A (en) | 1989-02-21 |
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