JPS63208966A - Dma transfer control system - Google Patents

Abstract

PURPOSE:To set various parameters at a DMA controller at a high speed by setting those various parameters needed for DMA transfer at the DMA controller from a CPU via a register of a reception frame control part. CONSTITUTION:When data is received by a communication control part CPU5 from a communication circuit 10, a bus master of a system bus is shifted to a DMA controller DMAC4 from the CPU1. Then the received data is transferred in turns of DMA to a memory 3 from the CCU5 based on various parameters stored in the DMAC4. When this transfer of data is ended, the bus master of the system bus moves to a reception frame control part 6 and various parameters stored in a register of the part 6 are sent to the DMAC4 and stored there. When this action is ended, the bus master returns to the CPU1 and those various parameters stored in the register of the part 6 are changed by the CPU1 for the next DMA transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DMA (direct memory access) transfer control system in, for example, a communication device.

[Prior Art] Conventionally, for example, when performing DMA transfer in a communication device,
Various parameters are set in the DMA controller (DMAC) by a CPU such as a microprocessor, and the DMA
When a start is instructed, data is transferred between the transmitting/receiving buffer and the memory using DMA. Specifically, when one word of communication data is received, for example, a request is issued to the DMAC to transfer DMA data from the reception buffer to the memory. This causes the DMAC to request use of the system path and transfer one word of received data to the memory using, for example, a cycle steal method. By repeating the MA transfer operation in this way, a plurality of words of communication data are transferred across the memory, and when the transfer of one frame of communication data is completed, the CPU is notified that the reception of one frame has ended. Upon completion of the reception of this one frame, the CPU resets each parameter of the DMAC in preparation for the next reception, and prepares for the reception of the next frame.

[Problems to be Solved by the Invention] Therefore, the CPU needs to execute at least the following steps between the end of receiving one frame and the start of receiving the next frame.

Step 1 Task switching when responding to an interrupt Step 2 Securing storage area for receiving the next frame Step 3 Resetting the internal registers of the DMAC However, the time required for these steps is slow due to program control, and especially in Step 2, the storage area is The intervention of another task to manage itself is required. This means that when designing a communication system, it is necessary to allow for a large margin time in addition to the time required for all of the above steps. There was a problem in that the ability to receive and process data reliably was restricted.

The present invention has been made in view of the above-mentioned conventional example, and an object of the present invention is to provide a DMA transfer control method that enables high-speed resetting of various parameters in a DMA control unit without the need for program control by a CPU. shall be.

[Means for Solving the Problems] In order to achieve the above object, the DMA transfer control system of the present invention has the following configuration. That is, a DMA control means connected to a common path with the CPU, a storage means for inputting and storing various parameters to the DMA control means from the CPU, and a set address of the various parameters to the 1) MAC. The device includes address means for outputting, and means for outputting the various parameters from the storage means to the DMA control means in synchronization with the basic clock of the CPU.

[Operation] In the above configuration, various parameters to the DMA control means connected to the common path with the CPU are inputted from the CPU and stored in the storage means. Before starting DMA transfer, the CPU
It operates to read various parameters from the storage means in synchronization with the basic clock of the CPU, output them to the address of the DMA control means addressed by the address means, and set the various parameters regardless of the control of the CPU.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of communication device (Figure 2)] FIG. 2 is a configuration diagram of the main parts of the communication device of this embodiment.

In the figure, reference numeral 1 denotes a CPU, which is, for example, an 8-bit microprocessor, which performs various logical operations and input/output control signals in accordance with control programs and data stored in the program memory 2, and controls the operation of the entire apparatus. 3 is a memory for storing transmitted and received data. 4 is a DM between the memory 3 and the communication control unit (CCU) according to the set parameters.
This is a DMA controller (DMAC) that performs A transfer.

5 is connected to the communication line 10, and
Communication control unit (CC) that supports lower level 5 level 2 functions.
In U), these lower-level functions specifically refer to functions such as flag synchronization, time fill, and zero insertion/deletion in HDLC (High Level Data Link Control) frames.

Reference numeral 6 denotes a reception frame control unit whose details are shown in FIG. 1, which sets various parameters to the DMAC 4 as described later. These units 1 to 6 are interconnected via an address bus 7, a data bus 8 (8 bits), and a control line 9 (hereinafter collectively referred to as a system bus).
The control line is a collection of all control signal lines such as read/write lines, clock signal lines, and bus request signal lines that control operations between devices.

In the above configuration, the CCU 3 performs 1-byte DMA transfer with the memory 3 via the system bus, and also transmits/receives IDLC frame data with the communication line 10 via the X, 21 interface, etc. I do. C.C.
When U 5 transfers the data received from the communication line 10 to the memory 3 by DMA, this DMA channel is used as the receiving DMA.
It's called a channel. The receive DMA channel is controlled by internal registers of DMAC4, but at least two registers are required. One is a 16-bit receive address register (RxADR) that stores the memory address to which the received data is transferred, and the other is a 16-bit receive byte count register (RxADR) that stores the maximum length of the received frame.
, BCR).

[Description of Received Frame Control Unit (FIG. 1)] FIG. 1 is a block diagram showing the configuration of the received frame control unit of this embodiment.

Reference numeral 100 denotes a control circuit that controls the reception frame control unit 6, and when it detects the end of reception via the control line 9, it outputs a bus request signal (BUS'RQ) to request a bus, and also outputs a bus request from the CPU The control signal and the address decode signal 109 from the decoder 102 are input,
Write signal 107.10 to register 104.105
Outputs 8. As a result, various parameters from the CPUI are set in the register corresponding to the address decode signal 109. A decoder 102 inputs the lower address of 16-bit address data from the address bus 7, decodes it, and outputs an address decode signal 109.

The output of the address sequencer 103 is connected to the address bus 7 via a 3-state output buffer, and
The basic clock 106 of I is used as a sequence clock, and specific address data is output to the address bus 7. In this embodiment, it is assumed that this address data is fixed and set in advance.

Both 104 and 105 are 16-bit registers, each consisting of two 8-bit registers, and each register has 3
It is connected to data bus 8 via a state input/output buffer. These four 8-bit registers are decoder 1
It is selected by the address decode signal 109 from 02. Timing sequencer 101 has basic clock 10
6 is input to control the output timing of the four 8-bit registers and the output timing of address data from the address sequencer 103.

With the above configuration, each parameter from CPU 1 is written to each 8-bit register of registers 104 and 105, and the 8-bit data of each register is written to the basic clock 10.
It will be written to the internal register of DMAC4 in one clock cycle of 9.

[Operation explanation (Figures 3 to 6)] Figure 3 shows the CPUI stored in the program memory 2.
2 is a flowchart of a control program for data reception processing in FIG.

This program is started by turning on the power of the device, and first performs initialization processing shown in FIG. 4 in step S1. If data is received in step S2, the process advances to step S3, and the DM
Instructs AC4 to start DMA. Incidentally, this DMA may be started automatically by the DMAC 4 according to an instruction from the CCU 3.

When DMA is started, the bus master of the system bus is cp
ut to DMAC4 (step 510), and in step SIO, input the received data from CCU3, transfer 1 byte of DMA data to memory 3, and continue data transfer from CCU3 to memory 3 until reception of one frame is completed. Repeatedly, when data transfer of 1 frame is completed, D
Finish MA.

Step Sit is an operation step of the reception frame control section at the end of data reception of one frame, and the details are shown in FIG.

When step S10.11 is completed, CPU I becomes the bus master again in step S4, and control is given to CPU i. In step S4, a reception area for the next frame is secured in the memory 3. In step S5, the upper 8 bits of the start address of the reception area secured in memory 3 are stored in register 1.
04, and in step S6, the lower 8 bits of the start address are written to the lower byte of register 10'4. Thereafter, the process returns to step SZ, and upon receiving the received data, the above-described operations are repeated.

Note that in this flowchart, the number of data in one frame is fixed, and the maximum number of transfer bytes of the received frame in the register 105 is not rewritten after step S4.
When the number of data in l frame changes, register 10
Of course, a step of changing the data in step 5 may be added.

FIG. 4 is a flowchart of initialization processing by the CPUI.

In step S20, a reception area for one frame data is secured in the memory 3, and in step S21, the start address of the memory area secured in step S20 is written into the reception address registers R and ADR of the DMAC 4. Step S22
Now, DMAC4 receive byte count register R, BC
Write the maximum number of transfer bytes of the received frame to H. In step S23, a memory area for the next received frame is secured in the memory 3, and in step S24, the starting address of the memory area secured in step 323 is written in the register 104. Next, in step S25, the maximum number of transfer bytes of the received frame is written into the register 105.

[Explanation of operation of received frame control section (FIGS. 5 and 6)] FIG. It is a flowchart.

When the completion of the DMA transfer path is detected in step S30, the process proceeds to step S31, and a bus request signal is outputted to the bus master of the system bus as much as possible. When the bus request is accepted and the device becomes the bus master, the process proceeds to step 333, where the timing sequencer 101 and address sequencer 103 are activated. In step S34, the upper byte of the register 104 is written to the upper byte of the reception address register RXADR of the DMAC4.
The lower byte of is written to the lower byte of R and ADR of DMAC4.

Next, in steps S36 and 37, the upper byte and lower byte of the register 105 are written into the received byte count registers R and BCR of the DMAC4. These write operations are executed in one clock cycle of the basic clock 106.

In step 338, the operation of the timing sequencer 1.1 and the address sequencer 103 is stopped, and in step S3
At step 9, use of the system bus is abandoned and the process ends.

FIG. 6 is a diagram comparing the operation timing of the CPUI and the operation timing of the reception frame control section.

60 is a waveform showing the basic timing of the address bus and data bus, and 61 is a write signal (WR) output from the CPUI. In this way, in a normal microprocessor, even if write data is set in the accumulator, writing to each register of DMAC4 (I1
0 write instruction), at least the basic clock 109:4
The time required for the cycle is required.

In comparison, in this embodiment, writing 4 bytes of data to the DMAC 4 can be done in 4 clock cycles of the basic clock 109, so each parameter of the DMAC 4 can be set at high speed.

In this embodiment, the internal register RxADR of DMAC4
Although the data set of %RXBCR has been described, the present invention is not limited to this, and virtual registers may be provided in the reception frame control unit 6 to write to all of the writable internal registers of the DMAC 4. For example, if a virtual register is provided for the internal register that allows/disables DMA transfer of DMAC4, the subsequent DM transfers will be executed at the same time as frame reception is completed upon request from the system side.
A transfer can be prohibited.

Further, although the present embodiment has been described with respect to DMA transfer of a communication device, the present invention is not limited to this, and it goes without saying that the present invention can also be applied to DMA transfer with a normal memory or an I10 device.

As described above, according to the present embodiment, the DMAC transfer preparation can be performed at high speed, so that there is an effect that continuous communication frames can be reliably received at high speed.

[Effects of the Invention] As described above, according to the present invention, various parameters can be set to the DMAC at high speed, so there is an effect that DMA transfer can be performed continuously at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of the reception frame control section of this embodiment, FIG. 2 is a diagram showing the configuration of the main part of the communication device of this embodiment, and FIG. 3 is a flowchart of reception control by the CPU. Figure 4 is a flowchart showing the initialization process by the CPU, Figure 5 is a flowchart of the DMAC parameter setting operation by the received frame control unit, and Figure 6 is a comparison between the timing of writing to the DMAC and the operation of the CPU. This is a timing chart. In the figure, 1...CPU, 2...Program memory, 3
...Memory, 4...DMAC, 5...CCU, 6
. . . Reception frame control unit, 7 . . Address bus, 8
...Data bus, 9...Control line, 10...Communication line, 100...Control unit, 101...Timing sequencer, 102...Decoder, 103...
Address sequencer, 104.105... register,
106...Basic clock, 10F, 108...Write signal.

Claims (2)

[Claims] (1) A DMA control means connected to a common bus with the CPU, and various parameters to the DMA control means
a storage means for inputting and storing the various parameters, an address means for outputting a set address of the various parameters to the DMAC, and an outputting of the various parameters from the storage means to the DMA control means in synchronization with a basic clock of the CPU. A DMA transfer control method characterized by comprising means for (2) The DMA transfer control method according to claim 1, wherein the transfer of various parameters from the storage means to the DMA control means is performed by direct access without going through the CPU.