JPS63208958A - Memory write/read protecting device - Google Patents

Abstract

PURPOSE:To avoid writing of wrong data by producing a resetting signal of CPU after the end of a memory writing/reading cycle. CONSTITUTION:A central arithmetic processing part 5 performs the data writing/ reading jobs to a memory 7 via a data line d2 and this writing/reading timing is controlled by a writing signal b2 and a reading signal c2. When the signal b2 or c2 is delivered, a resetting permission signal e2 given from a memory write/read control part 8 is turned off. Then a resetting signal generating part 9 of a CPU produces no resetting signal a2. This signal a2 is produced after the signal e2 is turned on. When the signal a2 is turned on, a memory control signal transmission control part 6 is blocked and the writing is inhibited to the memory 7.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a storage section of an arithmetic and control unit, and in particular, to a memory that protects writing to or reading from a storage element (hereinafter referred to as "memory") at the time of system reset. This invention relates to a read/write protection device.

[Conventional technology]

Conventionally, this type of memory write/read protection device has been realized with a configuration as shown in FIG.

In FIG. 3, 1 is a central processing unit, 2 is a memory control signal transmission control unit, 3 is a memory, and 4 is a reset signal generation unit. Further, al is a reset signal output from the reset signal generating section 4, and bl, cl, and dl are a memory write signal, a memory read signal, and data output from the central processing section 1.

FIG. 4 shows a time chart for explaining the operation of the memory write/read protection device of FIG. 3.

FIG. 4(a) shows the memory write signal b1, and FIG. 4(b) shows the reset signal 'a1. In FIG. 4, when the reset signal a1 becomes valid at time TI during the period when the memory write signal b1 is valid, that is, during the memory write period, the central processing unit 1 enters the initialization state, and the memory write signal Ignore b1. At the same time, the memory control signal transmission control section 2 also prohibits transmission of the memory write signal b1. As a result, the data d1 and memory write signal b1 applied to the memory 3 are
As shown in the figure, a valid period long enough to satisfy the standards of the memory 3 is not guaranteed, and the memory becomes invalid midway through. Therefore, the operation of the memory 3 is not guaranteed, and there is a possibility that erroneous data may be written to the memory 3.

[Problem that the invention seeks to solve]

In this manner, in the conventional memory write/read protection device, there is a possibility that erroneous data may be written to the memory 3. In this memory 3, important parameters for device operation, such as own station address information and
Contains very important parameters such as routing information. If this parameter is rewritten with incorrect data, the device will not be able to operate normally.
Depending on the time and circumstances, this may cause a line failure of the entire communication network.

[Means for solving problems]

In order to solve these problems, the present invention provides a memory write/read period detection unit that detects a data write period to the memory and a data read period from the memory, and a detection output from the memory write/read period detection unit. and a reset signal generation section that controls the generation of the reset signal using a signal, and the reset signal generation section synchronizes the generation of the reset signal with data writing to or reading data from the memory, and synchronizes the generation of the reset signal with data writing or reading data from the memory. After the completion of the reset, a reset signal is generated to protect the write/read operations to the memory at the time of reset.

[Effect]

In the memory write/read protection device according to the present invention, even if a reset factor occurs during the memory write period, the memory write can be protected and erroneous data will not be written.

〔Example〕

An embodiment of a memory write/read/output protection device according to the present invention is shown in FIG. In FIG. 1, 5 is a central processing unit, 6 is a memory control signal transmission controller, 7 is a memory, 8 is a memory write/read period detector, and 9 is a reset signal generator.

Normally, the reset signal a2 is disabled, and the central processing unit 5 outputs the memory write signal b2 or the memory continuation signal c2, and executes writing to or reading from the memory 7 regarding the data d2. are doing. At this time, the memory control signal voltage control section 6 is transmitting signals.

FIG. 2 is a time chart when a reset factor occurs during the memory write period. FIG. 2(a) shows the memory write signal b2, and FIG. 2(a) shows the reset signal a2. As shown in FIG. 2(b), the reset factor is at time T2.
If the reset signal a occurs, the reset signal generator 9 internally stores that a reset factor has occurred, but the reset signal a
2 is not yet valid. When the reset factor occurs, the central processing unit 5 continues to output the memory write signal b2 and the data d2, and the memory control signal transmission control unit 6
continues to transmit signals.

When the central processing unit 5 completes data writing to the memory 7, the memory write/read period detection unit 8 detects the end of the write period using the memory write signal b2 at time T3 shown in FIG. 2 (bl). The end of the memory read period is detected by the memory read signal c2.The memory write/read period detecting section 8 which has detected the end of the memory writing period makes the reset signal enable signal e2 valid to the reset signal generating section 9.Reset signal generation After the reset signal permission signal e2 becomes valid, the unit 9 first makes the reset signal a2 valid as shown in FIG. Prohibiting signal transmission - Through these operations, even if a reset factor occurs during the memory write period, the memory write period is guaranteed and erroneous data will not be written, as shown in FIG.

In the above embodiments, protection of memory write operations has been described, but protection of memory read operations can also be achieved in a similar manner.

〔Effect of the invention〕

As explained above, the present invention includes a memory write/read period detecting section that detects a period for writing data to the memory and a period for reading data from the memory, and a detection signal output from the memory writing/reading period detecting section to generate a reset signal. and a reset signal generation section that controls generation of the reset signal, the reset signal generation section synchronizing the generation of the reset signal with data writing to or reading data from the memory,
And by generating a reset signal after the completion of the reset and protecting the write/read operations to the memory at the time of reset, even if a reset factor occurs during the memory write/read period, the memory write/read can be protected. This has the effect that erroneous data writing or reading does not occur.

As a result, even if important parameters, such as address information and routing information of the own station, are stored in the memory, data will not be destroyed due to a reset, which has the effect of preventing abnormal operation of the device.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an embodiment of the memory write/read protection device according to the present invention, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is a system diagram showing a conventional memory write/read protection device. 4 are time charts for explaining the operation. 5... Central processing unit, 6... Memory control signal transmission control unit, 7... Memory, 8... Memory write/read period detection unit, 9... Reset signal generation unit. Patent applicant: NEC Corporation Shizuoka NEC Corporation

Claims (1)

[Claims] a memory write/read period detection unit that detects a data write period to the memory and a data read period from the memory; and a reset signal generation unit that controls generation of a reset signal based on a detection signal output from the memory write/read period detection unit. The reset signal generating section synchronizes the generation of the reset signal with data writing to or reading data from the memory, and generates the reset signal after the data writing or data reading is completed, and resets the reset signal. A memory write/read protection device is characterized in that it protects write/read operations to and from a memory.