JPS63208905A - Sequence generating circuit - Google Patents

Abstract

PURPOSE:To obtain a general-purpose and high-speed sequence generating circuit by storing the sequence state and its changing time point. CONSTITUTION:A sequence generating circuit consists of a sequence memory 1 which stores the sequence state, a time memory 2 which stores the changing time point of the sequence, an initial value memory 3, an output selection register 4, a control part 5, a clock 6, and an external setting device 7 of a personal computer, etc. set via an interface 8. The part 5 includes a counter 51, a timer 52 and a comparator 53. Thus the contents of the memory 3 are outputted while the register 4 is selecting the initial value and furthermore the contents of the memory 1 can be freely programmed under the control of the part 5. At the same time, the part 5 performs the control so that the sequence state is successively changed by the contents of the memory 2 as well as the clock 6 while the register 4 is selecting a sequence.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a sequence generation circuit that is widely used as a control device.

(Prior art) Conventionally, as a sequence generation circuit, a mechanical type using a relay or a cam, a pin board type using a diode matrix, a programmable controller using a microprocessor, etc. have been used (October 1981 Ohm Automatic Control Handbook (Equipment/Application Edition) Chapter 7 Sequence Control Equipment) published by the company.

(Problems to be Solved by the Invention) However, in the 5 mechanical type and the bin board type, the sequence program is changed manually.

It was unsuitable for use as a general-purpose device or for large-scale systems.

On the other hand, in a programmable controller, the input power is 1M,
Since a series of processes such as program execution, self-diagnosis, and output transfer are performed by a microprocessor, the time required (scan time) is 110m5ec-1
It takes approximately 00w+sac, and it is extremely difficult to operate at higher speeds.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to provide a sequence generation circuit that is versatile and can operate at high speed.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a memory that stores the state of a sequence, a memory that stores time or a time difference, a memory that stores an initial value, and an output selection register. , a control unit that controls these, and a clock.

(Function) In the above means, during the period in which the output selection register selects the initial value, the contents of the initial value memory are output, and the contents of the sequence memory are controlled by the control unit so that they can be freely programmed. Ru.

On the other hand, during the period in which the output selection register is selecting the sequence, the control unit controls the sequence state to change sequentially depending on the clock and the contents of the time memory.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a sequence generation circuit showing an embodiment of the present invention.

In Figure 1, 1 is a memory that stores the sequence state, the number of output points N and the maximum number of changes in the sequence state 2
-1 consists of RAM according to Reference numeral 2 denotes a memory for storing sequence change times, which is composed of a RAM and has the same address length as the sequence memory 1. 3 is a memory for storing initial values, 4 is an output selection register,
The number of output points for each is N, which is the same as in sequence memory 1. i is a control unit, and its configuration includes, for example, a counter 51.i as shown in a dotted line frame. Timer 52. It consists of a comparator 53. Further, 6 is a clock that provides a reference for sequence time, and its period is assumed to be ΔT. Reference numeral 7 denotes a device for setting and controlling the state of the sequence, such as a personal computer or a processor, and setting is made to the sequence generation circuit via an interface 8.

The operation of the present invention can be broadly divided into the following three parts.

ω Initial state setting ■ Sequence state setting ■ Sequence operation Next, items (1) and (2) will be explained using the time chart shown in FIG. 2, and (2) will be explained using the time chart shown in FIG. 3.

In FIG. 1, when the control signal 15-1 is in the logic "1" state, the output selection register 4 selectively outputs the output of the initial value memory 3 and derives it as the sequence output signal 14. Therefore, as shown in FIG. 2, if the initial states A, B, and C are written as the initial setting values 13 in the initial value memory 3,
These will be derived as sequence output signals 14. When the control signal 15-1 is "1", the sequence memory 1 and the time memory 2 are also in a writable state at the same time. Therefore, if you want to change the sequence state 11, set the control signal 15-3 to logic "1".
In this state, the counter 51 is enabled to advance the count, and the control signal 15-4. Sequence-like jllll
By synchronizing and outputting l and time setting value 12, data is sequentially written into sequence memory 12 and time memory 2. At this time, since the sequence output signal 14 selects the output of the initial value memory 3, it is not affected by the writing of the sequence memory 11 to the time memory 2.

Next, if you want to perform sequence operations.

As shown in FIG.
1, the output selection register 4 is set to the sequence memory 1.
Select the output of At the same time, control signal 15
-2, 15-3 as logic “1”, counter 5
1. The timer 52 is made operable.

At this time, the sequence memory 12 and time memory 2 are in the read state, so the sequence output signal 14 contains the contents of the first address of the sequence memory 1, for example, address O in FIG. address 0
The contents of each address (2 in the example of FIG. 3) are output. The comparator 53 compares the output of the time memory 2 and the output of the timer 52, and when they match, outputs a pulse indicating a match. As a result, the sequence address 16, which is the output of the counter 51, advances to address 1, and as a result,
Data at the next address in the sequence memory 1 is output to the sequence output signal 14, while the time setting value at the next address in the 1-time memory 2 is output to the comparator 53. In this manner, the sequence ends when the data in the time memory 2 reaches the maximum set time 2-1 or reaches the final address.

As described above, according to the present embodiment, it is possible to easily realize a sequence generation circuit in which the sequence can be easily set and changed, and the number of output points and the time can be applied over a wide range.

Furthermore, since it does not involve a single mechanical contact or a microprocessor, it has the advantage of being able to operate at very high speed.

Furthermore, the present invention has the advantage that since the initial value setting and the sequence setting can be made independently, the sequence setting can be made while the system is operating in the initial state.

In the above-mentioned embodiment, RAM was used for the sequence memory and time memory, but if the setting value changes are infrequent, ROM may be used to store the sequence status and external settings for time setting. The device can be omitted.

Also, if an external clock is prepared separately, the first
It is also possible to omit the clock 6 in the figure and operate in synchronization with an external clock.

Further, in the above-described embodiment, the time at which the sequence changes is stored, but the same operation and effect can be obtained even if this time is used as the time difference until the next sequence change.

〔Effect of the invention〕

As described above, according to the present invention, the sequence state and its change time are stored in memory.

A sequence generation circuit that is general-purpose and operates at high speed can be provided.

In addition, we prepared a separate memory to store the initial state, so
This has the significant advantage that sequences can be set and changed even while the system is running.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the invention, and FIGS. 2 and 3 are time charts for explaining the invention in detail. 1... Sequence memory 2... Time memory 3.
...Initial value memory 4...Output selection register large
...Control unit 6...Clock agent Patent attorney Nori Chika Ken Yudo Hirofumi Mitsumata Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] There is an initial value memory that stores initial setting values, a sequence memory that stores sequence status, a memory that stores time or time difference, and output from either initial value memory or sequence memory is selected according to commands from an external setting device. A sequence generation circuit consisting of an output selection register that outputs the selected sequence, a control section that controls these sequence memories, a memory that stores time or time difference, and a clock.