JPS6320830A - Fine processing - Google Patents

Fine processing

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Publication number
JPS6320830A
JPS6320830A JP16502586A JP16502586A JPS6320830A JP S6320830 A JPS6320830 A JP S6320830A JP 16502586 A JP16502586 A JP 16502586A JP 16502586 A JP16502586 A JP 16502586A JP S6320830 A JPS6320830 A JP S6320830A
Authority
JP
Japan
Prior art keywords
mask
charged
etching
irradiation
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16502586A
Other languages
Japanese (ja)
Inventor
Iwao Tokawa
東川 巌
Keiji Horioka
啓治 堀岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP16502586A priority Critical patent/JPS6320830A/en
Publication of JPS6320830A publication Critical patent/JPS6320830A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent a mask from being charged with electricity and carry out a favorable etching treatment by using conductive organic materials as a mask on the occasion of performing a selective etching treatment accompanied by irradiation of charged particles. CONSTITUTION:A mask 32 is formed to have a desired pattern on a processed base substance 31 and the processed base substance 31 is selectively etched in accordance with the pattern of the mask 32 by a dry etching accomapnied by irradiation of charged particles 33. In such a case, the conductive organic materials are used as materials for the mask 32. Thus, even though charged beams are irradiated on the conductive materials of mask, an electric charge is not accumulated in the mask 32 and the above conductive materials prevent the mask 32 from being charged with electricity. In the case of dry etching, consequently no large potential is developed in the mask pattern and such a state of conductive organic materials helps avoid causing disturbance of an etching treatment form as well as deterioration of an insulating film quality on a base and the like which are due to the charged mask 32.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明龜、微細加工方法に係わり、特に荷電粒子の照射
を伴うドライエツチング技術を利用した微細加工方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a microfabrication method, and particularly to a microfabrication method using a dry etching technique involving irradiation with charged particles.

従来、半導体集積回路の¥J造工程等においては、微細
加工のための各種の工夫がなされている。工ッチングに
おいては、ウェットエツチングに代り、より高い寸法精
度のiSられるドライエツチングが用いられてきている
。さらに、エツチングの異方性を得るために、リアクテ
ィブ・イオン・エツチング(RIE)等のように荷電粒
子の照射を伴うドライエツチング技術が採用されている
Conventionally, in the manufacturing process of semiconductor integrated circuits, various techniques have been used for microfabrication. In etching, dry etching with higher dimensional accuracy has been used instead of wet etching. Furthermore, in order to obtain etching anisotropy, dry etching techniques involving irradiation with charged particles, such as reactive ion etching (RIE), are employed.

しかしながら、この種の方法にあっては、荷電粒子の照
射に伴う各種の問題が生じている。例えば、ホトレジス
トパターンをマスクに多結晶シリコン摸をドライエツチ
ング加工し、薄[I S ! 02(ゲート酸化膜)上
に多結晶シリコンパターンを形成する工程においては、
SiO2膜質が劣化し、絶縁耐圧不良か生じることが報
告されている。また、マスクパターンの帯電に起因する
と考えられるカ0工形状不良も認められている。
However, this type of method has various problems associated with charged particle irradiation. For example, a polycrystalline silicon sample is dry-etched using a photoresist pattern as a mask, and a thin [I S! In the process of forming a polycrystalline silicon pattern on 02 (gate oxide film),
It has been reported that the quality of the SiO2 film deteriorates, resulting in poor dielectric strength. In addition, defects in the shape of the die, which are thought to be caused by the charging of the mask pattern, have also been observed.

(発明が解決しようとする間舅点) このように従来方法では、荷電粒子の照射によりマスク
に帯電が生じ、この帯電に起因してエツチング加工形状
が乱れたり、下地の絶縁膜の膜質劣化が生じる等の問題
があった。
(The problem that the invention seeks to solve) In this way, in the conventional method, the mask is charged due to the irradiation of charged particles, and this charging causes the etched shape to be disturbed and the film quality of the underlying insulating film to deteriorate. There were some problems such as:

本発明は上記事情を考慮してなされたもので、その目的
とするところは、マスクの帯電に起因する各種の不都合
を解決することができ、良好なドライエツチングを行い
得る微細加工方法を提供することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to provide a microfabrication method that can solve various inconveniences caused by electrification of a mask and can perform good dry etching. There is a particular thing.

[発明の構成] (問題点を解決するための手段) 本発明の骨子は、荷電粒子の照射によるマスクの帯電を
防止するために、マスクを導電材料で形成することにあ
る。
[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to form a mask from a conductive material in order to prevent the mask from being charged by irradiation with charged particles.

即ち本発明は、被加工基体上に所望パターンにマスクを
形成し、荷電粒子の照射を伴うドライエツチングにより
上記被加工基体を上記マスクのパターンに従って選択的
にエツチングする微細加工方法において、前記マスクの
材料として、導電性の有償材料を用いるようにした方法
である。
That is, the present invention provides a microfabrication method in which a mask is formed in a desired pattern on a substrate to be processed, and the substrate to be processed is selectively etched according to the pattern of the mask by dry etching accompanied by irradiation of charged particles. This method uses a conductive paid material as the material.

ここで、マスクの帯電は基本的にはマスクを導電性材料
で形成することにより防止できるが、ドライエツチング
時に一般に用いられるマスクパターンが有償材料からな
るレジストパターンであることから、マスク材料として
有撮材料を用いるのが望ましい。また、導電性材料とし
ては、光導電性材料の如く、光の照射により導電性とな
るもの。
Here, charging of the mask can basically be prevented by forming the mask with a conductive material, but since the mask pattern generally used during dry etching is a resist pattern made of a paid material, commercially available photolithography is used as the mask material. It is desirable to use materials. Furthermore, the conductive material is one that becomes conductive when irradiated with light, such as a photoconductive material.

或いは光照射により導電率が向上するものであってもよ
い。なお、この光励起は、エツチング容器内での反応ガ
スによる発光に限らず、容器内或いは容器外に設けられ
た光源による光照射であってもよい。
Alternatively, the conductivity may be improved by light irradiation. Note that this optical excitation is not limited to light emission by the reaction gas within the etching container, but may also be light irradiation from a light source provided within or outside the container.

〈作用) 上記方法であれば、マスクが導電材料で形成されている
ので、荷電ビームの照射があっても、マスクに電荷の蓄
積が生じることはなく、マスクの帯電が防止される。そ
の結果、ドライエツチング時にマスクパターンに大きな
電位が生じることはなく、マスクの帯電に起因するエツ
チング加工形状の乱れや下地絶縁膜の膜質劣化等を防止
する°  ことが可能となる。
(Function) According to the above method, since the mask is made of a conductive material, even if the mask is irradiated with a charged beam, no charge is accumulated on the mask, and the mask is prevented from being charged. As a result, a large potential is not generated in the mask pattern during dry etching, and it is possible to prevent disturbances in the etched shape and deterioration of the underlying insulating film due to charging of the mask.

(実施例) 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第1図(a)〜(f)は本発明の一実施例方法に係わる
多結晶シリコンゲート形成工程を示す断面図である。な
お、この工程は、平坦化層、中間層及びレジストの、所
謂3層レジスト構造を用いた例である。
FIGS. 1(a) to 1(f) are cross-sectional views showing a polycrystalline silicon gate forming process according to an embodiment of the present invention. Note that this step is an example using a so-called three-layer resist structure including a flattening layer, an intermediate layer, and a resist.

まず、第1図(a)に示す如く、シリコン基板11上に
素子分離用絶縁膜12及びゲート酸化膜(Si○zjl
>13を形成し、これらの上に不純物添加多結晶シリコ
ンfl!14を形成した。その後、第1図(1))に示
す如く、光導電性を有する有償材料であるポリビニルカ
ルバゾールの簿膜15を、多結晶シリコン膜14に約1
.8[μTrL]の厚さにスピンコードにより形成し、
これを十分乾燥させた。続いて、この薄Pa15上にS
i3N4薄喚16を約500[人コの厚さに堆積した。
First, as shown in FIG. 1(a), an element isolation insulating film 12 and a gate oxide film (Si○zjl
>13 and doped polycrystalline silicon fl! on top of these. 14 was formed. Thereafter, as shown in FIG. 1 (1), a film 15 of polyvinylcarbazole, which is a paid material having photoconductivity, is applied to the polycrystalline silicon film 14 by about 100 ml.
.. Formed by spin code to a thickness of 8 [μTrL],
This was thoroughly dried. Next, apply S on this thin Pa15.
i3N4 thin film 16 was deposited to a thickness of approximately 500 cm.

さらに、この上にポジ型ホトレジスト17 (OFPR
−800、東京応化(株)製)を約1.25[μrrL
]の厚さに塗布した。
Furthermore, a positive photoresist 17 (OFPR
-800, manufactured by Tokyo Ohka Co., Ltd.) at approximately 1.25 [μrrL
] thickness.

次いで、通常のりソゲラフイエ程により、第1図(C)
に示す如く、レジスト17を露光・現象してレジストパ
ターンを形成した。その後、CF4/H2i1合ガスを
用いたRIEにより、第1図(d)に示す如く、レジス
ト17をマスクとして5iaN41J16を選択エツチ
ングした。続いて、レジスト17を除去したのち、02
ガスを用いたRIEにより、第1図(e)に示す如く、
Si3N4膜16をマスクとしてポリビニルカルバゾー
ル薄膜15を選択エツチングした。
Next, by the usual glue sogerahuie process, Fig. 1 (C)
As shown in FIG. 2, the resist 17 was exposed and developed to form a resist pattern. Thereafter, 5iaN41J16 was selectively etched by RIE using a CF4/H2i1 gas mixture, using the resist 17 as a mask, as shown in FIG. 1(d). Subsequently, after removing resist 17, 02
By RIE using gas, as shown in Fig. 1(e),
The polyvinylcarbazole thin film 15 was selectively etched using the Si3N4 film 16 as a mask.

次いで、CF4/H2混合ガスを用いたRIEにより5
i3N41116を完全に除去した。その後、CCQ+
 /He混合ガスを用いたRIEにより、第1図(f)
に示す如く、ポリビニルカルバゾール薄膜15をマスク
として下地多結晶シリコン膜14を選択エツチングした
。次いで、o2プラズマアッシングによりマスクパター
ンを全部除去し、多結晶シリコンゲートを形成した。
Then, by RIE using CF4/H2 mixed gas, 5
i3N41116 was completely removed. After that, CCQ+
Figure 1(f) was obtained by RIE using /He mixed gas.
As shown in FIG. 2, the underlying polycrystalline silicon film 14 was selectively etched using the polyvinyl carbazole thin film 15 as a mask. Next, the mask pattern was completely removed by O2 plasma ashing to form a polycrystalline silicon gate.

なお、上記5iiN41a16.ポリビニルカルバゾー
ル1illa15.多結晶シリコン膜14の各エツチン
グの際には、第2図に示す如き、平行平板21.22を
備えたドライエツチング装置を用いた。そして、被加工
基#i23をU置した下部重陽22側に高周波型812
4からの高周波電力を印加し、エツチング材料に応じた
ガスを供給しながらエツチングを行った。
In addition, the above 5iiN41a16. Polyvinylcarbazole 1illa15. For each etching of the polycrystalline silicon film 14, a dry etching apparatus equipped with parallel flat plates 21 and 22 as shown in FIG. 2 was used. Then, a high frequency type 812 is placed on the lower double positive 22 side where the workpiece #i23 is placed.
Etching was performed while applying high frequency power from No. 4 and supplying a gas depending on the etching material.

さて、本発明に係わる微細加工工程は、前記第1図(f
)に示すポリビニルカルバゾール薄膜15をマスクとし
た多結晶シリコン膜14の選択エツチングである。この
エツチングの際には、マスクであるポリごニルカルバゾ
ール 放電による発光によって導電性となる。従って、エツチ
ングの際に荷電粒子の照射があってもマスクに電荷が蓄
積されることは殆どなく、マスクの帯電は防止されるの
である。
Now, the microfabrication process according to the present invention is as shown in FIG.
This is selective etching of the polycrystalline silicon film 14 using the polyvinyl carbazole thin film 15 shown in ) as a mask. During this etching, the film becomes conductive due to light emission caused by polygonylcarbazole discharge, which serves as a mask. Therefore, even if the mask is irradiated with charged particles during etching, almost no charge is accumulated on the mask, and the mask is prevented from being charged.

ここで、マスクが導電性であることから、マスクに流入
した電荷は多結晶シリコン膜14を介してアース端等に
逃げるのである。また、多結晶シリコン膜14が完全に
エツチングされた場合、電荷の逃げ道がなくなるが、多
結晶シリコン11014が完全に分離されるまで電荷は
逃げているので、マスクに蓄積される電荷は極めて少な
い。このため、マスクに蓄積された電荷によりマスクと
基板11との間で放電等が生じることはなく、下地Si
O21J13の特性劣化等を招くことはない。
Here, since the mask is conductive, the charge flowing into the mask escapes to the ground end etc. via the polycrystalline silicon film 14. Furthermore, when the polycrystalline silicon film 14 is completely etched, there is no way for the charges to escape, but the charges continue to escape until the polycrystalline silicon 11014 is completely separated, so the amount of charge accumulated in the mask is extremely small. Therefore, electric charges accumulated in the mask do not cause discharge or the like to occur between the mask and the substrate 11, and the underlying Si
This does not cause deterioration of the characteristics of O21J13.

これに対し、従来のようにマスクが絶縁体であると、エ
ツチング中にマスク内に荷電粒子の照射により電荷が蓄
積される。そして、多結晶シリコン模14が完全に分離
した時点では、マスクに蓄積された電荷量は極めて多い
ものとなる。従って、多結晶シリコン摸14が完全に分
離した時点で、マスクに蓄積された電荷により、マスク
と基板11との間に放電が生じる虞れがあり、この放電
により下地SiO2膜13の絶縁耐圧不良等を招くこと
になる。
On the other hand, if the mask is an insulator as in the prior art, charges will be accumulated in the mask during etching due to the irradiation of charged particles. When the polycrystalline silicon model 14 is completely separated, the amount of charge accumulated in the mask becomes extremely large. Therefore, when the polycrystalline silicon pattern 14 is completely separated, there is a possibility that a discharge will occur between the mask and the substrate 11 due to the charge accumulated in the mask, and this discharge will cause a breakdown in the dielectric strength of the underlying SiO2 film 13. etc. will be invited.

このように本実施例方法によれば、多結晶シリコン膜1
4をRIEで選択エツチングする際のマスクとしてポリ
ビニルカルバゾール薄膜15を用いているので、マスク
の帯電を未然に防止することができ、ゲート酸化I11
3の特性劣化をなくすことができる。また、マスクの帯
電がないことから、マスクに蓄積された電荷によりイオ
ンが曲げられる等の不都合もなく、良好なエツチング加
工形状を得ることができる。
In this way, according to the method of this embodiment, the polycrystalline silicon film 1
Since the polyvinyl carbazole thin film 15 is used as a mask when selectively etching 4 by RIE, it is possible to prevent the mask from being charged, and the gate oxidation I11
It is possible to eliminate the characteristic deterioration described in No. 3. Furthermore, since the mask is not electrically charged, there is no problem such as bending of ions by charges accumulated in the mask, and a good etched shape can be obtained.

なお、上記加工形状に関する効果は、トレンチ溝等の7
スベクト比の大きい溝形成において特に有効である。即
ち、第3図(a)に示す如くシリコン基板31上にマス
ク32を形成し、RIE等によりシリコン基板31を選
択エツチングしてアスペクト比の大きい溝を形成する場
合、マスク32が導電性であると、イオン33の照射に
よってもマスク32の帯電が生じることはない。このた
め、イオン33は溝内に垂直に照射され、これにより垂
直エツチングが可能となる。
Note that the effects related to the above-mentioned processed shape are as follows: 7.
This is particularly effective in forming grooves with a large velocity ratio. That is, when a mask 32 is formed on a silicon substrate 31 as shown in FIG. 3(a) and a groove with a large aspect ratio is formed by selectively etching the silicon substrate 31 by RIE or the like, the mask 32 is conductive. Also, the mask 32 is not charged even by the irradiation of the ions 33. Therefore, the ions 33 are irradiated vertically into the groove, thereby making vertical etching possible.

これに対し、マスク32が絶縁体であると、イオン33
の照射によってマスク32が帯電する。
On the other hand, if the mask 32 is an insulator, the ions 33
The mask 32 is charged by the irradiation.

マスク32が帯電すると、第3図(b)に示す如く溝内
に入射するイオン33はマスク32の電荷により曲げら
れる。このため、垂直で深い溝を形成することが困難と
なるのである。
When the mask 32 is charged, the ions 33 entering the groove are bent by the charge of the mask 32, as shown in FIG. 3(b). This makes it difficult to form vertical and deep grooves.

なお、本発明は上述した実施例方法に限定されるもので
はない。例えば、前記マスクとして用いる材料は、ポリ
ビニルカルバゾール等の光導電性を有する有菌材料に限
るものではなく、ポリアセチレン等の導電性の有殿材r
4であってもよい。ざらに、マスクとして光導電性の有
線材料を用いた場合、該材料に対する光照射をより確実
にするために、エツチング容器の外部に光源を設け、こ
の光源から上記材料の導電性が向上する波長域の光を照
射するようにしてもよい。また本発明は、多結晶シリコ
ン摸の選択エツチングに限らず、伯の材料の選択エツチ
ングに適用することが可能である。さらに、エツチング
方法としてはRIEに限るものではなく、荷電粒子の照
射を伴う各種のドライエツチングに適用することが可能
である。その他、本発明の要旨を逸脱しない範囲で、種
々変形して実施することができる。
Note that the present invention is not limited to the method of the embodiment described above. For example, the material used for the mask is not limited to a photoconductive sterile material such as polyvinylcarbazole, but also a conductive precipitated material such as polyacetylene.
It may be 4. Generally speaking, when a photoconductive wired material is used as a mask, in order to ensure that the material is irradiated with light, a light source is provided outside the etching container, and from this light source a wavelength that improves the conductivity of the material is emitted. Alternatively, the area may be irradiated with light. Furthermore, the present invention can be applied not only to selective etching of polycrystalline silicon but also to selective etching of glass materials. Furthermore, the etching method is not limited to RIE, but can be applied to various dry etching methods that involve irradiation with charged particles. In addition, various modifications can be made without departing from the gist of the present invention.

[発明の効果] 以上詳述したように本発明によれば、荷電粒子の照射を
伴う選択エツチングに際し、マスクとして導電性の有線
材料を用いることにより、マスクの帯電を防止すること
ができ、良好なエツチングを行うことができる。
[Effects of the Invention] As detailed above, according to the present invention, by using a conductive wired material as a mask during selective etching that involves irradiation with charged particles, it is possible to prevent the mask from being charged. Etching can be performed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は本発明の一実施例方法に係わる
多結晶シリコンゲート形成工程を示す所面図、第2図は
上記実施例方法に用いたドライエツチング装置の概略構
成を示す模式図、第3図(a)(b)はマスクの帯電に
よる問題を説明するための模式図である。 11.31・・・シリコン基板、12・・・素子分離用
絶縁膜、13・・・ゲート酸化膜(S i 02 FA
)、14・・・多結晶シリコン膜、15・・・ポリビニ
ルカルバゾール簿膜(導電性有機材料)、16・・・S
1ヨN4膜、17・・・ホトレジスト、21.22・・
・平行平板電穫、23・・・被加工基板、24・・・高
周波電源、32・・・マスク、33・・・イオン。 出願人代理人 弁理士 鈴江武彦 ムS1 口 第1図 築 2図 (a) 第31 (b) 図
FIGS. 1(a) to (f) are top views showing the polycrystalline silicon gate forming process according to one embodiment of the present invention, and FIG. 2 is a schematic diagram of the dry etching apparatus used in the above embodiment method. The schematic diagrams shown in FIGS. 3(a) and 3(b) are schematic diagrams for explaining problems caused by charging of the mask. 11.31... Silicon substrate, 12... Insulating film for element isolation, 13... Gate oxide film (S i 02 FA
), 14... Polycrystalline silicon film, 15... Polyvinyl carbazole film (conductive organic material), 16... S
1yoN4 film, 17...photoresist, 21.22...
・Parallel plate electrophotography, 23... Processed substrate, 24... High frequency power source, 32... Mask, 33... Ion. Applicant's representative Patent attorney Takehiko Suzue S1 Figure 1 Figure 2 (a) Figure 31 (b)

Claims (6)

【特許請求の範囲】[Claims] (1)被加工基体上に所望パターンにマスクを形成し、
荷電粒子の照射を伴うドライエッチングにより上記被加
工基体を上記マスクのパターンに従つて選択的にエッチ
ングする微細加工方法において、前記マスクの材料とし
て、導電性の有機材料を用いたことを特徴とする微細加
工方法。
(1) Form a mask in a desired pattern on the substrate to be processed,
A microfabrication method in which the substrate to be processed is selectively etched according to the pattern of the mask by dry etching accompanied by irradiation with charged particles, characterized in that a conductive organic material is used as the material of the mask. Microfabrication method.
(2)前記導電性の有機材料として、ポリアセチレンを
用いたことを特徴とする特許請求の範囲第1項記載の微
細加工方法。
(2) The microfabrication method according to claim 1, wherein polyacetylene is used as the conductive organic material.
(3)前記マスク材料として、光の照射により導電性と
なる若しくはその導電率が高くなる光導電性を有する有
機材料を用いたことを特徴とする特許請求の範囲第1項
記載の微細加工方法。
(3) The microfabrication method according to claim 1, characterized in that, as the mask material, an organic material having photoconductivity that becomes conductive or has high conductivity upon irradiation with light is used. .
(4)前記光導電性を有する有機材料として、ポリビニ
ルカルバゾールを用いたことを特徴とする特許請求の範
囲第3項記載の微細加工方法。
(4) The microfabrication method according to claim 3, wherein polyvinylcarbazole is used as the organic material having photoconductivity.
(5)前記マスクは、前記エッチングの前或いはエッチ
ング中に、該マスクを形成する材料の導電性が向上する
波長域の光が照射されることを特徴とする特許請求の範
囲第3項記載の微細加工方法。
(5) The mask is irradiated with light in a wavelength range that improves the conductivity of the material forming the mask before or during the etching. Microfabrication method.
(6)前記マスクは、凹凸を有する被加工基体上に平坦
化層、中間層及びレジストを形成した多層レジスト構造
の最下層となる平坦化層であり、パターニングされた上
記レジストをマスクとして上記中間層を選択エッチング
し、この中間層をマスクとして上記平坦化層を選択エッ
チングして形成されることを特徴とする特許請求の範囲
第1項記載の微細加工方法。
(6) The mask is a flattening layer that is the lowest layer of a multilayer resist structure in which a flattening layer, an intermediate layer, and a resist are formed on a substrate having irregularities, and the patterned resist is used as a mask to form the intermediate layer. 2. The microfabrication method according to claim 1, wherein said layer is selectively etched, and said planarization layer is selectively etched using said intermediate layer as a mask.
JP16502586A 1986-07-14 1986-07-14 Fine processing Pending JPS6320830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16502586A JPS6320830A (en) 1986-07-14 1986-07-14 Fine processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16502586A JPS6320830A (en) 1986-07-14 1986-07-14 Fine processing

Publications (1)

Publication Number Publication Date
JPS6320830A true JPS6320830A (en) 1988-01-28

Family

ID=15804412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16502586A Pending JPS6320830A (en) 1986-07-14 1986-07-14 Fine processing

Country Status (1)

Country Link
JP (1) JPS6320830A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04340717A (en) * 1991-05-17 1992-11-27 Sharp Corp Manufacture of semiconductor device
US5994007A (en) * 1997-12-19 1999-11-30 Kabushiki Kaisha Toshiba Pattern forming method utilizing first insulative and then conductive overlayer and underlayer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5796333A (en) * 1980-12-09 1982-06-15 Fujitsu Ltd Production of substrate for exposure of charged beam
JPS57192264A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Method of etching
JPS59116745A (en) * 1982-12-24 1984-07-05 Fujitsu Ltd Formation of pattern

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5796333A (en) * 1980-12-09 1982-06-15 Fujitsu Ltd Production of substrate for exposure of charged beam
JPS57192264A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Method of etching
JPS59116745A (en) * 1982-12-24 1984-07-05 Fujitsu Ltd Formation of pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04340717A (en) * 1991-05-17 1992-11-27 Sharp Corp Manufacture of semiconductor device
US5994007A (en) * 1997-12-19 1999-11-30 Kabushiki Kaisha Toshiba Pattern forming method utilizing first insulative and then conductive overlayer and underlayer

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