JPS6320639A - Memory access controller - Google Patents

Abstract

PURPOSE:To improve the processing performance by suppressing the data write to a cache memory and by-passing the cache memory to write data in a main storage device if a memory access request as the write request from processor fails to hit the cache. CONSTITUTION:A rewrite control part RE WRT CNT 10B, a write suppression control part WRT ST CNT 110 for a DA CNT 108, a timing priority control part TMG CNT 10E, and a data line BYPS 10F are provided. The memory read command which is generated in a read control part (RD CNT) 10A by the cache mishit processing and is sent to a main storage device (MMU) 102 is converted to a memory rewrite command by the rewrite control part (RE WRT CNT) 10B. This memory rewrite command has the timing controlled and is selected by the timing priority control part (TMG CNT) 10E and is sent to the MMU 102. Merge data stored in a swap data buffer SDB 107 is written in a prescribed address of the MMU 102, and the timing of the TMG CNT 10E is sent to the MMU 102 through a register ADR 10C.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention has a store-in type cache memory,
Regarding a memory access control device that executes data transfer between a main storage device and a main storage device using block data,
A memory access request that is a miss-hit write request is
The present invention relates to a processing control method for memory read data when all cache memory is being flushed out.

[Conventional technology]

In conventional memory access control devices, when a memory access request from a processing device results in a cache miss, block data is transferred to and from the main storage device. If the memory access request is a write request, it will be merged with the write data from the request source, and one will be written to the cache memory. Here, when there is a write request for a cache miss during the process of flushing out all cache memory data, the data obtained by merging the memory read data and the write data from the request source is - once canceled. It was written in memory.

FIG. 2 is a block diagram showing the entire general computer system. In the memory access control unit (hereinafter referred to as SIU) 201, each processing unit (hereinafter referred to as central processing unit, CPU, and input/output processing unit) is called IOP)2
03. When a memory access request is received from the bunker 204,
Processing is performed according to the first priority, and the main memory (hereinafter referred to as MM
A memory access request is sent to U')) 202.

If the memory access request is a write request, the write data f is written to the corresponding address of the MMU 202, and if the memory access request is a read request, the data at the corresponding address of the MMU 202 is read out and sent to the requesting process via the 5IU 201e. returned to the device.

In this 8IU 201, when a cache memory is provided for the purpose of improving the performance of memory access processing and reducing the load on the MMU 202, the CPU 203, l0
A memory access request from P204 has a probability of 90% or more when there is a cache hit, and processing for the request can be executed without going through the ΔL'b1tJ202. and swap out the block data and write the latest data to the cache memory.

The memory access processing is performed by the other system memory access control device 5IU211, the IU212 to the main storage device M, and the processing device CPU213. The same applies to l0P214.

In the computer system, when the 5IU 201 is disconnected due to a failure or other cause, when the 5IU 201 is connected, the cache memory data in the 5IU 201 is
Exposure processing to the MU 202 is required.

At this point, the CPU 203 or CPU 213 issues a cache memory data flushing instruction, and the cache memory data at the corresponding address according to the flushing instruction is
FIG. 3 is a block diagram of a conventional memory access control device.

CPU203. If a memory access request, which is a write request from l0P204, causes a cache miss, the third
In the memory access control device 5IU301 shown in the figure,
A memory data read command is issued to the MMU 302 under the control of the read control unit (hereinafter referred to as RD CNT) 30A. In response to the read command, the MMU 302 reads the data (block data) at the corresponding address, and reads 8IU3.
01.

The 5IU 301 recognizes the timing of data rewriting from the MMU 302, and when memory read data is accepted, it merges it with the write data stored in the mishit store data buffer (hereinafter referred to as MSDB) 3o3. Cache memory control unit (hereinafter referred to as DA) via memory data register (hereinafter referred to as MDR) 3ost
The merged data is written into the cache memory (hereinafter referred to as DA) 306 under the control of the CNT controller 308 . At this time, if it is necessary to swap out the DA306 data, read out the data of the relevant DA306 and store it in the swap data buffer (hereinafter referred to as SDR) 30.
7 and write control unit (hereinafter referred to as WRTCNT)
309 to the MMU 302 according to the memory write command.

The above is the process when a memory access request, which is a write request, causes a cache miss. If the request is accepted while all cache memory DA306 data is being written out, after writing data to the DA306, The data of DA306 of the corresponding address is WRT CNT
The data is output to the MMU 302 under the control of the controller 309 . In other words, when writing data (block data) to the DA 306, the DA 306 is used.
Block data writing process to A306 and D of the same data
Block data read processing from A306 is required.

[Problems to be Solved by the Invention] The conventional memory access control device described above performs block data transfer with the main storage device when a memory access request from the processing device causes a cache miss.
If the memory access request is a write request, the memory read data at this time is merged with the write data from the request source.
It will be written to cache memory.

Here, even though all cache memory data is being read out, if there is a memory access request that is a write request from the processing device and a cache miss occurs, the memory read data and the write request from the request source are Since the merged data with the data is written to the cache memory IjK once -, after the data is merged, the block to the cache memory must be sent out as the write data to the main storage device. There is a drawback that data writing processing and reading processing of the same block data must be performed, which takes time.

[Means for solving problems]

The memory access control device of the present invention has a store-in type cache memory, and when a memory access request from a processing device is a cache miss, data transfer to and from the main storage device is performed in units of a predetermined data length. , in a memory access control device that executes, there is a memory access request that is a write request from the processing device during the process of flushing out all cache memory data, and a memory corresponding to a memory read command issued when a cache miss occurs. write inhibiting means for inhibiting writing of cache memory write data obtained by merging read data and write data from the processing device to the cache memory; Swap data buffer storage data selection means for selecting data to be stored in the swap data buffer by selecting the data to be stored in the swap data buffer;
command converting means for converting the memory read command into a memory rewrite command in order to swap out data stored in the swap data buffer to the main storage device; and a memory access request means for selecting a memory write command and a memory re-attachment command converted by the command conversion means and transmitting the selected memory access command to the main storage device, and the memory access request means selects a memory write command and a memory re-attachment command converted by the command conversion means, and sends the selected memory access request means to the main storage device. If there is a memory access request x, which is a write request from the device, and a cache miss occurs fC, all data writing to the cache memory is inhibited, the cache memory is bypassed, and the write data to the cache memory is is configured by swapping it out to main storage.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The main difference from the conventional device is the rewrite control section (hereinafter referred to as RE).
WRT CNT) 10B, DA CNT10
8 write inhibition control unit (hereinafter referred to as WRT 5TCNT)
)110. This is because a timing priority control section (hereinafter referred to as TMG CNT) IOE and a data line (hereinafter referred to as BYP8) xoFffi are provided.

The processing when a memory access request, which is a general write request, results in a cache miss hint is similar to the operation described in FIG. 3. When the memory access request causes a cache miss, the RD CNT10A causes the ΔiMU
A memory read command is sent to i02, and the MMU 102 receives the memory read command, reads the data at the corresponding address, and sends it to 5IUIOI. When memory read data is accepted in 5ItJ101, MSDB10
3K stored write data (hereinafter abbreviated as merge data), via MDR105, DA CN
Under the control of T108, the merge data is written to the cache memory DA106.

If it is necessary to swap out DA106 data, read the relevant DA106 data and write it to WRTCNT10.
The memory write command from 9 sends it to the MMU 102.

The following describes the operation when the memory access request, which is the write request, is not accepted during the process of flushing out all cache memory data and a cache miss occurs.

When mode register (hereinafter referred to as SMDR 5) 10D receives this output instruction, WR in DA CNT108
Under the control of T ST CNTll0, writing of the merge data to DA106 is suppressed, and the data is written to BY
Bypassing DA106 via PSIOF, this merged data is selected (under control of RE WRT CNT10B) and stored in 5DRIQ7. (This merge data is block data). Created in RD CNTIQA by cache miss processing and closed MMU
The memory read command sent to 102 is RE WRT.
It is converted into a memory rewrite command at CNT10B.

This memory rewrite command is selected with timing controlled by T M GCNTIOEK, and MMtJ 102
will be sent to. TMG CNT10E recognizes the data reply timing from MMLI 102 in the event of a cache-miss, and takes this into consideration when transmitting MMLI 1
Controls the selection timing of the memory rewrite command to 02. The merge data stored in the SDB 107 is written to a predetermined address of the MMU 102 in accordance with this memory rewrite command.

TMG CNT10E selects the - command from among the memory read command, the converted memory rewrite command, and the memory write command by controlling the timing and priority, and the selected command is sent via the register ADH100. and sent to MMU 102.

As described above, in this embodiment, if there is a memory access request that is a write request during the process of flushing all cache memory data, and the request results in a cache miss, data writing to the cache memory is inhibited and the cache memory IJ t is
It can be written into the main memory K by bypass.

〔Effect of the invention〕

As explained above, the present invention provides a memory access control device that has a cache memory and transfers data to and from a main storage device using block data when a memory access request from a processing device causes a cache miss. , If a memory access request, which is a write request from the processing device, occurs during the process of flushing out all cache memory data, and the request results in a cache miss, data writing to the cache memory is inhibited, and the cache memory By bypassing the block data and writing it to the main memory, it is possible to omit the process of writing block data to the cache memory and reading the same data, eliminate time loss in the write process, and improve processing performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a computer system, and FIG. 3 is a block diagram showing a conventional device. 101...Memory access control unit (SIU), 10
2... Main memory unit (MMU), 103... Mishit store data buffer completed (MSDB), 104...
・Memory data register (MDR), 1os...
Memory data register (MDR), 106... Cache memory (DA), 107... Swap data buffer (SDB), 108... Cache memory control unit (DACNT), 109... Write control unit (WRT)
CNT), 110...Write inhibit control unit (WRT
ST CNT), 1oA-...Read control unit (RD
CNT), 10 B--Rewrite control unit (RE WR
T CNT), l0C-=M-[- re-access register (ADR), IOD... mode register (SMDR
), 10E...timing/priority control section (
TMG CNT), IOF...Data line (BYPS
), 201... memory access control unit (SIU),
202... Main memory unit (MMU), 203... Processing unit (CPU), 204... Processing unit (IOP), 2
11...Memory access control unit (SIU), 212
...Main storage device (MMU), 213... Processing unit (CPU), 214... Processing unit (IOP), 30
1...Memory access control unit (SIU), 302.
...Main memory unit (MMU), 303...Miss store data buffer (MSDB), 304...Memory data register (MDR), 305...Memory data register (MDR), 306...Cache memory (
DA), 307 --- Swap data buffer (SDB
), 308...cache memory control unit (DAC
NT), 309...Write control unit (WRT CNT)
, 30A...read control unit (RDCNT), 30B...
-Memory access register (ADR), 30C...Mode register (SMDR). 7-ゝFigure 7 M2

Claims (1)

[Claims] It has a store-in type cache memory, and when a memory access request from a processing device results in a cache miss, data transfer to and from the main storage device is performed in units of a predetermined data length. In the memory access control device, there is a memory access request, which is a write request, from the processing device during the flushing process of all cache memory data;
Write inhibition for inhibiting writing of cache memory write data into the cache memory, which is a merge of memory read data corresponding to a memory read command issued in the event of a cache mishit and write data from the processing device. swap data buffer storage data selection means for selecting the cache memory write data as data to be stored in the swap data buffer bypassing the cache memory; command converting means for converting the memory read command into a memory rewrite command in order to swap out; and a command converting means for converting the memory read command into a memory rewrite command; and memory access request means for selecting a memory rewrite command and sending it to the main storage device, wherein a memory access request, which is a write request, is received from the processing device while all cache memory data is being written out; A memory access control device characterized in that when a cache mishit occurs, data writing to the cache memory is inhibited, the cache memory is bypassed, and the cache memory write data is swapped out to a main storage device.