JPS63204626A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To manufacture a device with an excellent noise property having a region not affected by any active elements by providing an element forming region isolated from a semiconductor substrate. CONSTITUTION:N type epitaxial layers 2 in specific resistance of severalOMEGA.cm- several +OMEGA.cm are formed on the overall surface of P type semiconductor substrate 1 including a P type buried layer 9 provided on an N type buried layer 8. Furthermore, P type insulating isolation layers 3A in contact with the peripheral part of P type buried layer 9 are provided from the surface of epitaxial layers 2 while the layers 3A are connected to the lowest potential electrode 10B as an outer leading out electrode. Thus, a region formed into an N<+>type resistance layer 4 is isolated from other regions by the P type buried layer 9 and the P type insulating isolation layers 3A to prevent a current from running therein due to potential raise in the P type semiconductor substrate 1. Through these procedures, a semiconductor device with excellent noise property having a region not affected by any active elements can be manufactured.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device.

[Conventional technology]

A method for extracting the lowest potential electrode of a semiconductor integrated circuit device composed of conventional analog bipolar elements will be described with reference to FIG.

An N-type epitaxial layer 2 is provided on a P-type semiconductor substrate 1,
A plurality of island regions made of N-type epitaxial layers 2 are provided by selectively providing a P-type insulating isolation layer 3.

Next, an N+ type low resistance layer 4 is provided in one of the island regions,
An insulating film 5 is provided on the surface and openings are selectively opened, and N″″
An electrode 6 extending from the resistive layer 4 and a lowest potential electrode 7 connected to the P-type insulating separation layer 3 are provided at the same time.

[Problem that the invention seeks to solve]

The above-described conventional island region element consisting of an N-type epitaxial island has a P-type semiconductor substrate 1 connected to the lowest potential electrode 7.
Since it is directly connected to the P-N junction with the P-type semiconductor substrate 1, current flowing to the P-type semiconductor substrate 1 from active elements provided on other N-type epitaxial islands, such as NPN transistors, lateral PNP transistors, sub-PNP transistors, etc.
A local potential rise occurs around the element, causing an abnormal potential in the N+ type resistance region. For example, N+ type low resistance layer 4
When the potential reaches the lowest potential, the potential temporarily rises from the lowest potential due to the current flowing to the P-type semiconductor substrate 1, resulting in a disadvantage that the circuit does not operate normally.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a semiconductor integrated circuit device having a region not affected by active elements and having good noise characteristics.

[Means for solving problems]

A semiconductor integrated circuit device of the present invention includes: a buried layer of opposite conductivity type selectively formed on a semiconductor substrate of one conductivity type; a buried layer of one conductivity type provided on the buried layer of opposite conductivity type; an epitaxial layer of opposite conductivity type provided on the entire surface including the buried layer of one conductivity type; and an insulating separation layer of one conductivity type not provided in contact with the outer periphery of the buried layer of one conductivity type from the surface of the epitaxial layer;
The insulation portion Ii! It is configured to include an external extraction electrode connected to the i-layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

In FIG. 1, an N-type buried layer 8 is selectively provided on a P-type semiconductor substrate 1, and a P-type buried layer 9 is provided on this N-type buried layer 8. . An N-type epitaxial layer 2 having a resistivity of several Ω·cm to several tens of Ω·C is formed on the entire surface including this P-type buried layer 9, and a P-type epitaxial layer 2 is formed from the surface of this epitaxial layer 2. A P-type insulating separation layer 3A is provided in contact with the outer periphery of the buried layer 9. This P-type insulating separation layer 3A is connected to the lowest potential electrode 10B as an electrode for external extraction.

In FIG. 1, 3 is a P-type insulating separation layer that connects the P-type semiconductor substrate 1 and the lowest potential electrode 10A, 11 is a high-potential electrode that is connected to the N++ extraction layer 16, and 4 is an N+-type low resistance layer. Layer 6 is a metal wiring, and layer 5 is an insulating film. The lowest potential electrodes 10A and 10B are connected to separate external bonding pads or to the same bonding pad. The high potential electrode 11 is connected to a wiring having a higher potential than the P-type semiconductor substrate 1.

In the first embodiment configured in this way, the region where the N1 type resistor N4 is formed is located between the P type buried layer 9 and the P type buried layer 9.
Since it is separated from other regions by the type insulating separation layer 3A, there is no flow of current due to an increase in the potential of the P-type semiconductor substrate 1. Therefore, the element formed by the N1 type resistance layer 4 operates normally.

FIG. 2 is a sectional view of a second embodiment of the invention.

While in FIG. 1 there is an N+ type low resistance layer, this second embodiment has a P type paper layer 12, an N++ layer 13, a P type resistive high potential electrode 14, and a P type resistive low potential electrode 15. This is the case when it is set. This second embodiment has the advantage that a high resistance element can be used, and the P-type paper antilayer 12 has the advantage that it is not affected by potential changes of the P-type semiconductor substrate 1 at the P-type resistance high potential electrode 14.

〔Effect of the invention〕

As explained above, the present invention provides an element formation region separate from the semiconductor substrate, thereby making it possible to provide a region that is not affected by fluctuations in substrate potential due to active elements, and thereby providing a semiconductor integrated circuit device with good noise characteristics. There are benefits to be gained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a first embodiment of the present invention, FIG. 2 is a sectional view showing a second embodiment of the invention, and FIG. 3 is a sectional view of an example of a conventional semiconductor integrated circuit device. be. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type epitaxial layer, 3, 3A... P-type buried layer, 4... N+ type low resistance layer 5... Insulating film, 6... Metal Wiring, 7: lowest potential electrode, 8: N-type buried layer, 9: P-type buried layer,
10A.

Claims (1)

[Claims] A buried layer of opposite conductivity type selectively formed on a semiconductor substrate of one conductivity type, a buried layer of one conductivity type provided on the buried layer of opposite conductivity type, and the buried layer of one conductivity type. an epitaxial layer of opposite conductivity type provided on the entire surface, an insulating separation layer of one conductivity type provided from the surface of the epitaxial layer to the outer circumference of the buried layer of one conductivity type, and an external connection connected to the insulating separation layer. 1. A semiconductor integrated circuit device comprising: