JPH04144164A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a destruction of a resistance element by an excessive voltage by a method wherein, at a bottom of an island region respectively corresponding to a plurality of resistance layers provided within a single island region, a plurality of embedded layers divided corresponding to the respective resistance layers are formed. CONSTITUTION:A P type diffused layer 4 is formed on an N type epitaxial layer 3 to section an island region containing N type embedded layers 2a, 2b. P type resistance layers 5a, 5b are formed corresponding to the N type embedded layers 2a, 2b, respectively. Next, insulating layers 6 are laminated and holes are selectively opened in the insulating layers 6 on the resistance layers 5a, 5b to form a contact window 7. Metallic layers are laminated on a surface containing the contact window 7 and selectively etched to form wirings 8a, 8b and wirings 9a, 9b which are respectively connected to the resistance layers 5a, 5b of the contact window and which extend on the insulating layers 6. Here. the wirings 8a, 8b are connected to external terminals, and when an excessive voltage is applied, even if a current flows from the resistance layer 5a to the N type embedded layer 2a directly thereunder, the N type embedded layer 2b is divided and a current does not flow to the resistance layer 5b, whereby a resistance is not destructed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of resistive layers within the same island region.

[Conventional technology]

In the conventional semiconductor device, as shown in FIGS. 2(a) and 2(b), a high concentration N-type buried layer 2 is selectively formed on a P-type silicon substrate 1. An N-type epitaxial layer 3 is grown on the surface including the N-type epitaxial layer 3, and a P-type diffusion layer 4 for element isolation reaching the P-type silicon substrate 1 is selectively provided on the N-type epitaxial layer 3 to electrically connect the N-type epitaxial layer 3. separate and form island regions. P-type impurities are selectively diffused into the island region, and a plurality of resistance layers 5a and 5b are formed so as not to protrude from above the N-type buried layer 2. The resistive layers 5a, 5b are connected through contact windows 7 formed by selectively opening the insulating layer 6 deposited on the surface including the resistive layers 5a, 5b.
Wirings 8a, 8b and 9a, 9b connected to the insulating layer 6 and extending above the insulating layer 6 are formed.

The N-type buried layer 2 uses the P-type paper anti-layers 5a and 5b as emitters, and the N-type
It is formed to prevent the operation of a parasitic PNP (PNP) transistor with the P-type epitaxial layer 3 as the base and the P-type silicon substrate 1 as the collector.

[Problem to be solved by the invention]

In this conventional semiconductor device, when multiple resistance layers connected to external terminals are formed in one island region, when the external terminals are exposed to excessive voltage due to surge or static electricity, current flows from one resistance layer directly below the resistance layer. There was a problem in that the resistor was destroyed by passing through the buried layer and then through the route to the other resistor layer.

[Means to solve the problem]

The semiconductor device of the present invention includes an island region of opposite conductivity type formed on a semiconductor substrate of − conductivity type, a plurality of buried layers of opposite conductivity type dividedly provided at the bottom of the island region, and the buried layer. and a resistance layer of one conductivity type provided on the surface of the island region within the region of the buried layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line A-A' of a semiconductor chip showing an embodiment of the present invention.

As shown in FIGS. 1A and 1B, heavily doped N-type buried layers 2a and 2b are selectively formed on a P-type silicon substrate 1. As shown in FIGS. Next, an N-type epitaxial layer 3 is formed on the surface including the N-type buried layer 2a2b, and a P-type epitaxial layer 3 is formed on the N-type epitaxial layer 3.
A P-type diffusion layer 4 reaching the silicon substrate] is formed to partition an island region including N-type buried layers 2a and 2b, and
A P-type resistance layer 5a corresponds to each of the type buried layers 2a and 2b.
, 5b. Next, an insulating layer 6 is deposited on the surface including the resistance layers 5a and 5b, contact windows 7 are provided by selectively opening holes in the insulating layer 6 on the resistance layers 5a and 5b, and metal is deposited on the surface including the contact windows 7. The layers are deposited and selectively etched to form wires 8a, 8b and wires 9a9b which connect to the resistive layers 5a, 5b of the contact windows, respectively, and extend over the insulating layer 6.

Here, when the wirings 8a and 8b are connected to external terminals and an excessive voltage is applied, the N-type buried layer 2 immediately below the resistance layer 5a
Even if current flows through a, the N-type buried layer 2b is divided,
It does not leak into the other resistance layer 5b and the resistor is not destroyed.

〔Effect of the invention〕

As explained above, in the present invention, a plurality of buried layers are formed at the bottom of an island region corresponding to each of the plurality of resistance layers provided in one island region. This has the effect that destruction of the resistance element due to excessive voltage can be prevented.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view taken along line A-A' of a semiconductor chip showing an embodiment of the present invention, and FIG. 2(a>,
(b) is a plan view and a sectional view taken along the line BB' of a semiconductor chip showing an example of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2.2a, 2b... N-type buried layer, 3... N-type epitaxial layer, 4... P-type diffusion layer, 5a, 5b... resistance layer, 6... Insulating layer, 7
...Contact window, 8a, 8b, 9a, 9b-wiring.

Claims (1)

[Claims] an island region of opposite conductivity type formed on a semiconductor substrate of one conductivity type; a plurality of buried layers of opposite conductivity type provided separately at the bottom of the island region; A semiconductor device comprising: a resistance layer of one conductivity type provided on the surface of the island region within the region of the buried layer.