JPS6320393B2 - - Google Patents

Info

Publication number
JPS6320393B2
JPS6320393B2 JP14677481A JP14677481A JPS6320393B2 JP S6320393 B2 JPS6320393 B2 JP S6320393B2 JP 14677481 A JP14677481 A JP 14677481A JP 14677481 A JP14677481 A JP 14677481A JP S6320393 B2 JPS6320393 B2 JP S6320393B2
Authority
JP
Japan
Prior art keywords
type
layer
mesa
cladding layer
inp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14677481A
Other languages
Japanese (ja)
Other versions
JPS5848491A (en
Inventor
Ikuo Mito
Mitsuhiro Kitamura
Isao Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP14677481A priority Critical patent/JPS5848491A/en
Publication of JPS5848491A publication Critical patent/JPS5848491A/en
Publication of JPS6320393B2 publication Critical patent/JPS6320393B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching

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  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 本発明は活性層以外に流れる漏洩電流を極力低
減することにより、高光出力、高温連続動作が可
能な埋め込み形半導体レーザに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buried semiconductor laser capable of high optical output and continuous operation at high temperatures by minimizing leakage current flowing outside the active layer.

埋め込み形半導体レーザは、低発振閾値を示し
駆動電流が小さく、又出射ビームが等方的であ
り、光フアイバとの結合に有利である等、光フア
イバ通信用光源に適している。筆者等は、特願昭
55−123261に記す様に、内部に活性層を含むメサ
ストライプの側面にPn半導体層を形成し、埋め
込み形半導体レーザで問題となる漏洩電流を少く
する構造を発明し、InPを基板とするInGaAsP埋
め込み形半導体レーザとして、最小発振閾値8.5
mA、最高連続動作温度100℃に得た。しかしな
がら、この構造の埋め込み形半導体レーザでは、
メサ周辺部におけるPnPn構造のターン・オン電
圧が漏洩電流を完全に防止する程高くはなく、半
導体レーザに印加する順方向バイアス電圧が高く
なるにつれ、PnPn層を通して流れる漏洩電流が
増加し、高注入電流時での光出力の飽和、あるい
は高温領域における発振閾値の急増という傾向が
見られた。
Embedded semiconductor lasers are suitable as light sources for optical fiber communication because they exhibit a low oscillation threshold, require a small drive current, and emit an isotropic beam, which is advantageous for coupling with optical fibers. The authors are
55-123261, he invented a structure in which a Pn semiconductor layer is formed on the side surface of a mesa stripe containing an active layer to reduce leakage current, which is a problem in buried semiconductor lasers, and developed InGaAsP with an InP substrate. Minimum lasing threshold of 8.5 as an embedded semiconductor laser
mA, and a maximum continuous operating temperature of 100°C was obtained. However, in the embedded semiconductor laser with this structure,
The turn-on voltage of the PnPn structure at the periphery of the mesa is not high enough to completely prevent leakage current, and as the forward bias voltage applied to the semiconductor laser increases, the leakage current flowing through the PnPn layer increases, resulting in high injection There was a tendency for the optical output to saturate when the current was applied or for the oscillation threshold to rapidly increase in the high temperature region.

従つて本発明の目的は、埋め込み形半導体レー
ザ、特に特願昭55−123261に記す構造の埋め込み
形半導体レーザの漏洩電流を極力防止し、高光出
力が得られ又更に高い温度での連続動作が可能な
新しい構造の埋め込み形半導体レーザを提供する
ことにある。
Therefore, an object of the present invention is to prevent the leakage current of a buried semiconductor laser, especially the buried semiconductor laser having the structure described in Japanese Patent Application No. 55-123261, to obtain a high optical output and to be able to operate continuously at a high temperature. The object of the present invention is to provide an embedded semiconductor laser with a new possible structure.

本発明によれば、n形半導体基板上に、n形第
1クラツド層(禁制帯幅Egn1)、n形第2クラツ
ド層(禁制帯幅Eg2、Egn2>Egn1)、活性層(禁
制帯幅Ega、Ega<Egn2)、およびP形クラツド層
(Egp1、Egp1>Ega)の順に積層された層構造を
少くとも含む多層膜基板を、n形第1クラツド層
に到達する深さでメサエツチングすることにより
形成された、活性層を含む帯状メサ構造が、帯状
メサ構造内部のP形クラツド層に連続するP形電
流ブロツク層(禁制帯幅EB g、EB g>En1 g)、帯状メ
サ構造のメサ上部を除いて形成されるn形電流閉
じ込め層(禁制帯幅Ec g、Ec g>En1 g)、及び全面に
亘つて連続して形成されるP形埋め込み層(禁制
帯幅EE g、EE g>En1 g)の順に連続して積層される3
層を少くとも含む多層膜により埋め込まれている
ことを特徴とする埋め込み形半導体レーザ等が得
られる。
According to the present invention, an n-type first cladding layer (gap band width Eg n1 ), an n-type second cladding layer (gap band width Eg 2 , Eg n2 >Eg n1 ), and an active layer (gap band width Eg n1 ) are formed on an n-type semiconductor substrate. A multilayer film substrate including at least a layer structure in which a forbidden band width Eg a , Eg a <Eg n2 ) and a P-type cladding layer (Eg p1 , Eg p1 > Eg a ) is laminated in this order is formed into an n-type first cladding layer. The band-like mesa structure containing the active layer is formed by mesa etching at a depth reaching . g > E n1 g ), an n-type current confinement layer (forbidden band width E c g , E c g > E n1 g ) formed except for the upper part of the mesa of the band-shaped mesa structure, and continuously formed over the entire surface. P-type buried layers (gap band width E E g , E E g >E n1 g ) are successively stacked in the order of 3.
A buried type semiconductor laser or the like is obtained, which is characterized in that it is buried in a multilayer film including at least two layers.

次に図面を用いて本発明の実施例を説明する。 Next, embodiments of the present invention will be described using the drawings.

第1図は、特願昭55−123261に記すn形InPを
基板とするInGaAsP埋め込み形半導体レーザで
ある。この半導体レーザは(001)面を有すn形
InP基板1上にn形InPバツフア層2(厚さ3μ
m)、InGaAsP活性層3(発光波長1.3μm、厚さ
0.2μm)、P形InP層4(厚さ0.5μm)を積層した
後、<110>方向に平行に、高さ2μm幅2μmのメ
サストライプ30を形成し、その後メサ側面にP
形InP電流ブロツク層5及びn形InP電流閉び込
め層6を形成し、更に全体をP形InP埋め込み層
7、n形InPキヤツプ層8で覆い、メサ上部にZn
の選択拡散領域9を形成した構造をしている。こ
の半導体レーザのP形電極20とn形電極21と
の間に、P形電極を正とするバイアス電圧を印加
すると、メサ部はPn接合の順バイアスであるた
めPn接合である活性層に電流が注入されるが、
メサ部以外はPnPn接合、もしくはnPnPn接合で
あるため、電流は殆んど流れない。従つて、活性
層のみに効果的に電流が集中し10〜20mA程度の
低い発振閾値を示す。しかしながら、20〜30mW
と高い光出力を得る場合に於ては、注入電流が大
きくなるため選択拡散領域9の下部にかかる印加
電圧も高くなり、又P形埋め込み層7からP形ク
ラツド層4、P形電流ブロツク層5を径由して流
れる電流も大きくなる。この電流は、メサ側面に
於るPnPn接合、即ちInPのサイリスタのゲート
電流として作用しこのPnPn接合のターン・オン
電圧を低下させる働きをする。従つて、印加電圧
を高くして行くと、メサ側面を通じて流れる漏洩
電流が増加し、活性層へ注入される電流の割合が
減少して行くため、光出力の飽和傾向が次第に強
くなつて行き、メサ側面のPnPn接合がターン・
オンすると急激に光出力は低下する。この様子を
第2図に示す。この漏洩電流は素子の温度特性に
も影響する。即ち、発振閾値は温度ともに増加す
るため、高温では素子にかかる印加電圧が高くな
り、結局メサ側面のPnPn接合を通して流れる漏
洩電流が増加する。従つて活性層そのものの発振
閾値の増加分に漏洩電流の増加分が加えられ、素
子の温度特性は、高温領域に於て急激に悪くな
る。従つて、第1図に示す構造のInGaAsP埋め
込み形半導体レーザの最高連続動作温度は高々80
〜100℃程度であつた。
FIG. 1 shows an InGaAsP buried semiconductor laser using n-type InP as a substrate, as described in Japanese Patent Application No. 55-123261. This semiconductor laser is an n-type with a (001) plane.
n-type InP buffer layer 2 (thickness 3μ) on InP substrate 1
m), InGaAsP active layer 3 (emission wavelength 1.3 μm, thickness
After laminating a P-type InP layer 4 (0.5 μm thick), a mesa stripe 30 with a height of 2 μm and a width of 2 μm is formed in parallel to the <110> direction, and then a P-type InP layer 4 (thickness 0.5 μm) is formed on the mesa side surface.
An InP type current blocking layer 5 and an n type InP current confinement layer 6 are formed, and the whole is further covered with a p type InP buried layer 7 and an n type InP cap layer 8, and a Zn layer is formed on the top of the mesa.
It has a structure in which a selective diffusion region 9 is formed. When a bias voltage is applied between the P-type electrode 20 and the N-type electrode 21 of this semiconductor laser, with the P-type electrode being positive, the mesa part is forward biased to the Pn junction, so current flows into the active layer, which is a Pn junction. is injected, but
Since the parts other than the mesa part are PnPn junctions or nPnPn junctions, almost no current flows. Therefore, current is effectively concentrated only in the active layer, resulting in a low oscillation threshold of about 10 to 20 mA. However, 20~30mW
In order to obtain a high optical output, the injection current becomes large and the voltage applied to the lower part of the selective diffusion region 9 also becomes high. The current flowing through 5 also increases. This current acts as a gate current of the PnPn junction on the side of the mesa, that is, an InP thyristor, and serves to lower the turn-on voltage of this PnPn junction. Therefore, as the applied voltage increases, the leakage current flowing through the mesa side increases and the proportion of current injected into the active layer decreases, so the saturation tendency of the optical output gradually becomes stronger. The PnPn junction on the side of the mesa is turned
When turned on, the light output drops rapidly. This situation is shown in FIG. This leakage current also affects the temperature characteristics of the element. That is, since the oscillation threshold increases with temperature, the voltage applied to the element increases at high temperatures, which ultimately increases the leakage current flowing through the PnPn junction on the side surface of the mesa. Therefore, the increase in leakage current is added to the increase in the oscillation threshold of the active layer itself, and the temperature characteristics of the element deteriorate rapidly in the high temperature region. Therefore, the maximum continuous operating temperature of the InGaAsP buried semiconductor laser having the structure shown in Figure 1 is at most 80°C.
The temperature was about ~100℃.

第1図に示す半導体レーザの光出力、及び連続
動作上限温度を向上させるには、メサ側面の漏洩
電流の増加を極力小さくすることが重要である。
そのためにはメサ側面のPnPn接合のターン・オ
ン電圧が高く、それがかなり大きなゲート電流が
注入されても、大きく減少しなければ良い。
In order to improve the optical output and continuous operation upper limit temperature of the semiconductor laser shown in FIG. 1, it is important to minimize the increase in leakage current on the mesa side surface.
For this purpose, the turn-on voltage of the PnPn junction on the side of the mesa is high, and even if a fairly large gate current is injected, it is sufficient that it does not decrease significantly.

第3図は本発明の実施例を示すものである。第
1図の従来例と異なる点は、n形InP基板1とn
形InPバツフア層2(第3図では、膜厚0.6μm)
との間に、n形InGaAsP第1クラツド層10
(発光波長1.3μm、厚さ1μm)を介在させおり、
メサエツチングで平坦部にn形InGaAsP第1ク
ラツド層を露出させていること及びn形InPキヤ
ツプ層8を用いていないことである。
FIG. 3 shows an embodiment of the invention. The difference from the conventional example shown in Fig. 1 is that the n-type InP substrate 1 and the
InP type buffer layer 2 (film thickness 0.6 μm in Figure 3)
between the n-type InGaAsP first cladding layer 10
(emission wavelength 1.3 μm, thickness 1 μm),
The n-type InGaAsP first cladding layer is exposed in the flat part by mesa etching, and the n-type InP cap layer 8 is not used.

第3図に示す構造の埋め込み型半導体レーザで
は、メサ部の構造は、PInP/InGaAsP(活性
層)/nInP/nInGaAsP/nInP(基板)である。
Pn接合部はInGaAsP活性層3の内部にあり、又
InGaAsP活性層3とnInGaAsP第1クラツド層3
0との間は、nInPバツフア層2が0.6μmの厚さで
介在するため、InGaAsP活性層3からnInPバツ
フア層2へ漏洩する注入キヤリアは殆んど存在し
ない。又メサ側面部はP形InP/n形InP/P形
InP/n形InGaAsP/n形InP(基板)という構造
のPnPn接合になつている。この構造のPnPn接合
は、第1図に示した構造のInPのホモ接合による
PnPn接合の場合に比べ、特にゲート電流が存在
する場合に於て、ターン・オン電圧を高く維持す
ることができる。これは次の様に考えることがで
きる。
In the buried semiconductor laser having the structure shown in FIG. 3, the structure of the mesa portion is PInP/InGaAsP (active layer)/nInP/nInGaAsP/nInP (substrate).
The Pn junction is inside the InGaAsP active layer 3, and
InGaAsP active layer 3 and nInGaAsP first cladding layer 3
0, since the nInP buffer layer 2 with a thickness of 0.6 μm is present, there is almost no injection carrier leaking from the InGaAsP active layer 3 to the nInP buffer layer 2. Also, the mesa side part is P type InP/n type InP/P type
It is a PnPn junction with a structure of InP/n-type InGaAsP/n-type InP (substrate). The PnPn junction in this structure is based on the InP homojunction in the structure shown in Figure 1.
Compared to the PnPn junction, the turn-on voltage can be maintained higher, especially in the presence of gate current. This can be thought of as follows.

第1図、第3図におけるメサ側面のPnPn構造
は、P形InP埋め込み層7側をアノード、n形
InPバツフア層2、もしくはn形InGaAsP第1ク
ラツド層10側をカソードとし、ゲート電流がP
形InP電流ブロツク層5に注入される形のサイリ
スタとして考えることができる。この時、ゲート
電流が注入されるP形電流ブロツク層5を挾む
nPn接合を考えてみると、第1図の場合ではこれ
がInPのホモ接合のトランジスタになつているの
に対し、第2図の場合ではエミツタの禁制帯幅が
最も小さいトランジスタになつているため、n形
第1クラツド層10のエミツタから、P形InP電
流ブロツク層5のベース領域へ、エレクトロンを
注入する効率が小さくなる。従つてnPn接合トラ
ンジスタの電流利得αが小さくなるため、ゲート
電流が存在してもn形InGaAsP第1クラツド層
10からn形InP電流閉じ込め層6へ輸送される
電流が小さい。従つてPnPn接合全体のターン・
オン電圧は、ゲート電流が存在しても、第1図の
場合のPnPn接合よりも高く維持することが可能
となる。
In the PnPn structure on the side of the mesa in FIGS. 1 and 3, the P-type InP buried layer 7 side is the anode, and the n-type
The InP buffer layer 2 or n-type InGaAsP first cladding layer 10 side is used as the cathode, and the gate current is P.
It can be considered as a thyristor injected into the InP current blocking layer 5. At this time, the P-type current blocking layer 5 into which the gate current is injected is sandwiched.
Considering the nPn junction, in the case of Figure 1 it is an InP homojunction transistor, whereas in the case of Figure 2 it is a transistor with the smallest emitter bandgap, so The efficiency with which electrons are injected from the emitter of the n-type first cladding layer 10 to the base region of the P-type InP current blocking layer 5 is reduced. Therefore, the current gain α of the nPn junction transistor becomes small, so even if a gate current exists, the current transported from the n-type InGaAsP first cladding layer 10 to the n-type InP current confinement layer 6 is small. Therefore, the turn of the entire PnPn junction is
The on-voltage can be maintained higher than in the PnPn junction shown in FIG. 1 even in the presence of gate current.

以上より、第3図に示す本発明の実施例の構造
の埋め込み形半導体レーザでは、印加電圧を高く
しても、メサ側面のPnPn接合はターン・オンし
にくく、この領域を通じて流れる漏洩電流は非常
に小さい。従つて、P側の電流通路を制限する必
要はなく、第2図に示すような選択拡散領域を形
成する必要がない。従つて製造工程が簡略化で
き、又オーミツク抵抗も小さくできる。この素子
の室温での発振閾値は20mAで光出力は50mW程
度まで直線的に増加し、飽和傾向は見られない。
又、高温領域に於て、発振閾値が増加しても、漏
洩電流が少いため、素子の温度特性が急激に悪く
なることはなく、Ith∝exp(T/T0)で表わされる 特性温度T0は室温から100℃程度までの間で70k
という値が得られ、100℃以上までCW動作が可
能であつた。
From the above, in the buried semiconductor laser having the structure of the embodiment of the present invention shown in FIG. 3, even if the applied voltage is high, the PnPn junction on the mesa side surface is difficult to turn on, and the leakage current flowing through this region is extremely low. small. Therefore, there is no need to restrict the current path on the P side, and there is no need to form a selective diffusion region as shown in FIG. Therefore, the manufacturing process can be simplified and the ohmic resistance can also be reduced. The oscillation threshold of this device at room temperature is 20 mA, and the optical output increases linearly to about 50 mW, with no tendency to saturation.
In addition, even if the oscillation threshold increases in the high temperature region, the leakage current is small, so the temperature characteristics of the element do not deteriorate rapidly, and the characteristic temperature T expressed by Ith∝exp(T/T 0 ) 0 is 70k from room temperature to about 100℃
This value was obtained, and CW operation was possible up to 100°C or higher.

上記の実施例では、最終層がP形InP層である
が、更にオーミツク抵抗を小さくするために、P
形InGaAsP電極形成層を付加させても良い。又、
上記実施ではn形InGaAsP第1クラツド層とし
て、発光波長が1.3μm相当の組成のInGaAsP層
を用いたが、これを1.1μm相当の組成にし、かつ
n形InPバツフア層3を適切な厚さに設定するこ
とにより、活性層で発光する光をn形InGaAsP
第1クラツド層に結合させ導波する構造にするこ
とも可能である。又本実施例ではInP基板を用い
ているが、GaAs基板を用いて、AlGaAs系の半
導体材料で作製することも可能である。
In the above embodiment, the final layer is a P-type InP layer, but in order to further reduce the ohmic resistance, a P-type InP layer is used.
An InGaAsP electrode forming layer may be added. or,
In the above implementation, an InGaAsP layer with a composition equivalent to an emission wavelength of 1.3 μm was used as the n-type InGaAsP first cladding layer, but this was changed to a composition equivalent to 1.1 μm, and the n-type InP buffer layer 3 was adjusted to an appropriate thickness. By setting the light emitted in the active layer to n-type InGaAsP
It is also possible to have a structure in which the waveguide is coupled to the first cladding layer. Further, although an InP substrate is used in this embodiment, it is also possible to use a GaAs substrate or to fabricate it from an AlGaAs-based semiconductor material.

最後に本発明の特長をまとめると、埋め込み形
半導体レーザにおいて、メサ側面のPnPn層のオ
ーン・オン電圧を高く維持できる低禁制帯幅層を
導入することにより、光出力の直線性が良くなり
高出力化できること、又素子の温度特性が改善さ
れ、100℃以上の高温まで連続動作が可能である
こと等である。
Finally, to summarize the features of the present invention, by introducing a low bandgap layer that can maintain a high on-on voltage of the PnPn layer on the side surface of the mesa in a buried semiconductor laser, the linearity of the optical output is improved and the It is possible to generate output, and the temperature characteristics of the device have been improved, allowing continuous operation up to high temperatures of 100°C or higher.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の埋め込み形半導体レーザの断
面図。第2図は従来例の埋め込み形半導体レーザ
の注入電流−光出力の特性を示すグラフ。第3図
は本発明による埋め込み形半導体レーザの実施例
を示す断面図。 図中、1……n形InP基板、2……n形InPバ
ツフア層、3……InGaAsP活性層、4……P形
InPクラツド層、5……P形InP電流ブロツク層、
6……n形InP電流閉じ込め層、7……P形InP
埋め込み層、8……n形InPキヤツプ層、9……
Znの選択拡散領域、10……n形InGaAsP第1
クラツド層、20……P側金属電極、21……n
側金属電極、30……メサストライプである。
FIG. 1 is a sectional view of a conventional buried type semiconductor laser. FIG. 2 is a graph showing the injection current vs. optical output characteristic of a conventional buried semiconductor laser. FIG. 3 is a sectional view showing an embodiment of a buried semiconductor laser according to the present invention. In the figure, 1... n-type InP substrate, 2... n-type InP buffer layer, 3... InGaAsP active layer, 4... P-type
InP cladding layer, 5... P-type InP current blocking layer,
6...N-type InP current confinement layer, 7...P-type InP
Buried layer, 8... n-type InP cap layer, 9...
Zn selective diffusion region, 10... n-type InGaAsP 1st
Cladding layer, 20...P side metal electrode, 21...n
Side metal electrode, 30...Mesa stripe.

Claims (1)

【特許請求の範囲】 1 n形半導体基板上に、n形第1クラツド層
(禁制帯幅En1 g)n形第2クラツド層(禁制帯幅
En2 g、En2 g>En1 g)、活性層(禁制帯幅Ea g、Ea g
En2 g)、およびP形クラツド層(Ep1 g、Ep1 g>Ea g)の
順に積層された層構造を少くとも含む多層膜基板
を、前記n形第1クラツド層に到達する深さでメ
サエツチングすることにより形成された、前記活
性層を含む帯状メサ構造が、前記帯状メサ構造内
部の前記P形クラツド層に連続するP形電流ブロ
ツク層(禁制帯幅EB g、EB g>En1 g)、前記帯状メサ
構造のメサ上部を除いて形成されるn形電流閉じ
込め層(禁制帯幅Ec g、Ec g>En1 g)、及び全面に亘
つて連続して形成されるP形埋め込み層(禁制帯
幅EE g、EE g>En1 g)の順に連続して積層される3層
を少くとも含む多層膜により埋め込まれているこ
とを特徴とする埋め込み形半導体レーザ。 2 特許請求の範囲第1項記載のn形半導体基板
が、(001)面を有するn形InP基板であり、n形
第1クラツド層がn形InGaAsP層であり、活性
層がInGaAsP層でありn形第2クラツド層およ
びn形電流閉じ込め層がn形Inp層であり、また
P形クラツド層、P形埋め込み層、およびP形電
流ブロツク層がP形InP層であり、かつ、帯状メ
サ構造が、<110>方位にほぼ平行に形成されてい
ることを特徴とする埋め込み半導体レーザ。
[Claims] 1. On an n-type semiconductor substrate, an n-type first cladding layer (forbidden band width E n1 g ) and an n-type second cladding layer (forbidden band width E n1 g ) are formed.
E n2 g , E n2 g > E n1 g ), active layer (gap E a g , E a g <
E n2 g ) and a P-type cladding layer (E p1 g , E p1 g >E a g ) are laminated in this order. The band-shaped mesa structure including the active layer formed by mesa etching in the band-shaped mesa structure has a P-type current blocking layer (with forbidden band widths E B g , E B g >E n1 g ), an n-type current confinement layer (forbidden band width E c g , E c g >E n1 g ) formed except for the upper part of the mesa of the band-shaped mesa structure, and continuously formed over the entire surface. Embedded type embedded with a multilayer film including at least three P-type embedded layers (gap band width E E g , E E g >E n1 g ) successively stacked in this order. semiconductor laser. 2. The n-type semiconductor substrate according to claim 1 is an n-type InP substrate having a (001) plane, the n-type first cladding layer is an n-type InGaAsP layer, and the active layer is an InGaAsP layer. The n-type second cladding layer and the n-type current confinement layer are n-type InP layers, and the P-type cladding layer, the P-type buried layer, and the P-type current blocking layer are P-type InP layers, and the band-like mesa structure is is formed substantially parallel to the <110> direction.
JP14677481A 1981-09-17 1981-09-17 Embedded type semiconductor laser Granted JPS5848491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14677481A JPS5848491A (en) 1981-09-17 1981-09-17 Embedded type semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14677481A JPS5848491A (en) 1981-09-17 1981-09-17 Embedded type semiconductor laser

Publications (2)

Publication Number Publication Date
JPS5848491A JPS5848491A (en) 1983-03-22
JPS6320393B2 true JPS6320393B2 (en) 1988-04-27

Family

ID=15415235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14677481A Granted JPS5848491A (en) 1981-09-17 1981-09-17 Embedded type semiconductor laser

Country Status (1)

Country Link
JP (1) JPS5848491A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61284987A (en) * 1985-06-10 1986-12-15 Sharp Corp Semiconductor laser element
US4839900A (en) * 1985-08-21 1989-06-13 Sharp Kabushiki Kaisha Buried type semiconductor laser device

Also Published As

Publication number Publication date
JPS5848491A (en) 1983-03-22

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