JPS63203044A - Reception circuit for phase shift modulation signal - Google Patents

Abstract

PURPOSE:To utilize a communication line effectively by providing plural conversion mode selection circuits, data comparison circuits, error counters and coincidence discrimination circuits or the like so as to apply the twice selection and comparison simultaneously by reducing the time for removing uncertain events. CONSTITUTION:One of 4 code conversion modes from a code conversion circuit 1 is selected by a conversion mode selection circuit 51, compared with a data from a pattern generating circuit 2 by a data comparison circuit 61. Moreover, the other set of conversion mode of the circuit 1 is selected by a conversion mode selection circuit 52 and compared with the data from the circuit 2 by the data comparison circuit 62. Then outputs of the circuits 61, 62, the number of dissident pulses is counted by error counters 31, 32, inputted to a conversion mode selection circuit 53 via coincidence discrimination circuits 41, 42 and the signal of the coincident data is selected. If the result of discrimination of the circuits 41, 42 represents dissidence, the correct mode is selected via an AND circuit 8 and a 1/2 frequency circuit 9 or the like to reduce the removal time of uncertain event thereby utilizing the communication line effectively.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a phase shift keying method for eliminating phase uncertainties that occur when demodulating a four-phase phase shift keying signal (hereinafter referred to as a four-phase PSK signal). This invention relates to a signal receiving circuit.

[Conventional technology]

Conventionally, there is a circuit shown in FIG. 4 as an example of a circuit for removing a phase uncertainty event that occurs when demodulating a four-phase PSK signal. This receiving circuit includes a code conversion circuit 1, a conversion mode selection circuit 5, a pattern generation circuit 2, a data comparison circuit 6, an error counter 3, a coincidence determination circuit 4, and a binary counter 7.

FIG. 3 is a comparison diagram of the state of a reproduced carrier of a four-phase PSK signal and the received code and code conversion mode corresponding to the state. In the conventional circuit, the code conversion circuit 1 prepares a code conversion mode between state A and state A, and one received data and the data of the same pattern as the known pattern inserted on the transmission side from the pattern generation circuit 2. Data comparison circuit 6
The pulses are compared and a mismatch pulse is output. The number of mismatched pulses is counted by the error counter 3, and if the number of mismatched pulses exceeds a set value, a match determination circuit 4 determines the mismatch, and the signal for switching the code conversion mode is converted to a 2-bit binary counter. 7, and the code conversion mode is switched by the conversion mode selection circuit 5.

In this way, code conversion modes are sequentially selected up to the mode in which the data match. For example, when the conversion mode selection circuit 5 sequentially selects from state A to state A, if the transmitting side carrier state is the state shown in FIG. 3 and the reproduced carrier state is state A, data comparison is performed four times. The phase uncertainty event will be removed after the

[Problem that the invention seeks to solve]

However, since the conventional circuit is a circuit that selects and compares four code conversion modes in order, in the worst case, four selection comparisons are required to remove the phase uncertainty event, and therefore, the phase uncertainty This method has the disadvantage that it takes a long time to remove an event, and communication lines cannot be used effectively.

An object of the present invention is to provide a four-phase PSK signal receiving circuit that eliminates such drawbacks, performs two selection comparisons simultaneously, shortens the time required to remove uncertain events, and makes effective use of communication lines. There is a particular thing.

[Means for solving problems]

The configuration of the four-phase PSK signal receiving circuit of the present invention includes a code conversion circuit that converts a received code of a signal subjected to four-phase phase shift keying in accordance with the state of a reproduced carrier, and four signals from this code conversion circuit. a first selection circuit that selects a set of modes from the code conversion modes according to a first control signal;
a second selection circuit that selects one mode from among the outputs of the selection circuit according to a second control signal; a pattern generation circuit that generates a known pattern to be inserted on the transmission side; and an output of the pattern generation circuit. Compare each mode output from the first selection circuit, identify whether a desired signal is selected, and send first and second selection control signals to the first and second selection circuits. The invention is characterized by comprising a control means for giving.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention.

This embodiment includes a code conversion circuit 1, a pattern generation circuit 2 that generates a known pattern inserted on the transmission side, error counters 31 and 32, and match determination circuits 41 and 42.
, a first conversion mode selection circuit 51, 52, a second conversion mode selection circuit 53, data comparison circuits 61 and 62, an AND circuit 8, and a 1/2 frequency divider circuit 9. .

Code conversion modes of states A to D shown in FIG. The mode output is input to the conversion mode selection circuit 52.

On the other hand, suppose that the pattern generated by the pattern generation circuit 2 is set to the pattern inserted into the I channel. The data comparison circuit 61 is inserted into one channel on the conversion mode selection circuit 51 side, and the data comparison circuit 62 is inserted into the conversion mode selection circuit 51 side.
Inserted into the ■channel on the 2nd side. Although any two sets of input signals may be input to the conversion mode selection circuits 51 and 52, the insertion channel of the data comparison circuits 61 and 62 is set to the same channel as the generation pattern setting channel of the pattern generation circuit 2.

Modes of state A and state B of the received data code-converted by the code conversion circuit 1 are selected by the conversion mode selection circuit 51.
One of them is selected in , and compared with the data generated from pattern generation circuit 2 in data comparison circuit 61 . Furthermore, one of the modes C and C is selected in the conversion mode selection circuit 52, and the pattern generation circuit 2
The data generated from the data comparison circuit 62 is compared with the data generated from the data comparison circuit 62. The outputs of these data comparison circuits 61 and 62 are respectively counted by error counters 31 and 32 to count the number of mismatched pulses, and when the number of these mismatched pulses is greater than a set value, a match judgment circuit 41 and 42 determines that there is a mismatch. It will be judged. Based on the determination results of these coincidence determination circuits 41 and 42, the conversion mode selection circuit 53 selects the matched data side signal.

Further, if both of the judgment results of the match judgment circuits 41 and 42 are judged as mismatch, the output signal of the AND circuit 8 changes, and the 1/2 frequency divider circuit 9 is operated, and the conversion mode selection circuits 51 and 52 inverts the polarity of the selection signal. As a result, the remaining state modes are selected, data comparison is performed again in the same process, and the correct mode is selected.

In this way, no matter which of the four states the reproduced carrier is in, correct received data can be obtained by comparing the data twice at worst, and the phase uncertainty event can be removed.

In this embodiment, the pattern generated by the pattern generation circuit 2 is the pattern inserted into the I channel, but it may also be set to the pattern inserted into the Q channel. In this case, the insertion channel of the data comparison circuits 61 and 62 is This can be done by setting it to the Q channel.

Further, in this embodiment, two data comparisons are performed for one type of generation pattern, but two data comparisons may be performed for two types of generation patterns. Further, in this embodiment, data is compared using a known pattern inserted on the transmitting side, but data may be compared with data after error correction.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention. In this embodiment, two pattern generation circuits 21 and 22 each generate a known pattern inserted on the transmitting side.
The second embodiment differs from the first embodiment in that the second embodiment is provided, but the other configurations are the same as the first embodiment.

Code conversion modes of states A to D shown in FIG. are respectively input to the conversion mode selection circuit 52. Pattern generation circuit.

Set the generation pattern of 21 to the pattern inserted in channel ■, and set the generation pattern of pattern generation circuit 22 to Q.
Set to a pattern inserted into a channel.

The data comparison circuit 61 is inserted into one channel on the conversion mode selection circuit 51 side, and the data comparison circuit 62 is inserted into the Q channel on the conversion mode selection circuit 52 side. The combination of input signals to these conversion mode selection circuits 51 and 52 is as follows:
Any two sets may be used, but the insertion channels of the data comparison circuits 61 and 62 are set to the same channels as the generation pattern setting channels of the pattern generation circuits 21 and 22, respectively. In the circuit of this embodiment, data comparison is performed in the same process as in the first embodiment, and phase uncertainty events are removed.

[Effects of the Invention] As explained above, the present invention detects the regenerated carrier state on the receiving side by comparing data twice in the worst case, and removes phase uncertainty events, so that the present invention has the effect of making effective use of communication lines. .

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a block diagram of a second embodiment of the invention, and Fig. 3 shows the state of the reproduced carrier of the four-phase PSK signal and its state. FIG. 4 is a block diagram showing the circuit configuration of a conventional example, which is a comparison diagram with corresponding reception codes and code conversion modes. 1... Code conversion circuit, 2, 21.22... Pattern generation circuit, 3.31.32... Error counter, 4.
41.42... Match determination circuit, 5, 51, 52.53
...Conversion mode selection circuit, 6.61.62...Data comparison circuit, 7...Binary counter, 8...AN
D circuit, 9...1/2 frequency divider circuit. Agent: Patent Attorney Shinmi Uchihara

Claims (1)

[Claims] A code conversion circuit converts the received code of the four-phase phase shift keyed signal in accordance with the state of the reproduced carrier, and a control signal from the code conversion circuit selects the first of the four code conversion modes. a first selection circuit for selecting a mode of the set;
a second selection circuit that selects one mode from among the outputs of the first selection circuits based on a second control signal; a pattern generation circuit that generates a known pattern to be inserted on the transmission side; and this pattern generation circuit. and each mode output from the first selection circuit, identify whether or not a desired signal is selected, and send the first and second selection circuits to the first and second selection circuits. A phase shift keying signal receiving circuit comprising: control means for providing a control signal.