JPS63164556A - Circuit for receiving phase deviation modulating signal - Google Patents

Abstract

PURPOSE:To effectively utilize a communication line by simultaneously discriminating two kinds of patterns in each mode by means of a control means. CONSTITUTION:A code conversion circuit 1 is set up to a prescribed code conversion mode and the generation pattern of a pattern generating circuit 2 is set up to a pattern inserted into an I channel. Data on the I channel side are compared with data generated from the circuit 2 and data to which polarity is inverted by an inversional circuit 9 by data comparators 61, 62. Error counters 31, 32 count up the number of noncoincident pulses, and when the counted value exceeds a set value, noncoincidence is decided by coincidence circuits 41, 42. When the circuits 41, 42 decide the noncoincidence, a pulse is generated from an AND circuit 11, a 1/2 frequency dividing circuit 10 is driven, an output from the circuit 10 is inputted to a selection signal switching circuit 8 and the mode of a conversion mode selecting circuit 5 is switched. When either one of the circuits 41, 42 decides coincidence and the other decides noncoincidence and when both the circuits 41, 42 decide coincidence, the mode of the circuit 5 is switched to discriminate a pattern.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a receiving circuit for a phase shift keying signal, and in particular, the present invention relates to a receiving circuit for a phase shift keying signal. The present invention relates to a receiving circuit for a phase shift keying signal that removes a phase uncertainty event using a known code inserted on the transmitting side or a citrome during error correction.

[Conventional technology]

First, conventional technology will be described. FIG. 4 shows a conventional circuit for removing phase uncertainty events that occur when demodulating a four-phase PSK signal. Figure 2 shows the state of the reproduced carrier of the four-phase PSK signal and the received code (i, q) corresponding to that state.
2 is a chart showing a contrast between the code conversion mode and the mode selection signal (■ and Q indicate data channels).

In the conventional example circuit, a code conversion mode between state A and state A is prepared in the code conversion circuit 1, and data with the same pattern as the known pattern inserted on the transmitting side from the pattern generation circuit 2 and received data on one side are prepared. are compared in the data comparison circuit 6, the number of mismatched pulses is counted by the error counter 3, and if the number of mismatched pulses exceeds a set value, a match determination circuit 4 determines the mismatch, and code conversion is performed. A signal for switching the mode is output from the 2-bit binary counter 7, and the conversion mode selection circuit 5 switches the code conversion mode. In this way, code conversion modes are sequentially selected until the mode in which the pattern data matches. For example, when the conversion mode selection circuit 5 sequentially selects from state A to state A, if the transmitting side carrier state is the state shown in FIG. 2 and the reproduced carrier state is state A, the data will be compared four times. After the phase uncertainty event is removed.

[Problem that the invention seeks to solve]

The conventional phase shift keying signal receiving circuit described above is a circuit that sequentially selects and compares four code conversion modes, so in the worst case, four selection comparisons are required to remove phase uncertainty events. Therefore, there is a drawback that it takes a long time until the phase uncertainty event is removed, and the communication line cannot be used effectively.

As mentioned above, conventionally, when removing the phase uncertainty event that occurs when demodulating a four-phase PSK signal, a circuit that sequentially compares and selects four code conversion modes using one data comparison circuit has the worst four-phase PSK signal. In contrast, the present invention simultaneously compares two types of data for one of the four code conversion modes, and in the worst case, two identical selected comparisons remove the phase uncertainty. It removes the event.

[Means for solving problems]

The phase shift keying signal receiving circuit of the present invention inputs a signal that has been subjected to four-phase phase shift keying into which a predetermined known pattern has been inserted, and converts the received code in accordance with the four states of the reproduced carrier. a code conversion circuit that selects the state of one of the predetermined signals; a selection circuit that selects the state of one of the predetermined signals; and a code conversion circuit that selects the state of one of the predetermined signals; A phase shift keying signal receiving circuit comprising: control means for identifying whether a signal is selected and providing a selection mode switching signal to the selection circuit; It is constructed by identifying the

〔Example〕

Next, the present invention will be explained based on the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, and FIG. 2 shows the state of the reproduced carrier of the four-phase PSK signal, the received code corresponding to the state, the code conversion mode, and the mode selection signal. Figure 2 is a chart showing a comparison.

The first embodiment of the present invention includes a code conversion circuit 1, a pattern generation circuit 2 that generates the same pattern as a known pattern inserted on the transmitting side, error counters 31 and 32, and match determination circuits 41 and 42. , conversion mode selection circuit 5, data comparison circuits 61 and 62, 1/2 frequency division circuit 10, selection signal switching circuit 8, inversion circuit 9, AND circuit 11,
EXCLUSIVE-NOR circuit 12 and holding circuit 13
It is equipped with

First, code conversion modes of states A to D shown in FIG. 2 are prepared in the code conversion circuit 1. The pattern generated by the pattern generation circuit 2 is set to the pattern inserted into the channel (2). Of the received data whose code has been converted by the code conversion circuit 1, data on the channel side is compared with the data generated from the pattern generation circuit 2 in the data comparison circuit 61, and with the data whose polarity has been inverted in the inversion circuit 9 by the data comparison circuit. 62, respectively. Error counters 3 and 32 count the number of mismatched pulses, and if the number of mismatched pulses is equal to or greater than a set value, match determination circuits 41 and 42 determine that there is no mismatch. When the determination circuits 41 and 42 determine that both of them do not match, a pulse is generated in the AND circuit 11, and the 1/2 frequency divider circuit 10 operates to invert the polarity of the output. The output signal of the 1/2 frequency divider circuit 10 is input to the selection signal switching circuit 8,
The mode of the conversion mode selection circuit 5 is switched.

When the initial value of the output signal of the selection signal switching circuit 8 is (0°6-0), that is, the mode selection signal for selecting state A shown in FIG. The state of the reproduced carrier is state A at the input of the data comparison circuit 61 and state C at the input of the data comparison circuit 62. When the match determination circuit 41 determines a match and the match determination circuit 42 determines a mismatch, the output signal of the holding circuit 13 is left as is, and the output signal of the selection signal switching circuit 8 is changed to (0, O). In other words, the mode of the conversion mode selection circuit 5 remains in state A. Here, the first
2 input from the right side of the selection signal switching circuit 8 in the figure.
This signal is selected as the output, and will be abbreviated as the right-hand signal (in the opposite case, the left-hand signal). Conversely, when the match determination circuit 41 determines that there is no mismatch and the match determination circuit 42 determines that there is a match, the polarity of the output signal of the holding circuit 13 is inverted, and the output signal of the selection circuit switching circuit 8 is changed to the left side signal (1, O)
, the mode of the conversion mode selection circuit 5 is switched to state C, and the correct mode is output.

If it is determined that the two do not match, the 1/2 frequency divider circuit 10 operates, and the mode selection signal of the selection signal switching circuit 8 becomes the right signal (0, 1) and switches to select state B. In this case, when the state of the reproduced carrier is in state B at the input of the data comparison circuit 61 and state B at the input of the data comparison circuit 62, it is determined that they match. When the match determination circuit 41 determines a match and the match determination circuit 42 determines a mismatch, the output signal of the holding circuit 13 is left as is, and the output signal of the switching circuit 8 is left as the right side signal (0, 1), that is. The mode of the conversion mode selection circuit 5 remains in state B.

Conversely, if the match determination circuit 41 determines that there is no match, and the match determination circuit 42 determines that there is a match, the polarity of the output signal of the holding circuit 13 is inverted, and the output signal of the selection signal switching circuit 8 is changed to the left signal (1, 1). , the mode of the conversion mode selection circuit 5 is switched to state 1, and the correct mode is output. Here, even if both the match determination circuits 41 and 42 determine that they do not match,
If the output of the 1/2 frequency divider circuit 10 is inverted once, one of the match determination circuits 4 and 42 will determine a match.

In this way, the selection signal switching circuit 8 outputs a mode selection signal corresponding to the state of the reproduced carrier determined to be a match, and the conversion mode selection circuit selects the correct mode. Further, when the match determination circuit 42 determines that there is a match, the data input to the data comparison circuit 62 after the correct mode is selected is the same as the pattern generated by the pattern generation circuit 2. The input data is inverted only when it is determined that they match, so that no mismatch occurs after the mode is switched. Further, the holding circuit 13 holds the selection signal of the mode that is first determined to be a match so that it does not change after the mode is switched.

In this way, no matter which of the four reproduced carrier states there are, correct received data can be obtained and the phase uncertainty event can be removed by performing two data comparisons at worst.

In this embodiment, the pattern generated by the pattern generation circuit 2 is the pattern inserted into the I channel, but it may also be set to the pattern inserted into the Q channel. In this case, the inserted channels of the data comparison circuits 61 and 62 are The present invention can be implemented by setting the Q channel. Further, in this embodiment, data was compared using a known pattern inserted on the transmitting side, but the present invention can also be implemented by comparing data after error correction.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention.

The second embodiment includes a code conversion circuit 1, a conversion mode selection circuit 5, a pattern generation circuit 2 that generates a known pattern inserted on the transmission side, error counters 31 and 32, and match determination circuits 41 and 42. , data comparison circuits 61 and 62, a selection signal switching circuit 8, an AND circuit 11, a holding circuit 13, an up counter 14, a down counter 15, and a selection circuit 16.

The pattern generated by the pattern generation circuit 2 is set to the known pattern inserted into the channel side, and the input of the data comparison circuit 61 is set to the channel side.
The inputs of are respectively connected to the Q channel side through the selection circuit 16 L2. The initial values of the UP counter 14 and the DOWN counter 15 are set so as to become mode selection signals for selecting state A and state 2 shown in FIG. 2, respectively. ■The mode selection signal is generated sequentially from state A to state on the channel side, and the mode selection signal is generated from state on to state A on the Q channel side.
A mode selection signal is generated sequentially.

In the second embodiment, match determination circuits 41 and 42 determine whether or not they match in the same process as in the first embodiment.

If it is determined that the two do not match, a signal is sent out by the AND circuit 11, and the UP counter 14 and the DOWN counter 15 operate respectively. As a result, state B and state C
The correct mode is selected in the same manner as the circuit of the first embodiment. After the correct mode is selected, the data input to the data comparison circuit 62 changes to the pattern inserted into the Q channel, so the selection circuit 16 selects the data from the Q channel side so that it is compared with the data on the Q channel side. Switching is performed to the data on the channel side to prevent discrepancies and coincidences after mode switching. In the second embodiment, as in the first embodiment, the phase uncertainty event is removed by comparing data twice at worst.

〔Effect of the invention〕

As explained above, the present invention detects the state of the reproduced carrier on the receiving side by comparing data of a predetermined known pattern twice at worst, and removes phase uncertain events, making effective use of communication lines. It has the effect of being able to.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing the configuration of the first embodiment of the present invention, and Fig. 2 shows the state of the reproduced carrier of the four-phase PSK signal and the reception code and code conversion corresponding to the state. FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention, and FIG. 4 is a block diagram showing the configuration of a conventional circuit. 1... Code conversion circuit, 2... Pattern generation circuit, 3
・31・32...Error counter, 4・4], ・42
... Match determination circuit, 5... Conversion mode selection circuit, 6
・61, 62... Data comparison circuit, 7... Binary counter, 8... Selection signal switching circuit, 9... Inverting circuit, 10... 1/2 frequency dividing circuit, 11... AND Circuit, 12... EXCLUSIVE-NOR circuit, 13
...Holding circuit, 14 ・tJP counter, 15...
DOWN counter, 16... selection circuit.

Claims (1)

[Claims] a code conversion circuit that inputs a signal into which a predetermined known pattern has been inserted and has been subjected to four-phase phase shift keying, and converts the received code in accordance with the four states of the reproduced carrier, and a predetermined signal. a selection circuit for selecting one of the states; and a selection circuit for identifying whether or not the predetermined signal is selected for the output of the selection circuit by detecting the known pattern inserted on the transmission side; A phase shift keying signal receiving circuit comprising a control means for supplying a selection mode switching signal to a selection circuit, wherein the control means simultaneously identifies two types of patterns for one mode. Receiving circuit for modulated signals.