JPS63203017A - Multiplier and divider circuit in 2m galois field - Google Patents

Abstract

PURPOSE:To simplify the operation where multiplication/division of the 2<m> Galois field is processed by addition/subtraction of a logarithmic conversion value by applying the processing that a multiplier/divisor or a number inverting each bit and a multiplicand/dividend and '1' is added to the result of addition if carry takes place. CONSTITUTION:A multiplier/divisor bit inverting circuit 100 receives m-bit multiplier/divisor b1-bm subject to logarithmic conversion, outputs the inputted multiplier/divisor, outputs the inputted multiplier/divisor as it is in the case of the multiplication and gives an output in the case of the division while each bit of the multiplier/divisor is inverted. An adder circuit 200 receives outputs e1-em of the circuit 100 and m-bit multiplicand/dividend a1-am subject to logarithmic conversion and applies the addition to both the inputs. When a carry is caused in the result of addition from the circuit 200 and '1' is set in a carry output Cm+1, '1' is added to the result of said addition by inputting the said signal to a carry input C0 to output solutions d1-dm of the multiplication/ division.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a circuit that performs multiplication and division in a two-Galois field, and in particular, the present invention relates to a circuit that performs multiplication and division in a two-Galois field, and in particular, multiplication and division by addition and subtraction of logarithmically transformed values whose bases are primitive elements of multipliers and non-multipliers. It relates to circuits that perform calculations.

[Conventional technology]

Conventionally, this type of multiplication/division circuit in two Galois fields has a length of 9 m.
+1-bit adder circuit adds and subtracts m-bit multiplier and m-bit non-multiplier/divider, and from m+1-bit solution including 9 carry pits, read-only memory etc.
It was converted into a corresponding solution in a 2-Galois body of bits.

[Problem that the invention seeks to solve]

As mentioned above. Conventional multiplication/division circuits in 2-Galois fields require two operations: addition and subtraction of 9 multipliers and non-multipliers, and then code conversion from 9m+1 bits to m bits, and the hardware is complicated. There is.

[Failure to solve the problem]

The present invention aims to eliminate these drawbacks.

A multiplier that inputs a logarithmically converted m-bit multiplier and then outputs the input multiplier as it is by controlling the multiplication and division switching signal, and outputs the input multiplier as it is during multiplication, and inverts each bit of the multiplier during division. a pit inversion circuit; and an addition circuit which performs addition by inputting the multiplier/divisor bit inversion circuit output and a logarithmically converted m-bit non-multiplier/divisor and has a carry input and a carry output, the addition circuit The carry output of the adding circuit is connected to the carry input, and when a carry occurs in the addition result of the multiplication/division number and the non-multiplication/division number input to the adder circuit, 1 is added to the addition result.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. 100
is a multiplier/divisor bit inversion circuit which inputs logarithmically converted m-bit multipliers b1 to bm and outputs the input multiplier/divider as is when performing multiplication by controlling the multiplication/division switching signal C; Inverts each bit of a number and outputs it. 200 is an adder circuit, which is the output e of the 1-power divisor pit inversion circuit 100, and the m-bit non-multiplier divisor a1 which has been logarithmically converted from the ˜radius.
~alTl are input and both inputs are added.

If a carry occurs in the addition result from the adder circuit 200 and 1 is set at the carry output Cm+1, the same signal is input to the carry input C8, and 1 is added to the addition result to obtain the multiplication/division solutions d1 to dm. is output.

FIG. 2 shows an embodiment of the multiplier/divisor bit inversion circuit ioo. For each bit of the logarithmically converted m-bit multiplier/divisor S, ~bm, the exclusive OR with the multiplication/division switching signal C is taken, and outputs 01-em of the 9m-pit multiplier/divisor bit inversion circuit are output.

2 near, zero, <2.ka. When performing total multiplication and division in the A field using logarithmically transformed values whose bases are the primitive elements of the multiplier and the non-multiplier and divisor, the basis that it can be performed with the above circuit configuration is shown below.

Now, if the primitive element of the 2-Galois field is α, the elements of the 2-Galois field other than zero are shown below.

GF(2”)-(α0+ ”+ α2+ α5+ ””
"+ α2-2+m-1 α) Furthermore, the following formula is defined.

α2m+i = αi+1 α2m1-1 = α0
, , , , , , (1゜However, i is O<i<2
An integer that satisfies -2.

Furthermore, the number () obtained by inverting each bit of the logarithmically transformed value whose base is the primitive element α of the element is given by the following formula.

(α,,)−1−α′”−2−1,＜α0)−′=(α
°)・・・・・・(2) Next, the multiplication of elements is α3・α1
=αj+.

When j+k<2'', the following formula is obtained and it is included in GF (2m).

j k j4-k ・・・・・・・・・
・・・・・・・・・ (3) When α ・ α = α j+k〉20, use formula (1) as shown below.

j+k 2m+ (12m to j+) -12m to j+
+1 , , , , (4゜α = α
= α again. Division of elements can be done using equation (2) as shown below.

αj−α to αj−=αJ+(2−1−k)+1−α
When 2+j-, j〉kO, 0'! #)
When 2"+j-k>2".

αj, α = (: 12m + (2rr + -j- -2m)
+1 2m+j-1 (+1 ,,, (5゜=α j<k (at D, tsu'!,!l) 2m+j-k<
2m (D time td.

αj÷α to −α2+kok
(6) From the above equations (3) to (6), it can be seen that multiplication and division in a two-Galois field can be performed with the circuit configuration described above.

〔Effect of the invention〕

As explained above, the present invention adds a 9-power divisor or a number obtained by inverting each bit of the multiplier/divisor and a non-multiplier divisor, and when a carry occurs in the addition result, 1 is added to the addition result. By configuring the circuit to connect the carry output of the adder circuit to the carry input, it is possible to perform addition and subtraction when multiplication and division in a two-Galois field is performed by adding and subtracting logarithmically transformed values whose bases are the primitive elements of the multiplier and the non-multiplier and divisor. There are effects that can be achieved with a single operation and a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an embodiment of a multiplier/divisor bit inversion circuit. 100... Multiplier/divisor bit inversion circuit, 200... Addition circuit. Figure 2

Claims (1)

[Claims] 1. Multiplication and division in the 2^m Galois field excluding zero, which is done in the process of calculating the error location polynomial from the syndrome during decoding of the BCH error correction code, is converted into a logarithm whose base is the primitive element of the multiplier and non-multiplier. In a circuit that performs addition and subtraction of converted values, a logarithmically converted m-bit multiplier is input, and by controlling the multiplication/division switching signal, the input multiplier is output as is during multiplication, and each of the multipliers is output during division. A multiplier/divisor bit inversion circuit that inverts and outputs bits, and a logarithmically converted m of the multiplier/divisor bit inversion circuit output.
It has an m-bit adder circuit having a carry input and a carry output for performing addition by inputting a non-multiplying divisor of bits,
The carry output of the adder circuit is connected to the carry input, and when a carry occurs in the addition result of the multiplier/divider and the non-multiplier/divider input to the adder circuit, 1 is added to the addition result.
^m Multiplication/division circuit in Galois field.