JPS63202970A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63202970A JPS63202970A JP62034439A JP3443987A JPS63202970A JP S63202970 A JPS63202970 A JP S63202970A JP 62034439 A JP62034439 A JP 62034439A JP 3443987 A JP3443987 A JP 3443987A JP S63202970 A JPS63202970 A JP S63202970A
- Authority
- JP
- Japan
- Prior art keywords
- source
- conductor layer
- low concentration
- gate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000004020 conductor Substances 0.000 claims abstract description 29
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims description 24
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は半導体装置、特にＬ Ｄ Ｄ （Ｌｉｇｈｔｌ
ｙ Ｄ。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to semiconductor devices, particularly LDD (Light
yD.
ｐｅｄ Ｄｒａｉｎ ）構造をもったＭ ＯＳ Ｆ Ｅ
Ｔ （ＭｅｔａｌＯｘｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃ
ｔｏｒ Ｆｉｅｌｄ ＥｆｆｅｅｔｉｖｅＴｒａｎｓｉ
ｓｔｏｒ）に関する。MOSFE with ped drain) structure
T (MetalOxide Sem1conduc
torFieldEffectiveTransi
stor).
（従来の技術）
近年、ＭＯＳＦＥＴの需要が非常に高まっておリ、また
、益々高集積化が要求されている。ＭＯＳＦＥＴは一般
に、半導体基板上に形成されたソースと、ドレインと、
そしてこれらの間に形成されるチャネルを制御するため
に絶縁膜を介して設けられたゲートとから構成される。(Prior Art) In recent years, the demand for MOSFETs has increased significantly, and higher integration is also required. MOSFET generally has a source and a drain formed on a semiconductor substrate,
and a gate provided through an insulating film to control a channel formed between these.
このようなＭＯＳＦＥＴの中で、特にソース・ドレイン
間の耐圧（以下、出力耐圧という）を高くするために、
ドレインに隣接した部分にドレインより低濃度の不純物
を拡散した低濃度領域を設けるＬＤＤ構造をもったもの
が開発されてきている。Among these MOSFETs, in order to particularly increase the breakdown voltage between the source and drain (hereinafter referred to as output breakdown voltage),
A device having an LDD structure has been developed in which a low concentration region is provided adjacent to the drain in which impurities are diffused at a concentration lower than that of the drain.
第３図は、このようなＬＤＤ構造をもった従来の一般的
なＭＯＳＦＥＴの構造断面図である。Ｎ型のシリコンか
らなる半導体基板１の上に、Ｐ型の不純物を拡散したソ
ース２およびドレイン３が設けられ、更に、このトレイ
ン３に隣接して低濃度領域４が設けられている。このソ
ース２とドレイン３との間に形成されるチャネルを制御
するために、絶縁層５を介してアルミニウムからなるゲ
ート６が設けられている。また、同じアルミニウムによ
って、ソース配線層７およびドレイン配線層８か形成さ
れている。FIG. 3 is a structural sectional view of a conventional general MOSFET having such an LDD structure. A source 2 and a drain 3 in which P-type impurities are diffused are provided on a semiconductor substrate 1 made of N-type silicon, and furthermore, a low concentration region 4 is provided adjacent to the train 3 . In order to control the channel formed between the source 2 and drain 3, a gate 6 made of aluminum is provided with an insulating layer 5 interposed therebetween. Also, the source wiring layer 7 and the drain wiring layer 8 are formed of the same aluminum.
第４図は、アルミニウムのかわりにポリシリコンからな
るゲート９を用いた例である。最近、ゲート電極には第
３図に示すようなアルミニウムより第４図に示すポリシ
リコンの方が、よく用いられるようになってきている。FIG. 4 shows an example in which a gate 9 made of polysilicon is used instead of aluminum. Recently, polysilicon as shown in FIG. 4 has been more commonly used for gate electrodes than aluminum as shown in FIG.
これは、ポリシリコンのゲートがアルミニウムのゲート
に比べて、集積化に優れ、応答性も良く、しかも低消費
電流で動作しつるというメリットがあるためである。This is because polysilicon gates have advantages over aluminum gates in that they have better integration, better response, and operate with lower current consumption.
（発明か解決しようとする問題点）
プラスチックモールドタイプの半導体装置においては、
水分が半導体チップ内に侵入し、低濃度の不純物拡散層
の濃度を変化させてしまうことがしばしばある。これは
水分の侵入により発生した可動イオンが周囲の電界によ
って移動して一部に集中し、この集中したイオンによる
電界によって濃度変化が生じるためである。このような
現象はＬＤＤ構造のＭＯＳＦＥＴにおいては、ＯＮ抵抗
の増加、出力電流の減少という形であられれる。(Problem to be solved by invention) In plastic mold type semiconductor devices,
Moisture often enters the semiconductor chip and changes the concentration of the low concentration impurity diffusion layer. This is because mobile ions generated by the intrusion of water move and concentrate in one area due to the surrounding electric field, and the electric field caused by the concentrated ions causes a concentration change. In a MOSFET having an LDD structure, this phenomenon occurs in the form of an increase in ON resistance and a decrease in output current.
第３図に示すようなアルミニウムをゲートに用いた装置
では、アルミニウムによるゲート６によって、外部から
の不純物の侵入を防ぐことができるが、第４図に示すよ
うなポリシリコンをゲートに用いた装置では、低濃度領
域４を十分に保護できず、外部からの不純物の侵入によ
って」−述のような問題を生じてしまうことになる。前
述のように、最近ではポリシリコンをゲートとして用い
る装置が多く、このような素子特性の不安定性は大きな
問題となってきている。In a device using aluminum for the gate as shown in FIG. 3, the gate 6 made of aluminum can prevent impurities from entering from the outside, but in a device using polysilicon for the gate as shown in FIG. In this case, the low-concentration region 4 cannot be sufficiently protected, and impurities may enter from the outside, causing the problems described above. As mentioned above, recently many devices use polysilicon as a gate, and instability of such device characteristics has become a major problem.
ポリシリコンをゲートとして用いる装置にお・けるこの
ような問題を解決するための手段として、第５図に示す
ような構造が提案されている。これは、アルミニウムか
らなるドレイン配線層８を少し延ばし、この延展部８′
によって低濃度領域４の上方を覆い、延展部８゛を保護
導体層として用い、外部からの不純物の侵入を防止しよ
うとするものである。しかしながら、このような構造を
採ると、素子の出力耐圧値が低下する事実が実験的に確
認されており、新たな問題となる。近年では、バイポー
ラＣＭＯ８化によってこのような問題を解決する試みも
みられるが、コストが高くなるため実用的な問題が生じ
る。As a means to solve these problems in devices using polysilicon as gates, a structure as shown in FIG. 5 has been proposed. This extends the drain wiring layer 8 made of aluminum a little, and this extended portion 8'
This is intended to cover the upper part of the low concentration region 4 and use the extended portion 8' as a protective conductor layer to prevent impurities from entering from the outside. However, it has been experimentally confirmed that when such a structure is adopted, the output breakdown voltage value of the element decreases, which poses a new problem. In recent years, attempts have been made to solve this problem by using bipolar CMO8, but this increases the cost and causes practical problems.
そこで本発明は、出力耐圧値を低下させることなく、安
定した素子特性を維持できる半導体装置を提供すること
を目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that can maintain stable element characteristics without reducing the output breakdown voltage value.
（問題点を解決するための手段）
本発明は、半導体基板上に、ソースと、ドレインと、こ
のドレインに隣接して設けられ低濃度の不純物を含む低
濃度領域と、ソース・ドレイン間に形成されるチャネル
を制御するためのゲートと、を備える半導体装置におい
て、
低濃度領域を覆うようにその上方に保護導体層を形成し
、少なくともチャネルがＯＦＦとなった □とき
に、この保護導体層がソースとほぼ同電位となるように
電気的に接続したものである。(Means for Solving the Problems) The present invention provides a source, a drain, a low concentration region provided adjacent to the drain and containing a low concentration impurity, and a region formed between the source and the drain on a semiconductor substrate. In a semiconductor device, a protective conductor layer is formed above the low concentration region so as to cover the low concentration region, and when at least the channel is turned off, the protective conductor layer It is electrically connected to have almost the same potential as the source.
（作 用）
上述の構造によれば、外部からの不純物の侵入は、保護
導体層によって防止することができる。(Function) According to the above-described structure, the intrusion of impurities from the outside can be prevented by the protective conductor layer.
したがって、低濃度領域の不純物濃度の不安定化を抑止
することができ、素子特性の安定化を図ることかできる
。また、本願発明者は、この保護導体層を、ソースとほ
ぼ同電位に保つことにより出力耐圧の低下を抑制しうる
ことを発見し、実験的に確認した。したがって、少なく
とも高出力耐圧が要求されるチャネルのＯＦＦ時に、保
護導体層をソースとほぼ同電位に保つようにしたもので
ある。Therefore, it is possible to prevent the impurity concentration in the low concentration region from becoming unstable, and it is possible to stabilize the device characteristics. In addition, the inventor of the present invention discovered and experimentally confirmed that by keeping this protective conductor layer at substantially the same potential as the source, a decrease in output breakdown voltage can be suppressed. Therefore, the protective conductor layer is kept at approximately the same potential as the source at least when the channel is turned off, which requires a high output breakdown voltage.
（実施例）
以下、本発明を図示する実施例に基づいて説明する。第
１図は、本発明の第１の実施例に係るＭＯＳＦＥＴの構
造断面図である。従来装置と同様に、Ｎ型のシリコンか
らなる半導体基板１の上に、Ｐ型の不純物を拡散したソ
ース２およびドレイン３が設けられ、更に、このドレイ
ン３に隣接して低濃度領域４が設けられている。このソ
ース２とドレイン３との間に形成されるチャネルを制御
するために、絶縁層５の中にポリシリコンからなるゲー
ト９が設けられている。また、ソース２およびドレイン
３の」二には、アルミニウムからなるソース配線層７お
よびドレイン配線層８が電気的に接続されている。この
装置の特徴は、ソース配線層７の一部が図の右方へと延
び、延展部７′を形成している点である。この延展部７
′は、ゲート９の上方を横切り低濃度領域４の上方を覆
うように形成されている。この延展部７−は保護導体層
として、外部から低濃度領域４に不純物が侵入するのを
妨げる。したがって、素子特性の安定性が確保される。(Example) The present invention will be described below based on an illustrative example. FIG. 1 is a structural sectional view of a MOSFET according to a first embodiment of the present invention. Similar to the conventional device, a source 2 and a drain 3 in which P-type impurities are diffused are provided on a semiconductor substrate 1 made of N-type silicon, and a low concentration region 4 is further provided adjacent to the drain 3. It is being In order to control the channel formed between the source 2 and drain 3, a gate 9 made of polysilicon is provided in the insulating layer 5. Further, a source wiring layer 7 and a drain wiring layer 8 made of aluminum are electrically connected to the two ends of the source 2 and drain 3. A feature of this device is that a part of the source wiring layer 7 extends to the right in the figure to form an extended portion 7'. This extension part 7
' is formed to cross over the gate 9 and cover the low concentration region 4 . The extended portion 7- serves as a protective conductor layer and prevents impurities from entering the low concentration region 4 from the outside. Therefore, stability of element characteristics is ensured.
また、この保護導体層、すなわち、延展部７−はソース
配線層７の一部分であるため、常にソース２と同電位に
保たれる。したがって、この保護導体層を設けたことに
より出力耐圧が低下することはない。Further, since this protective conductor layer, that is, the extension portion 7 - is a part of the source wiring layer 7 , it is always kept at the same potential as the source 2 . Therefore, the output breakdown voltage does not decrease due to the provision of this protective conductor layer.
第６図は、保護導体層を有するＭＯＳＦＥＴの出力耐圧
を示す図である。棒グラフＡは、第５図に示す従来の構
造、すなわち、ドレイン配線層８の一部分を保護導体層
として用いた装置における出力耐圧の頻度分布を示し、
棒グラフＢは、第１図に示す本発明に係る構造、すなわ
ち、ソース配線層７の一部分を保護導体層として用いた
装置における同分布を示す。グラフからも明らかなよう
に、従来の構造では、出力耐圧が５０Ｖ程度に低下して
しまうのに対し、本発明に係る構造では、出力耐圧は９
０Ｖ程度確保できることが、実験により確認された。こ
の理由は、第５図に示す構造では、チャネルＯＦＦ時に
延展部８′に負の電位が印加され、これによって低濃度
領域４の上部に正の電荷が誘引されるためと考えられる
。第１図に示す本発明に係る構造では、ＭＯＳＦＥＴで
はソース２が基板１に接続されて用いられるため、延展
部７−は基板１と同電位になり、上述のような現象が起
こらず、高出力耐圧を維持できるものと考えられる。FIG. 6 is a diagram showing the output withstand voltage of a MOSFET having a protective conductor layer. Bar graph A shows the frequency distribution of output breakdown voltage in the conventional structure shown in FIG. 5, that is, a device using a part of the drain wiring layer 8 as a protective conductor layer.
Bar graph B shows the same distribution in the structure according to the present invention shown in FIG. 1, that is, a device in which part of the source wiring layer 7 is used as a protective conductor layer. As is clear from the graph, in the conventional structure, the output withstand voltage drops to about 50V, whereas in the structure according to the present invention, the output withstand voltage drops to about 9V.
It has been confirmed through experiments that approximately 0V can be secured. The reason for this is thought to be that, in the structure shown in FIG. 5, a negative potential is applied to the extension portion 8' when the channel is turned off, thereby attracting positive charges to the upper part of the low concentration region 4. In the structure according to the present invention shown in FIG. 1, since the source 2 of the MOSFET is connected to the substrate 1, the extended portion 7- has the same potential as the substrate 1, and the above-mentioned phenomenon does not occur. It is thought that the output withstand voltage can be maintained.
第２図は、本発明の第２の実施例に係るＭＯＳＦＥＴの
構造断面図である。第１の実施例との相違は、アルミニ
ウムからなる保護導体層１０が、ソース配線層７あるい
はドレイン配線層８から独立しており、所定位置におい
てコンタクトホール１１を介してゲート９に接続されて
いる点である。FIG. 2 is a structural sectional view of a MOSFET according to a second embodiment of the present invention. The difference from the first embodiment is that the protective conductor layer 10 made of aluminum is independent from the source wiring layer 7 or the drain wiring layer 8, and is connected to the gate 9 through a contact hole 11 at a predetermined position. It is a point.
すなわち、保護導体層１０はゲート９と同電位に ・保
たれることになるが、チャネルＯＦＦ時にはゲート９は
ソース２と同電位となるため、第１の実施例と同じ効果
を奏することができる。That is, the protective conductor layer 10 is kept at the same potential as the gate 9, but when the channel is OFF, the gate 9 is at the same potential as the source 2, so the same effect as in the first embodiment can be achieved. .
以上゛、本発明を２つの実施例に基づいて説明したが、
本発明は要するに低濃度領域を保護導体層で覆い、この
保護導体層を少なくともチャネルがＯＦＦとなったとき
にソースとほぼ同電位に保つような構造であれば、どの
ような構造を採ってもかまわない。また、前述の実施例
はＰチャネル型のものであるが、Ｎチャネル型のものに
も同様に適用可能である。The present invention has been described above based on two embodiments, but
In short, the present invention covers the low concentration region with a protective conductor layer, and any structure can be used as long as the protective conductor layer is kept at approximately the same potential as the source at least when the channel is turned off. I don't mind. Furthermore, although the above-mentioned embodiments are of P-channel type, they are equally applicable to N-channel type.
以上のとおり本発明によれば、ＭＯＳＦＥＴの低濃度領
域を保護導体層で覆い、この保護導体層を少なくともチ
ャネルがＯＦＦとなったときにソースと同電位に保つよ
うにしたため、外部からの不純物の侵入を防止すること
により、素子特性の安定化を図ることができ、かつ、高
出力耐圧を確保できる。As described above, according to the present invention, the low concentration region of the MOSFET is covered with a protective conductor layer, and this protective conductor layer is kept at the same potential as the source at least when the channel is turned off. By preventing intrusion, element characteristics can be stabilized and high output withstand voltage can be ensured.
第１図は本発明の第１の実施例に係る半導体装置の断面
構造図、第２図は本発明の第２の実施例に係る半導体装
置の断面構造図、第３図は従来のアルミニウムをゲート
に用いた半導体装置の断面構造図、第４図は従来のポリ
シリコンをゲートに用いた半導体装置の断面構造図、第
５図は従来の保護導体層を設けた半導体装置の断面構造
図、第６図は本発明に係る装置と従来の装置との出力耐
圧の比較を示すグラフである。
］・・・半導体基板、２・・・ソース、３・・・ドレイ
ン、４・・・低濃度領域、５・・・絶縁層、６・・・ア
ルミニウムゲート、７・・・ソース配線層、７″・・・
延展部、８・・・ゲート配線層、８′・・・延展部、９
・・・ポリシリコンゲート、１０・・・保護導体層、１
１・・・コンタクトホール。
出願人代理人 佐 藤 −雄
＝ １１−
躬３図
も４図
１８開口ａＧ３−２０２９７０ （５）七力耐圧（Ｖ
）FIG. 1 is a cross-sectional structural diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional structural diagram of a semiconductor device according to a second embodiment of the present invention, and FIG. 4 is a sectional structural diagram of a semiconductor device using conventional polysilicon for the gate; FIG. 5 is a sectional structural diagram of a semiconductor device provided with a conventional protective conductor layer; FIG. 6 is a graph showing a comparison of the output breakdown voltage between the device according to the present invention and the conventional device. ]... Semiconductor substrate, 2... Source, 3... Drain, 4... Low concentration region, 5... Insulating layer, 6... Aluminum gate, 7... Source wiring layer, 7 ″...
Extension part, 8... Gate wiring layer, 8'... Extension part, 9
...Polysilicon gate, 10...Protective conductor layer, 1
1...Contact hole. Applicant's agent: Sato -Yu = 11- Mitsu 3 Figure 4 Figure 18 opening aG3-202970 (5) Seven-force withstand pressure (V
)
Claims (1)
インに隣接して設けられ前記ドレインの不純物濃度より
低い濃度で不純物を含む低濃度領域と、前記ソースと前
記ドレインとの間に形成されるチャネルを制御するため
のゲートと、を備える半導体装置において、前記低濃度
領域を覆うようにその上方に形成され、少なくとも前記
チャネルがＯＦＦとなったときに、前記ソースとほぼ同
電位となるように電気的に接続された保護導体層を設け
たことを特徴とする半導体装置。 ２、保護導体層が、ソースに対する配線層に接続されて
いることを特徴とする特許請求の範囲第１項記載の半導
体装置。 ３、保護導体層が、ゲートに対する配線層に接続されて
いることを特徴とする特許請求の範囲第１項記載の半導
体装置。 ４、半導体基板がシリコンからなり、ゲートがポリシリ
コンからなることを特徴とする特許請求の範囲第１項乃
至第３項のいずれかに記載の半導体装置。 ５、保護導体層がアルミニウムからなることを特徴とす
る特許請求の範囲第４項記載の半導体装置。[Claims] 1. On a semiconductor substrate, a source, a drain, a low concentration region provided adjacent to the drain and containing an impurity at a concentration lower than the impurity concentration of the drain, and the source and the drain. a gate for controlling a channel formed between the semiconductor devices, the gate being formed above the low concentration region so as to cover the low concentration region, and at least when the channel is turned off, the gate is substantially connected to the source. A semiconductor device comprising a protective conductor layer electrically connected to have the same potential. 2. The semiconductor device according to claim 1, wherein the protective conductor layer is connected to a wiring layer for the source. 3. The semiconductor device according to claim 1, wherein the protective conductor layer is connected to a wiring layer for the gate. 4. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor substrate is made of silicon and the gate is made of polysilicon. 5. The semiconductor device according to claim 4, wherein the protective conductor layer is made of aluminum.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62034439A JPS63202970A (en) | 1987-02-19 | 1987-02-19 | Semiconductor device |
| KR1019880001743A KR910003274B1 (en) | 1987-02-19 | 1988-02-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62034439A JPS63202970A (en) | 1987-02-19 | 1987-02-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63202970A true JPS63202970A (en) | 1988-08-22 |
Family
ID=12414258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62034439A Pending JPS63202970A (en) | 1987-02-19 | 1987-02-19 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS63202970A (en) |
| KR (1) | KR910003274B1 (en) |
-
1987
- 1987-02-19 JP JP62034439A patent/JPS63202970A/en active Pending
-
1988
- 1988-02-19 KR KR1019880001743A patent/KR910003274B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR910003274B1 (en) | 1991-05-25 |
| KR880010507A (en) | 1988-10-10 |
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