JPS63202065A - Frame transfer type solid-state image sensor - Google Patents
Frame transfer type solid-state image sensorInfo
- Publication number
- JPS63202065A JPS63202065A JP62034749A JP3474987A JPS63202065A JP S63202065 A JPS63202065 A JP S63202065A JP 62034749 A JP62034749 A JP 62034749A JP 3474987 A JP3474987 A JP 3474987A JP S63202065 A JPS63202065 A JP S63202065A
- Authority
- JP
- Japan
- Prior art keywords
- photoelectric conversion
- substrate
- term
- voltage
- impressed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000037433 frameshift Effects 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000003384 imaging method Methods 0.000 claims description 15
- 239000000969 carrier Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 13
- 238000002955 isolation Methods 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14887—Blooming suppression
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、ビデオカメラに使用されるフレーム・トラン
スファー型固体撮像素子に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a frame transfer type solid-state image sensor used in a video camera.
（ロ）従来の技術
フレーム・トランスファー型電荷結合素子方式（ＦＴ−
ＣＣＤ）固体撮像素子において、その構造上垂直スミア
現象が問題となる。垂直スミア現象とは、撮像部の一部
分に光を照射し、その出力信号をモニタテレビジョンで
観測した場合に照射部に対応した部分の上下に縦方向の
帯状の信号が現われる現象である。これは、撮像部から
蓄積部へのフレームシフト期間においても撮像部に光が
入射し、光電変換により発生したキャリアが転送用ＣＯ
Ｄに入り、転送され信号として出力されることが原因で
ある。例えば、箕谷他：クロスゲート構造のブルーミン
グ及び垂直スミアの抑制、テレビ学会枝根、ＴＥＢＳ
９４−５ ＥＤ ７７４（Ｆｅｂ、 １９ Ｂ ４
）等で説明きれている。(b) Conventional technology frame transfer charge-coupled device system (FT-
In solid-state image sensors (CCD), vertical smear phenomenon poses a problem due to their structure. The vertical smear phenomenon is a phenomenon in which when a portion of an imaging section is irradiated with light and the output signal is observed on a monitor television, vertical band-shaped signals appear above and below the portion corresponding to the irradiated section. This is because light enters the imaging section even during the frame shift period from the imaging section to the storage section, and carriers generated by photoelectric conversion are transferred to the CO for transfer.
This is because the signal enters D, is transferred, and is output as a signal. For example, Minaya et al.: Suppression of blooming and vertical smear in cross-gate structure, Television Society of Japan, TEBS
94-5 ED 774 (Feb, 19 B 4
) and so on.
ＦＴ−ＣＣＤ固体撮像素子において、垂直スミア現象を
低減する方法として次の３つが考えられている。第１は
フレーム転送周波数を高くする方法、第２は垂直スミア
成分を検出し、これによって映像信号を修正する方法及
び第３はフレームシフト期間の間だけ光をしゃ断する方
法である。The following three methods have been considered for reducing the vertical smear phenomenon in FT-CCD solid-state image sensors. The first method is to increase the frame transfer frequency, the second method is to detect the vertical smear component and modify the video signal accordingly, and the third method is to cut off the light only during the frame shift period.
（ハ）発明が解決しようとする問題点
しかしながら、これらの方法には以下の問題点が存在す
る。第１の方法は周波数増加に伴う転送用ゲートまわり
のアドミタンスの上昇により、周波数の増加にも限界が
ある。第２の方法については、周辺回路が複雑になりか
つ信号処理により画質劣化の恐れがある。第３の方法に
ついては、開時には光の透過率が高い高速の電気的なシ
ャッターを作ることは技術的に困難でありまた小型、軽
量であるはずの素子を大きなものあるいは高価なものに
してしまう。(c) Problems to be solved by the invention However, these methods have the following problems. In the first method, there is a limit to the increase in frequency due to the increase in admittance around the transfer gate as the frequency increases. Regarding the second method, the peripheral circuitry becomes complicated and the image quality may deteriorate due to signal processing. Regarding the third method, it is technically difficult to create a high-speed electric shutter that transmits a high amount of light when open, and the element that should be small and lightweight becomes large or expensive. .
（ニ）問題点を解決するための手段
本発明は斯上した問題点に鑑みてなされ、ＦＴ−ＣＣＤ
固体撮像素子の半導体基板内の光電変換領域の大きさを
光電変換期間とフレームシフト期間とで異ならしめて、
従来の垂直スミア現象を低減したＦＴ−ＣＣＤ固体撮像
素子を提供するものである。(d) Means for solving the problems The present invention has been made in view of the above-mentioned problems.
The size of the photoelectric conversion region in the semiconductor substrate of the solid-state image sensor is made different between the photoelectric conversion period and the frame shift period,
The present invention provides an FT-CCD solid-state imaging device that reduces the conventional vertical smear phenomenon.
（＊）作用
実質的な光電変換領域の大きさを外部信号の半導体基板
への印加により、フレームシフト期間において縮少させ
、フレームシフト期間に撮像部への光入射により発生す
るキャリアを低減きせることにより、垂直スミア現象を
減少させることが出来る。(*) Effect: By applying an external signal to the semiconductor substrate, the actual size of the photoelectric conversion region is reduced during the frame shift period, thereby reducing carriers generated by light incident on the imaging section during the frame shift period. This makes it possible to reduce the vertical smear phenomenon.
（へ〉実施例
以下に本発明に依るＦＴ−ＣＣＤ固体撮像素子の一実施
例を第１図および第２図を参照して詳述する。Embodiment An embodiment of the FT-CCD solid-state imaging device according to the present invention will be described in detail below with reference to FIGS. 1 and 2.
第１図は本発明に依るクロスゲート構造を持つＦＴ−Ｃ
ＣＤ固体撮像素子の構造を示す部分断面斜視図である。Figure 1 shows an FT-C with a cross-gate structure according to the present invention.
1 is a partially cross-sectional perspective view showing the structure of a CD solid-state image sensor.
このクロスゲート構造のＦＴ−ＣＣＤ固体撮像素子は０
Ｍ０８２層ポリシリコン・１Ｍアルミニウムプロセスで
製造され、第１図はその撮像部を図示している。This cross-gate structure FT-CCD solid-state image sensor has 0
It is manufactured using an M082-layer polysilicon/1M aluminum process, and FIG. 1 shows its imaging section.
第１図において、（１）（１’）は第１ゲート、（２）
（２’）は第２ゲートであり、ともにポリシリコンで形
成され、第１ゲート（１）（１’）は水平方向（図中の
Ｘ軸方向）に第２ゲート（２）（２’ ）は垂直方向（
図中のＹ軸方向）に延在され互いに直交して配置された
クロスゲート構造を採っている。第１ゲート（１）（１
’）下のシリコン基板（３）はフィールド酸化膜より成
る素子分離領域（４）の下を除いてゲート酸化膜（５）
を介してＮ型とする。また第２ゲート（２）（２′）下
のシリコン基板（３〉は素子分離領域（４）下を除いて
ゲート酸化膜（５）を介してＮ−型とする。第１ゲート
（１）（１″）および第２ゲート（２）（２″）に覆わ
れていない開口部分（６）の下はゲート酸化膜（５）を
介してＰ型とする。これらの３つの領域はＮ型シリコン
基板（７）の上面全面に設けたＰ型ウェル領域（８）表
面にイオン注入及び熱処理技術を用いて形成する。更に
素子分離領域（４）下には高不純物濃度のＰ＋型のチャ
ンネルストップ領域（９）を設ける。第１ゲート（１）
（１’）および第２ゲート（２）（２’）には４相のク
ロックパルスφ８．φ！ ＋ ｄ） ａ ＋φ、を印加
するためのアルミニウム電極（図示せず）が接続され、
基板（７）の裏面には金電極（１０）が形成されている
。なおＰ型ウェル領域（８）は基準電位零に固定きれ、
第２図に示すクロックパルスの波高値はこの基準電位を
零としたときの値である。In Figure 1, (1) (1') is the first gate, (2)
(2') is the second gate, both made of polysilicon, and the first gate (1) (1') is connected to the second gate (2) (2') in the horizontal direction (X-axis direction in the figure). is vertical (
A cross gate structure is adopted in which the gates extend in the Y-axis direction (in the figure) and are arranged orthogonally to each other. 1st gate (1) (1
') The lower silicon substrate (3) has a gate oxide film (5) except under the element isolation region (4) consisting of a field oxide film.
It is made into an N type via. In addition, the silicon substrate (3) under the second gate (2) (2') is made N- type through a gate oxide film (5) except under the element isolation region (4).The first gate (1) (1") and the second gate (2). The area under the opening (6) not covered by the second gate (2) (2") is made P type through the gate oxide film (5).These three regions are made N type. A P-type well region (8) provided on the entire upper surface of the silicon substrate (7) is formed using ion implantation and heat treatment techniques.Furthermore, a P+-type channel stop with a high impurity concentration is formed below the element isolation region (4). A region (9) is provided.A first gate (1).
(1') and the second gate (2) (2') have four-phase clock pulses φ8. φ! + d) an aluminum electrode (not shown) for applying a +φ, is connected;
A gold electrode (10) is formed on the back surface of the substrate (7). Note that the P-type well region (8) can be fixed at a reference potential of zero,
The peak value of the clock pulse shown in FIG. 2 is the value when this reference potential is set to zero.
Ｐ型ウェル領域（８）と基板（７）とで形成されるＰＮ
接合の深さは素子分光感度が視覚分光感度に近うくよう
に最適値を選択している。PN formed by P-type well region (8) and substrate (7)
The optimum depth of the junction is selected so that the element spectral sensitivity approaches the visual spectral sensitivity.
斯上した構造により、第１ゲート（１）（１’）および
第２ゲート（２）（２”）下にＰ型ウェル領域（８）内
に埋め込みＣＯＤを形成でき、縦型オーバーフロードレ
イン構造を持つ固体撮像素子が構成される。With the above structure, a buried COD can be formed in the P-type well region (8) under the first gate (1) (1') and the second gate (2) (2''), and a vertical overflow drain structure can be formed. A solid-state image sensor is constructed.
次にこの固体撮像素子の駆動方法を第２図のタイミング
チャートを参照して説明する。第１ゲート（１）（１’
）及び第２ゲート（２）（２’）にはそれぞれ、第２図
のタイミングチャートに示す、φ２．φ４゜−１，φ、
の電圧クロックパルスを印加する。奇数フィールドの光
電変換期間には、主にφ８が印加された第２ゲート（２
）下に、偶数フィールドのそれには主にφ、が印加され
た第２ゲート（２’）下に、光電変換により発生した信
号電荷が蓄積される。撮像部から蓄積部への転送の期間
は、伝統的な４相駆動であり、高速転送を行なう。蓄積
部から水平転送部への転送も４相駆動を用いる。Next, a method of driving this solid-state image sensor will be explained with reference to the timing chart of FIG. 1st gate (1) (1'
) and the second gates (2) (2') respectively have φ2. φ4゜-1, φ,
Apply a voltage clock pulse of . During the odd field photoelectric conversion period, the second gate (2
), signal charges generated by photoelectric conversion are accumulated under the second gate (2') to which φ is mainly applied in the even field. The period of transfer from the imaging section to the storage section is traditional four-phase drive, and high-speed transfer is performed. Four-phase drive is also used for transfer from the storage section to the horizontal transfer section.
本発明で最も特徴とする点は、第２図で示された時間変
化するφｓｕｂなる電圧クロックパルスをシリコン基板
（７）裏面上の金電極（１０）に印加することである。The most distinctive feature of the present invention is that a time-varying voltage clock pulse φsub shown in FIG. 2 is applied to the gold electrode (10) on the back surface of the silicon substrate (7).
光電変換期間には、比較的低い電圧を、また撮像部から
蓄積部への転送期間には、高い電圧をＮ基板（７）に印
加する。印加電位は、Ｎ基板＜７〉側が正極（＋）とな
るような逆方向に印加する。φｓｕｂのタイミングは第
２図のタイミングチャートに示すとおりである。光電変
換期間のφｓｕｂの電圧は、ブルーミング抑圧が充分で
かつ感度低下が起こらないよう決定し、撮像部から蓄積
部へのフレームシフト期間では、転送効率低下と感度低
下が起こらずかつスミアの抑制が充分となるように決定
する。A relatively low voltage is applied to the N substrate (7) during the photoelectric conversion period, and a high voltage is applied during the transfer period from the imaging section to the storage section. The applied potential is applied in the opposite direction so that the N substrate <7> side becomes the positive electrode (+). The timing of φsub is as shown in the timing chart of FIG. The voltage of φsub during the photoelectric conversion period is determined so that blooming suppression is sufficient and sensitivity decrease does not occur, and during the frame shift period from the imaging section to the storage section, transfer efficiency and sensitivity decrease do not occur and smear is suppressed. Decide that it will be sufficient.
この結果、Ｐ型ウェル領域（８）上に埋め込みＣＯＤを
持つＮ型基板（７）の裏面に逆方向バイアスを印加する
ことにより、Ｐ型ウェル領域（８）とＮ型基板（７）間
の空乏層の拡がりを制御することが出来る。これは、Ｐ
型ウェル領域（８）内で光電変換により発生した電荷が
逆方向印加電圧を高くすればするほどＮ型基板（７〉側
により多くの重荷がはき出されることを利用するもので
ある。したがって光電変換期間には、Ｎ型基板（７）裏
面に印加する逆方向バイアス電圧を低圧にすることによ
り、光電変換により発生した信号電荷が効率良く転送の
ためのＣＣＤに蓄積されるようになり、フレームシフト
期間には高圧の電圧を印加することによりＣＯＤに入り
込む、光電変換により発生した電荷を抑えることすなわ
ち、スミア低減が出来る。要約すると、実質的な光電変
換領域の大きさを光電変換期間は拡大し、フレームシフ
ト期間で、は縮少することが出来る固体撮像素子を実現
できる。As a result, by applying a reverse bias to the back surface of the N-type substrate (7) having an embedded COD on the P-type well region (8), the gap between the P-type well region (8) and the N-type substrate (7) is The expansion of the depletion layer can be controlled. This is P
This method takes advantage of the fact that the higher the voltage applied in the reverse direction, the more the charge generated by photoelectric conversion in the type well region (8) is exposed to the N-type substrate (7> side. Therefore, the photoelectric conversion During this period, by lowering the reverse bias voltage applied to the back surface of the N-type substrate (7), the signal charges generated by photoelectric conversion are efficiently accumulated in the CCD for transfer, resulting in frame shift. By applying a high voltage during the photoelectric conversion period, it is possible to suppress the charge generated by photoelectric conversion that enters the COD, that is, to reduce smear.In summary, the photoelectric conversion period expands the size of the actual photoelectric conversion area. It is possible to realize a solid-state imaging device that can reduce the frame shift period.
（ト）発明の効果
本発明に依れば、Ｎ型基板（７）上のＰ型ウェル領域（
８）に埋め込みＣＯＤを形成し、Ｎ型基板（７）とＰ型
ウェル領域（８）とで形成されるＰＮ接合の逆方向バイ
アスを光電変換期間とフレームシフト期間で変化させる
ことにより、光電変換領域の大きさを光電変換期間には
拡大しフレームシフト期間には縮少することができるの
で、半導体基板内のみで垂直スミア現象を大幅に低減で
きるフレーム・トランスファー型固体撮像素子を実現で
きる利点を有する。(G) Effects of the Invention According to the present invention, the P-type well region (
8), and by changing the reverse bias of the PN junction formed by the N-type substrate (7) and the P-type well region (8) between the photoelectric conversion period and the frame shift period, photoelectric conversion is performed. Since the size of the area can be expanded during the photoelectric conversion period and reduced during the frame shift period, we have the advantage of realizing a frame transfer type solid-state image sensor that can significantly reduce the vertical smear phenomenon only within the semiconductor substrate. have
第１図は本発明に依るＦＴ−ＣＣＤ固体撮像素子を説明
するための部分断面斜視図、第２図は本発明のＦＴ−Ｃ
ＣＤ固体撮像素子の駆動方法を説明するためのタイミン
グチャート図である。
（１）（１’）は第１ゲート、 （２）（２’）は第２
ゲート、 （３）は半導体基板、 （４）は素子分離領
域、（５）はゲート酸化膜、 （６）は開口部、
（７）はＮ型基板、 （８）はＰ型ウェル領域、 （９
）はチャンネルストップ領域、 （１０）は金電極であ
る。FIG. 1 is a partial cross-sectional perspective view for explaining an FT-CCD solid-state image sensor according to the present invention, and FIG. 2 is a FT-CCD solid-state image sensor according to the present invention.
FIG. 3 is a timing chart diagram for explaining a method of driving a CD solid-state image sensor. (1) (1') is the first gate, (2) (2') is the second gate
gate, (3) is the semiconductor substrate, (4) is the element isolation region, (5) is the gate oxide film, (6) is the opening,
(7) is an N-type substrate, (8) is a P-type well region, (9
) is the channel stop region, and (10) is the gold electrode.
Claims (1)
により発生したキャリアが前記撮像部の電荷結合素子に
蓄積される光電変換期間と前記撮像部から蓄積部に転送
しているフレームシフト期間とで制御されるフレーム・
トランスファー型固体撮像素子において、前記光電変換
期間と前記フレームシフト期間とで半導体基板内の光電
変換領域の大きさを異ならしめたことを特徴とするフレ
ーム・トランスファー型固体撮像素子。(1) It has an imaging section and a storage section, and has a photoelectric conversion period during which carriers generated by photoelectric conversion in the imaging section are accumulated in a charge-coupled device of the imaging section, and are transferred from the imaging section to the storage section. Frame shift period and frame control
1. A frame transfer solid-state image sensor, characterized in that the photoelectric conversion region in the semiconductor substrate has a different size between the photoelectric conversion period and the frame shift period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62034749A JP2517258B2 (en) | 1987-02-18 | 1987-02-18 | Frame transfer type solid-state image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62034749A JP2517258B2 (en) | 1987-02-18 | 1987-02-18 | Frame transfer type solid-state image sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63202065A true JPS63202065A (en) | 1988-08-22 |
| JP2517258B2 JP2517258B2 (en) | 1996-07-24 |
Family
ID=12422978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62034749A Expired - Lifetime JP2517258B2 (en) | 1987-02-18 | 1987-02-18 | Frame transfer type solid-state image sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2517258B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5667977A (en) * | 1979-11-09 | 1981-06-08 | Toshiba Corp | Substrate voltage control method of charge transfer element |
-
1987
- 1987-02-18 JP JP62034749A patent/JP2517258B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5667977A (en) * | 1979-11-09 | 1981-06-08 | Toshiba Corp | Substrate voltage control method of charge transfer element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2517258B2 (en) | 1996-07-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |