JPS63201990A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To arrange bit lines densely by constituting an address decoder section of a NAND circuit and an inverter made of 2-transistor (TR). CONSTITUTION:The address decoder is constituted of a 4-input NAND circuit 1 and 4 inverters each consisting of P-channel MOS TRs 11-14 as load TRs and N-channel MOS TRs 15-18 as driving TRs. Only when the output signal of the 4-input NAND circuit 1 is at L level and address signals A1-A4 are at H level, the level of output signals (01-04) of the inverters go to H, the N-channel MOS TRs Q1-Q8 between data lines (DL1-DL4, inverse of DL1 - inverse of DL4) and bit lines (BL1-BL4, inverse of BL1 - inverse of BL4) are turned on and a signal is transmitted between the data line and the bit line. Since the inverter of the 2-TR is arranged between the bit lines of the address decoder section, the pitch between the bit lines is made small and the arrangement corresponding to high circuit integration is attainable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device, and particularly to a circuit constituting an address decoder section of the semiconductor memory device.

2. Description of the Related Art It is well known that an address decoder section of a semiconductor memory device is constructed by a NAND circuit and a NOR circuit as logical product circuit means. FIG. 2 shows a conventional example in which a unit block is composed of one four-man powered NAND circuit and four two-man powered NOR circuits. Note that this conventional example is
The entire address decoder is constructed from a plurality of blocks. The output signal of the four-man power NAND circuit 1 is connected in parallel to one input part of each of the four two-man power NOR circuits 2 to 5, and the respective address signals At-A4 are connected to the other input part of each of the four two-man power NOR circuits 2 to 5. is input. Further, the output signals of each of these NOR circuits 2 to 5 are connected to each gate electrode of four sets of MoS transistors Q1 to Q8 for connection between data lines and bit lines. Here, the odd-numbered MOS transistors Q+, Qs, QS, and Q7 are connected to positive signals of the four sets of data lines and bit lines<DL1 to DL4. BLI～BL
4), and connects even numbered MOS transistors Q2. Q4. Qe and Qa are the inverted signals (DLI to DL4°BLI to BL4) of the four sets of data lines and bit lines.
). This circuit operation is performed by four people
Output signal of ND1, that is, two-man NOR circuits 2 to 5
The input signal of each one becomes low level "L", and
When the other input signal of each two-man power NOR circuit, that is, the address signal inversion signal (Al-A4) becomes "L", the output signal of two-man power NOR circuits 2 to 5 becomes 0.
1 to 04 become high level "H". Then, each MOS
The output signals 01 to 04 of the transistors Q1 to Q8 are H"
When , each data line is transmitted.

Problems to be Solved by the Invention According to the conventional technology, the address decoder section of a semiconductor memory device is composed of one NAND circuit and two NOR circuits. For a pair of bit lines, one two-man power N
An OR circuit is required. Increasing the number of memory cells in a semiconductor memory device and achieving higher integration requires narrowing the pitch of the bit lines, but since conventional NOR circuits use four transistors, there is a limit to the pitch of the bit lines. There was a problem in that the degree of integration was restricted in the address decoder section.

Means for Solving the Problems The semiconductor memory device of the present invention has an address decoder section with NA
It is composed of an ND circuit and an inverter having a two-transistor configuration, the output signal of the NAND circuit is used as the input signal of the inverter, the address signal is input to the source of the load side transistor of the inverter, and the output signal of the inverter is It has a circuit configuration connected to the gate electrode of a MOS transistor for connection between data line and bit line.

According to the structure of the present invention, since a two-transistor inverter is placed between the bit lines of the address decoder section, the pitch between the bit lines can be reduced and an arrangement suitable for high integration is possible.

Embodiment An embodiment of the present invention is shown in FIG. The address decoder of the present invention includes a four-power NAND circuit 1 and P-channel MOS transistors 11 to 11 as load-side transistors.
14 is an n-channel MOS as a drive transistor.
This is an embodiment of one block composed of four inverters using transistors 15 to 18. The output signal of the 4-person NAND circuit 1 is "L", and the address signal A
Only when l-A4 is "H", the inverter output signal (O1-04) becomes "H", and the n-channel MO8) transistors Q1-Q8 in between are turned on, and each data line-bit Signals are transmitted between lines. Here, the output signals 01 to 04 of the inverters are, for example, when one output signal 01 is "H", all other nodes are "L" because the address signals A2 to A4 are -L". Become.

Therefore, two data lines and two bit lines are never connected at the same time.

Effects of the Invention According to the present invention, it becomes possible to arrange bit lines densely, which is highly effective in increasing the degree of integration and reducing the depth.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an address decoder section of a device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of an address decoder section in a conventional example. 1...4-manpower NAND circuit, 11-14...
...P channel MOS transistor, 15-18.
...DL1 to DL4 ...Bit line, BL
I~BL4゜BLI~BL4...Bit line, Q
1 to Q8...N-channel MOS transistors for connection between bit line and data line. Name of agent Patent attorney Toshio Nakao and 1 other person fd input N
ANDI payoff lf ~ 14-P charge off MOS) Lance 71.5
~Ill-4 Zuyara Pain νMQS) Langimeta 01~
Qδ−fu′2+Ya・n茅ノνMO, S）Randsukuman
l Figure 2

Claims (1)

[Claims] The address decoder section is constituted by AND circuit means and an inverter, the output signal of the AND circuit means is connected to the input of the inverter, the address signal is input to the source of the load-side transistor of the inverter, and the output of the inverter is A semiconductor memory device that has a circuit configuration that inputs a signal to the gate electrode of a MOS transistor for connecting a data line and a bit line.