JPH04176093A - Memory circuit - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by connecting a data line and an inverted data line to the input of first and second inverters via transistors and directly inputting and outputting data to and from, respectively, the input of the inverters. CONSTITUTION:A RAM memory 41 has inverters 50 and 51 and transistors 52 and 53. When the RAM memory 41 falls in a read condition, the data outputs O1-On of an address 0 are directly outputted. When the memory 41 is written, when -WE is at Low and data is 0, an nch transistor 403 becomes 0n, an output alphabecomes Low and therefore the D side of the RAM cell 41 becomes Low. When the data is 1, an nch transistor 404 becomes ON, an output beta becomes Low and therefore the D side of the RAM cell 41 becomes High. Thus, the necessity of providing a hardware as a register other than the RAM is removed and a circuit scale is reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to memory circuits.

[Conventional technology]

A conventional memory circuit is shown in FIG. 4, and RA in FIG.
M cell 10 is shown in FIG. FIG. 6 shows an example of a signal processing circuit using the conventional memory circuit shown in FIG. 4.

In FIG. 4, a large number of RAM cells 10 are arranged and R
The AM cells 10, D, are connected to a pair of digit lines, and the RAM cells 10, A, are grouped together by a horizontal line and connected to an address decoder 11.

In FIG. 5, the RAM cell 10 in FIG. 4 is a MOS)
transistors 20 and 21 and two inverters 22 and 23
and has.

In FIG. 6, a memory circuit 30 consisting of the RAM shown in FIG. 4, an input register 31, and an output register 32 are shown.
are connected by a data bus 33. When writing to or reading from the memory circuit 30, it is not possible to use the memory circuit 30 as an interface because it is not possible to write to or read from the memory circuit 30 on a temporary basis, similar to a register. Therefore, in addition to the memory circuit 30, input/output registers 31 and 32 were provided.

[Problem to be solved by the invention]

In conventional memory circuits, since the RAM 30 cannot be used as a temporary register, a temporary register is specially provided in hardware, which has the disadvantage of increasing the circuit scale.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit which solves the above-mentioned drawbacks and which requires a small circuit scale.

[Means to solve the problem]

The configuration of the memory circuit of the present invention is such that the output of the first inverter is connected to the input of the second inverter, the input of the first inverter is connected to the output of the second inverter, and the first . A data line and an inverted data line are respectively connected to the inputs of the second inverter via transistors. Alternatively, data is directly input/output from the input/output of the second inverter.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a memory circuit according to an embodiment of the present invention.

In FIG. 1, the memory circuit of this embodiment includes a RAM memory 41 arranged in a grid pattern, a write circuit 40 arranged in a - column, and an address decoder 42.

Here, the RAM memory 41 is D, D-human power, and Q
output, and α, β, and A inputs, and the Q output is passed through an inverter 43 to output Q s + Q2 + .

It becomes QTl.

FIG. 2 is a circuit diagram showing the RAM memory 41 of FIG. 1. In FIG. 2, this RAM memory is connected to an inverter 5.
0.51 and MOS) transistors 52 and 53.

FIG. 3 is a circuit diagram showing the write circuit 40 of FIG. 1. In FIG. 3, this write circuit includes MOS transistors 1403, 404 . ! :, NOR game) 401, 402
and inverter 405.

In FIGS. 1 to 3, when the memory is in the read state, data outputs 01 to 01 at address O. is output directly.

Next, when writing to the memory, when U is LOW and data is O, the nch transistor 403 is turned on and the output α becomes N Low. Therefore, the D side of the RAM cell 41 becomes Low.

When the data is 1, the nch transistor 404 is turned on and the output β becomes Low. Therefore, RAM cell 41
The D side of becomes High.

FIG. 7 is a circuit diagram showing a RAM memory of a memory circuit according to another embodiment of the present invention.

In FIG. 7, the RAM memory of this embodiment is a MOS)
It has transistors eo and et, and inverters 62 and 63.

In FIG. 7, when the memory is in a read state, the output of the inverter 62 is directly output to the outside of the memory.

〔Effect of the invention〕

As explained above, in the present invention, the output of one inverter is input to the input of the other inverter, the input of the inverter is connected to the data line, the inverted data line, and an N-channel transistor, and the input of each inverter is connected to the input of the inverter. Since it has the function of inputting data directly and outputting data directly from the output of the inverter,
Since AM cells can be used as registers, this RAM
There is no need to provide any other hardware as a register (
This has the effect of reducing the circuit scale.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a RAM cell in FIG. 1, and FIG.
Figure 4 is a block diagram of a conventional memory circuit, Figure 5 is a circuit diagram of a RAM cell in Figure 4,
FIG. 6 is a block diagram showing a signal processing circuit using the memory circuit of FIG. 4, and FIG. 7 is a block diagram showing a memory portion of another embodiment of the present invention. 10.41...RAM cell, 11.42...Address decoder, 20, 21, 52, 53, 60°61.4
03,404...MOS) transistor, 22, 23
．． 43. 50. 51. 62. 63. 405
...Inverter, 40L 402...NOR gate, 31...Input register, 32...Output register, 33...Data bus, 40...Write circuit.

Claims (1)

[Claims] The output of the first inverter is connected to the input of the second inverter, the input of the first inverter is connected to the output of the second inverter, and the inputs of the first and second inverters each have data. line, an inverted data line is connected through a transistor, and the first or second
A memory circuit characterized in that data is directly input/output from the input/output of an inverter.