JPS62234292A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To contrive to lower power consumption by providing a sense amplifier to execute the differential amplifying only of the information of a memory cell and the second sense amplifier selected by a column selecting signal and transferred to an input/output bus. CONSTITUTION:The information of all memory cells M selected through one word line W by a row decoder 1 is transferred to respective pairs of a digit line D and an inversion D and differentially amplified by a sense amplifier S2 at the time of inputting a sense-up enable signal. Next, a column decoder 2 turns on switch transistors T1-T4 and the control transistor of a sense amplifier S3 connected to a pair of a digit line D and an inversion D by a column selecting signal Y. As such a result, the information of a digit line is transferred to an input output bus I/O and an inversion I/O by the amplifier S3. Consequently, since the power consumption of the amplifier S2 is small and operated only temporarily, the power consumption is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which information can be read from and written to any memory address at any time at a constant speed.

[Conventional technology]

A conventional semiconductor memory device of this type will be explained with reference to the drawings.

As an example is shown in FIG. 3, in a conventional semiconductor memory device of this type, a sense amplifier S1 is disposed only at one end of a pair of two digit lines DD.

The information of all the memory cells M selected by the row decoder l is transmitted to each set of digit lines or D via one word line W, and this information is differentially amplified by the sense amplifier Sl. , whose differential amplified outputs are transmitted to each set of digit lines and D. Column decoder 2ri outputs a set of digits &! by one column selection signal Y. Switch transistors T1 and T2 connected in series to D and D are turned on, respectively. Information on a set of digit lines D-D is transmitted via the input/output bus I1 through these switch transistors T1-T.
0・10K is transmitted.The information of other memory cells M selected by the word line W is also differentially amplified by the sense amplifier 81, but since the switch transistors T1 and T2 corresponding to these information are off, the input/output is Bus I10・l
10K cannot be transmitted 0 When the conventional example shown in FIG. 3 is highly integrated, the memory cell M connected to one digit 1llI31D or D
As a result, the parasitic capacitance increases and the sensitivity of the sense amplifier S1 deteriorates. To solve this problem, the digit line DD is divided into multiple parts to reduce the parasitic capacitance. However, due to the multi-division of the digit line DD, the number of switch transistors T, lp2 connected to the output buses I10 and Ilo also increases, so that the parasitic capacitance of the input/output buses I10 and Ilo increases. Therefore, in addition to differentially amplifying the information in the memory cell M, the sense amplifier 1 is required to amplify the information in order to transfer the information to the input/output bus I10.

Due to high integration and multi-division of digit lines D-D, the power consumption of sense amplifier S1 includes a portion for differential amplification of information in memory cell M, and a portion for transfer to output bus 10 and Ilo. The amplification for the first and second cases will be equal to each other, or the latter will be larger.

It is sufficient that only one sense amplifier S1 corresponding to the digit line D selected by the column selection signal Y is operating at this time, but in the conventional example shown in FIG. is also working.

[Problem that the invention seeks to solve]

As explained above, the conventional semiconductor memory device has the disadvantage of high power consumption because all sense amplifiers that do not need to operate operate.

An object of the present invention is to solve the above-mentioned drawbacks and provide a semiconductor memory device with low power consumption.

[Means for solving problems]

The semiconductor memory device of the present invention includes a first sense amplifier, two digit lines forming a set with one end connected to each of the differential terminals of the first sense amplifier, and two first switch transistors corresponding to each of the digit lines of L to L and controlled on/off by a column selection signal, and each of the differential terminals connected in series through each of these two first switch transistors. a second sense amplifier which is connected to the other end of each of the two digit lines and whose operation or non-operation is controlled by the column selection signal; and each of the differential terminals of the second sense amplifier. and two second switch transistors that are connected in series with each of the first switch transistors and are controlled on and off by the column selection signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 f
a) and (b) are the sense amplifier S2φS in FIG.
FIG. 3 is a circuit diagram showing 3.

As shown in FIG. 2(a), one end of the digit line D-D is connected to each of the two differential terminals of the sense amplifier S2, and these digit lines D-D form one set. . A sense amplifier enable signal 5AE (omitted in FIG. 1) is applied to the common terminal of the sense amplifier S2, and the sense amplifier 82 operates only when the sense amplifier enable signal SAE is input. A memory cell M is arranged at the intersection of the digit line D and the word line W. Each word line W is connected to a row decoder 1. Figure 2 fb)
As shown in the figure, the other ends of the -silk digit lines DD are connected to two differential terminals of the sense amplifier S3 through switch transistors T3 and T4 in series, respectively. Further, each of these differential terminals is connected to input/output buses I10 and Ilo via switch transistors TI-T2 in series. Since these switch transistors T1 to T4 are on/off controlled by the column selection signal Y, the digit line D-D corresponding to the sense amplifier S3 for which the column selection signal Y is not selected by the column decoder 2 is connected to the input/output bus l1O- Not connected to Ilo.

The sense amplifier enable signal SAE is applied to the common terminal of the sense amplifier S3 via the transistor T, and the transistor T is also on/off controlled by the column g signal Y. Amplifier S3 does not operate even when sense amplifier enable signal 8AE is input.0 Information of all memory cells M selected by row decoder 1 via one word line W is transmitted to each set of digit line or D. Sense Ang Enable Signal SAW
These pieces of information are differentially amplified by the sense amplifier S2 at the time of input, and the differential amplified output is transmitted to each set of digit lines and D. The column decoder 2 uses one column selection signal Y to turn on the switch transistors TI to T4 connected to the negative set of digit lines DD and the transistor T of the sense amplifier 3 connected to these switch transistors. As a result, the information on the digit lines D-D corresponding to the column selection signal Y becomes the sense amplifier enable signal SAE.
When input, the signal is amplified by the sense amplifier S3 and transmitted to the input/output bus I1O-Ilo.

The information of one memory cell M is transferred to the input/output bus I10/Ilo.
When data is transferred to the memory cell M, one sense amplifier S2 and one sense amplifier S3 corresponding to the memory cell M operate.

The sense amplifier S3 is connected to the input/output bus I10 with large parasitic capacitance.
・Power consumption increases because it is necessary to drive Ilo, but only one operates at a time.O Sense amplifier S2 only needs to differentially amplify the information in memory cell M, and is used as an input/output bus with large parasitic capacitance. I10・I
Since there is no need to drive lo, the consumption power is extremely small, and the sum of the extinction powers of all sense amplifiers S2 can be ignored compared to the power consumption of one sense amplifier S3.

〔Effect of the invention〕

As explained in detail above, the semiconductor memory device of the present invention
By having the first sense amplifier perform only differential amplification of the information in the memory cells, the power consumption of the first sense amplifier can be reduced, and the information differentially amplified by the first sense amplifier 7 is transferred to the input/output bus. Since only one of the second sense amplifiers selected by the column selection signal is operated, power consumption is reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the semiconductor memory device of the present invention, FIG. 2 (a), [b) is a circuit diagram showing the sense amplifiers S2 and S3 in FIG. FIG. 1 is a block diagram showing an example of a semiconductor memory device. 1...Row decoder, 2...Column decoder, D-D...Deck), 1%, Ilo/Il
o...Input/output bus, M...memory cell, 5z-83...Sense amplifier% T1 to T4
...Switch transistor, W...Word line, Y...Column selection signal. 11Jc g"','・;・ Agent Patent attorney Uchihara Hi,,51-1・' D・25: Deλji... Shoreline y7~14: Switch transistor gel l10-le 6: To the upper blade" S W: Zord Forest N
；Me7ri-t and full Y;Departure''-Meζ, I′
α No. S2/S3: Zensuanfu 0 'jiEl'vf! J SAE: 7-ring A〉F' material--Flui neck-ch (a-) Fig. 2

Claims (1)

[Claims] A first sense amplifier; two digit lines forming a set with one end connected to each differential terminal of the first sense amplifier; Two first switch transistors that correspond one-to-one to each of the lines and are controlled on/off by a column selection signal, and each of the differential terminals is connected to the a second sense amplifier that is connected to the other end of each of the two digit lines and whose operation/non-operation is controlled by the column selection signal; and a differential terminal of the second sense amplifier. A semiconductor memory device comprising: two second switch transistors connected in series with each of the first switch transistors and controlled on/off by the column selection signal.