JPS60150296A - Static memory circuit - Google Patents

Abstract

PURPOSE:To reduce the number of data bus lines and to attain a high integration by actuating selectively a differential amplifying circuit at the time of reading, not actuating the differential amplifying circuit at the time of writing and by actuating selectively a transfer gate. CONSTITUTION:Read data bus lines RDB, RDB and write data bus lines WDB, WDB are made in common to be data bus lines DB and DB. A read data bus line RDB and write data bus WDB are made in common to be a data bus line DB. The data bus lines DB and DB are connected to an input circuit 24 to which a write control signal WE is impressed. A word line WL is selected by a column decoder 22 actuated by receiving a column address AR, and a read column output YjR is outputted by a column decoder 23 which receives a column address Ac and receives a read/write control signal WE. A write column output YjW is also outputted from the decoder 23.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor memory circuit using MOS transistors,
In particular, it relates to the input/output configuration of static random access memory (hereinafter referred to as RAM). Static memory is widely used in fields that require fast access operations. In the study and memory, a differential amplifier is provided as a sense amplifier for each digit, and the output of the differential amplifier for each digit is commonly connected to the readout path line, and the selection of the digit is This is done by operating only the differential amplifiers for digits and digits.On the other hand, since the differential amplifiers for each digit can only be used for reading, each digit and t line is written through a transfer gate. For this reason, separate pass lines must be provided for the read system and the write system, which has been a major impediment to higher integration of circuits.

An object of the present invention is to provide a state memory circuit that is advantageous for high integration.

A static memory circuit according to the present invention includes a pair of A fins, a pair of digit lines, a pair of transfer gates connected and separated between the pair of digit lines and a pair of pass lines, and a pair of digit lines. and a differential amplification circuit whose output is connected to the pair of pass lines, the differential amplification circuit is activated when selected during reading, and the differential amplification circuit is inactivated during writing. It is characterized in that the transfer gate is activated when selected.

According to the present invention, both read data and write data can be transmitted through a common path line by switching the differential amplifier and transfer gate between read and write operations.

According to the present invention, the number of data bus lines can be reduced by approximately half, which is advantageous for increasing the degree of memory integration.

An example of a conventional study memory circuit will be explained with reference to FIG. In FIG. 1, a memory cell C is arranged in place of the word line WL digit line DG, DG.

FETs Q1 to Q are N-channel transistors and constitute a sense amplifier 1 that senses the differential voltage between digit lines DG and DG.

The output of sense amplifier 1 is the load “B T Qa −Qy
The read data bus lines RDH and RDB are connected to the read data bus lines RDH and RDB. This sense amplifier 1 is controlled by the output signal Yja of a decoder that can take the selection level of ``11'' level only during reading.Transfer gate F'
Both ETQ4 and qe are decoder output signals Yiw whose gates are selectively set to 1'1'' level only during writing.
are connected, and write data buses WDB and W are connected during writing.
Connect each to the DB.

The read data buses RDB, RT)B are connected to the output amplifier 3, and the write data buses WDT3. WDB is connected to input circuit 2.

As explained above, in the configuration of the conventional differential sense-amplifier circuit, RDB, RDB.

Four data bus lines, WDB and WDB, were required. By the way, in a Tatabit-based RAM, for example, a RAM with 8 bits of Ilo, there are 4 bits for each I10.
Because 1 data bus line is required, the total RAM is 32
Two data bus lines are required. This increase in the number of data bus lines leads to an increase in the chip area of the RAM, which is a problem in multi-bit RAMs.

Next, an embodiment according to the present invention will be described with reference to FIG.

In FIG. 2, the same reference numerals are used for parts corresponding to those in FIG. 1, and the explanation thereof will be omitted.

The difference in configuration between FIG. 2 and FIG. 1 is that read data bus lines RDB, RDB and write data bus lines WDB, WDB are made common, respectively, and data bus lines D=B, I)H, The read data bus line RDB and the write data bus line WDB are shared and the data
This is what we did with the bus line DB. Data bus vs. DB, D
B is connected to the input/output circuit 24 to which the input/output terminal Dx10% write control signal WE is applied. In the present invention, when reading and when selected, FETQs is turned on and the difference □
Dynamic sense amplifier 1 is not activated and the other F E T
When Q4=Qs becomes non-conductive, read data is given to L5- buses 1iDB and DB. On the other hand, when writing, Q is turned off and the differential sense amplifier 1 is inactive. Even if the write data bus line is shared, the voltage is applied to the digit lines DG and DG.Therefore, the circuit operation is exactly the same as in the prior art.

The word line WL is selected by the ite decoder 22 which operates in response to the eve address AR, and the read column output Y j
R receives column address Ac and read/write control signal W
It is output from column decoder 23 which receives E. A write column output Yjw is also output from the decoder 23.

As explained above, in the present invention, the differential sense amplifier only requires two data bus lines, which is half the number of data bus lines in the prior art. For example, in a RAM having an Ilo of 8 bits, only 16 data bus lines are required, and the number of data bus lines can be reduced by 16 compared to the conventional technology. This is very effective when considering miniaturization of RAM chips.

Furthermore, it goes without saying that the present invention is not limited to the embodiments of the present invention, but can be applied to various ranges that satisfy the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional memory circuit, and FIG. 2 is a circuit diagram showing a memory circuit according to an embodiment of the present invention. WL...Word line, C...Memory cell, DG. DG...Digital line, RDB, RDB...
...Read data bus line, WDB, WDB...
...Write data bus line, DB, DB...
・Read/write common data bus line, Yjw,
Yjw...Decoder output signal %Q1~Q,・
...N-channel transistor, l...Differential sense amplifier. 7- Figure 1

Claims (1)

[Claims] In a static memory circuit in which memory cells are arranged at the intersections of word lines and digit line pairs, a pair of input/output bus lines and a transfer gate pair are connected between the pair of input/output bus lines and the digit line pair. and a differential amplifier provided for each digital and digital line pair, the output of which is commonly connected to the input/output bus line, and when reading, only the selected differential amplifier is operated, and when writing A state characterized in that sometimes only a pair of transfer gates connected to a selected digit line pair is operated.
memory circuit.