JPH1196752A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an effective band width of a random access port by executing the read/write operation of the random access port when the data are transferred between a serial register and a memory cell array. SOLUTION: A timing generator 7 inputs a command signal, an address signal and a clock signal, and outputs a bank activation signal, a row address signal, a column address signal and a data transfer signal at every banks B0-Bm. Respective banks B0-Bm receive respectively the bank activation signals to be operated independently, and are provided respectively with a row decoder 3, a column decoder 5, a sense amplifier 4, the memory cell array 1 and a data transfer gate 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a dual-port semiconductor memory device having a random access memory (RAM) and a serial access memory (SAM).

[0002]

2. Description of the Related Art A dual-port type semiconductor memory device comprises:
By having the SAM section, a higher-speed operation than that of the general-purpose dynamic RAM is realized, and it is widely used as a memory for image processing.

FIG. 5 is a block diagram showing an example of a conventional dual-port type semiconductor memory device. Hereinafter, description will be made based on this drawing.

In the random access port, a memory cell is selected by a row address decoder 101 and a column address decoder 102 based on a row address and a column address inputted from address input terminals A _{0 to} A _j, and a read / write operation is performed on the memory cell. The operation of the sense amplifier 103, I /
It comprises an O bus 104 and a data input / output buffer 105. The serial access port has an address buffer 10
6, a serial selector 108 which inputs a tap address and a stop address and reads / writes data in the serial register 107 in order from the tap address to the stop address, and a data transfer cycle from the memory cell array 109 to the serial register 107 according to a data transfer cycle. It comprises a serial data input / output buffer 110 for reading and writing from the serial register 107 to the memory cell array 109.

[0005] The features of this conventional operation are that a read / write operation from a random access port and a read / write operation from a serial register of a serial access port are performed.
This means that the write operation and the write operation can be performed simultaneously and asynchronously. On the other hand, the read / write operation of data between the serial register and the memory cell array is performed in a data transfer cycle, but the read / write operation of the random access port at this time needs to be stopped.

[0006]

A first problem of the prior art is that the effective bandwidth of the read / write operation of the random access port is limited by the data transfer cycle for controlling the data transfer between the memory cell array and the serial register. Is to be reduced. The reason is that the data transfer cycle stops the operation of the entire memory.

A second problem of the prior art is that the size of the memory chip is increased because the capacity of the serial register is as large as the number of sense amplifiers or half thereof. The reason is that a large amount of data is transferred in one data transfer cycle by increasing the capacity of the serial register in order to reduce the influence of the first problem.

[0008]

SUMMARY OF THE INVENTION A first object of the present invention is to improve the effective bandwidth of a random access port by enabling a read / write operation of a random access port when transferring data between a serial register and a memory cell array. It is to provide a semiconductor memory device.

A second object of the present invention is to achieve the first object of the present invention, which eliminates the need for using a large-capacity serial register as in the prior art. An object of the present invention is to provide a semiconductor memory device capable of reducing the chip size by increasing the number of transfers.

[0010]

A dual port type semiconductor memory device according to the present invention receives a command signal, an address signal, and a clock signal from a command input terminal group, an address input terminal group, and a clock input terminal to activate a bank. A timing generator for outputting a signal, a row address signal, a column address signal, and a data transfer signal; a serial register for storing serial data; a memory cell for storing random data; a sense amplifier for amplifying data of the memory cell; A data transfer gate for transferring data between the memory cell and the serial register by inputting a transfer signal, and inputting the row address signal and the column address signal and inputting the row address and the column from the memory cell; Line deco to select data corresponding to address And a serial read / write bus connecting the serial register and the data transfer gate, and data input / output provided between the serial register and a serial access input / output terminal. A serial input / output buffer for amplifying data, a random input / output buffer provided between each bank and a random access input / output terminal, and amplifying data to be input / output, and connecting the random input / output buffer to each bank. And a random read / write bus.

The timing generator inputs a command signal, an address signal, and a clock signal from a command input terminal group, an address input terminal group, and a clock input terminal, and outputs a bank activation signal, a row address signal, a column address signal, and a data transfer signal. Occurs. Each of the banks performs a data read / write operation on a memory cell by inputting a row address and a column address, and performs a data read / write operation between a serial register and a memory cell by a data transfer signal. .

A memory cell array (bank) connected to a common read / write bus and capable of independently performing a random read / write operation or a data transfer operation, and having one bank perform a random read / write operation, , The random read / write operation and the data transfer operation can be performed simultaneously.

[0013]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device according to the present invention. Hereinafter, description will be made based on this drawing.

The timing generator 7 receives a command signal and an address input terminal group 7 from a command input terminal group 71.
2 and a clock signal from the clock signal input terminal 73, respectively.
00, a bank activation signal, a row address signal, a column address signal, and a data transfer signal are output for each of the banks B0 to Bm via the row address signal line group 300, the column address signal line group 400, and the data transfer signal line group 100. . Each bank B
0 to Bm can operate independently in response to the respective bank activation signals, and have a row decoder 3, a column decoder 5, a sense amplifier 4, a memory cell array 1, and a data transfer gate 2. Column decoder 5 of each bank B0-Bm
And a random input / output buffer 8 are connected by a random read / write bus 500. The data transfer gates 3 of the banks B0 to Bm are connected to the serial read / write bus 60.
0 is connected to the serial register 6. The other end of the serial register 6 is connected to a serial input / output buffer 9, and the other end of the serial input / output buffer 9 is connected to a serial access input / output terminal 91. The other end of the random input / output buffer 8 is a random access input / output terminal 81
It is connected to the.

FIG. 2 is a timing chart showing an example of the operation of the semiconductor memory device of FIG. Hereinafter, the operation of the semiconductor memory device according to the present embodiment will be described with reference to FIGS.

First, in synchronization with the clock signal at the clock signal input terminal 73, "R1" is input to the command input terminal group 71.
, The address of “X1” is input to the address input terminal group 72. In response to the command and the address, the timing signal 7 activates the bank activation signal line group 2
Part 200-1 of 00 is activated. At the same time, “X ₁ ” is generated in the row address signal line group 300. Bank B0 corresponding to this bank activation signal is connected to another bank B1.
To Bm, the command “R
1 'from by entering a column address activation signal "C _1" and column address "Y _1", after a certain Reitenmi period, the column address activation signal "C _1" and column address "Y
By inputting " ₁ ", the random access input / output terminal 8
1 outputs data “q ₁ ”. Next, in accordance with the timing at which the output of the data “q1” by the “R1” command ends, the command “R ₂ ”, the row address “X ₂ ”,
The column address “Y ₂ ” and the column address activation command “C
By entering ₂ ", data can be output without interruption to" q ₂ "immediately after the" q ₁ ".

When serial data transfer is performed from the bank Bm during this read operation, the command input terminal group 71
And a data transfer command “D” to the address input terminal group 72.
m "and the data transfer address" Xm ", one of the data transfer signal line groups 100-m is activated, and the data group corresponding to the row address Xm is transferred to the serial register 6 via the serial read / write bus 600. Forwarded through. This data is stored in the serial register 6
The data is sequentially output from a serial access input / output terminal 91 via a serial input / output buffer 9.

FIG. 3 is a block diagram showing an example of a bank in the semiconductor memory device of FIG. Hereinafter, description will be made with reference to FIGS.

As is known, the memory cell array 1 outputs the data selected by the row decoder 3 to the bit line pair 700 passing through the memory cell array 1 as a small signal difference.
This is amplified by a sense amplifier 4 composed of flip-flops composed of N-channel transistors 45 and 46 and P-channel transistors 43 and 44, thereby giving a sufficient difference potential to the bit line pair 700. The bit line pair 700 is connected to a random read / write bus 500 via N-channel transistors 52 and 53.
The gates of the N-channel transistors 52 and 53 are connected to a column address selection circuit 51 by a column address selection signal line 54.
It is connected to the.

In this example, the sources of the N-channel transistors 22 and 23 are connected to the bit line pair 700 passing through the memory cell array 1, the drains thereof are connected to the serial read / write bus 600, and the N-channel transistor 2
The gates 2 and 23 are connected to a data transfer signal line 1001 common to other bit line pairs.

Next, the operation of the bank of this embodiment will be described.

First, when bank activation signal line group 200 is activated and a row address signal is input from row address signal line group 300, data corresponding to the row address of memory cell array 1 is stored in each bit line pair 700. Is output to Further, when the sense amplifier activating circuit 41 receives the bank activating signal from the bank activating signal line group 200 and generates the sense amplifier activating signal 42, each minute potential difference output to the memory cell 1 is amplified. .

Here, in the case of the random read operation, one of the column address selection signal lines 54 is activated by the column address input from the column address signal line group 400, and the column address of the data of the sense amplifier 4 is One selected data is output to the random read / write bus 500. In the case of the random write operation, data of the random read / write bus 500 is written to the bit line pair 700 in which one of the column address selection signal lines 54 is activated and the N-channel transistors 52 and 53 are turned on, similarly to the read operation. .

On the other hand, in the case of the read data transfer operation, after the amplification by the sense amplifier 4 is completed, the data transfer signal line 1001 is activated to activate the sense amplifier 4.
Are output to the serial read / write bus 600. In the case of write data transfer, by activating the data transfer signal line 1001 before the sense amplifier 4 is activated, data of the respective serial read / write buses 600 can be simultaneously written to all portions of the sense amplifier 4. it can.

A plurality of banks B0 to Bm performing this operation are arranged as shown in FIG. 1 and connected to a common random read / write bus 500 and serial read / write bus 600.
By operating the banks B0 to Bm independently as shown in FIG. 2, data transfer can be performed while the read / write operation of the random access input / output terminal 81 is performed without interruption. Thereby, the effective bandwidth of the read / write operation of the random access input / output terminal 81 can be improved.

FIG. 4 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention. Hereinafter, description will be made based on this drawing.

The present embodiment aims at reducing the overall chip size by reducing the capacity of the serial register 61 and dividing the data transfer gate 21 into a plurality. In this embodiment, since the capacity of the serial register 61 is small, the chip size can be reduced without increasing the input / output bandwidth of the serial access memory by increasing the number of data transfers.

[0028]

The first effect is that the effective bandwidth of the random access port can be improved. The reason is that by having a plurality of banks that independently perform a random read / write operation or a data transfer operation, one bank can simultaneously perform a random read / write operation and the other bank can simultaneously perform a data transfer operation.

The second effect is that the chip size can be reduced. The reason is that, since the effective bandwidth of the random access port can be improved, the number of data transfers can be increased even if the capacity of the serial register is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart showing an example of the operation of the semiconductor memory device of FIG. 1;

FIG. 3 is a block diagram showing an example of a bank in the semiconductor memory device of FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention.

FIG. 5 is a block diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

B0 to Bm Bank 1 Memory cell array 2 Data transfer gate 3 Row decoder 4 Sense amplifier 5 Column decoder 6 Serial register 7 Timing generator 8 Random input / output buffer 9 Serial input / output buffer 21 Divided data transfer gates 22, 23, 45, 46 , 52, 53 N-channel transistor 41 Sense amplifier activation circuit 42 Sense amplifier activation signal line group 43, 44 P-channel transistor 51 Column address selection circuit 54 Column address selection signal line 61 Small capacity serial register 71 Command input terminal group 72 Address input terminal group 73 Clock signal input terminal 81 Random access input / output terminal 91 Serial access input / output terminal 100 Data transfer signal line group 200 Bank activation signal line group 300 Row address signal line group 4 00 column address signal line group 500 random read / write bus 600 serial read / write bus 700 bit line pair

Claims (3)

[Claims] 1. A dual-port semiconductor memory device comprising: a random access memory unit having a memory cell array; and a serial access memory unit having a serial register. In the random access memory unit, the memory cell array is divided into a plurality. And a data transfer gate for performing a data read / write operation between the serial register and the divided memory cell array. Semiconductor storage device. 2. A command signal, an address signal, and a clock signal are input from a command input terminal group, an address input terminal group, and a clock input terminal, and a bank activation signal, a row address signal, a column address signal, and a data transfer signal are output. A timing generator, a serial register that stores serial data, a memory cell that stores random data, a sense amplifier that amplifies data in the memory cell, and a memory cell that communicates with the serial register by inputting the data transfer signal. A data transfer gate for transferring data between the memory cells, and a row decoder and a column decoder for inputting the row address signal and the column address signal and selecting data corresponding to the row address and the column address from the memory cells. A plurality of banks and the serial A serial read / write bus connecting the register and the data transfer gate; a serial input / output buffer provided between the serial register and the serial access input / output terminal to amplify input / output data; A semiconductor memory device comprising: a random input / output buffer provided between an access input / output terminal and amplifying data to be input / output; and a random read / write bus connecting the random input / output buffer and each of the banks. 3. The data transfer gate according to claim 1, wherein the data transfer gate is divided into a plurality of parts in the bank, and the capacity of the serial register is reduced in accordance with one capacity of the divided data transfer gate. Semiconductor storage device.