JPS60234299A - Decoder circuit - Google Patents

Abstract

PURPOSE:To suppress the level fluctuation of a non-selected word line by using a clock produced by an address signal to control a latch circuit provided to a word line. CONSTITUTION:When a NAND gate NA produces a decoding signal of a low level, word lines W0-W3 are set under a non-selected state respectively. While clocks phiX00-phiX11 of address decoding outputs of AND gates An1-An4 of a decoding circuit are supplied to NAND gates NA1-NA4 of the 2nd decoding circuit. Then the outputs of gates NA1-NA4 corresponding to selected word lines W0-W3 are set at high levels. Therefore FETM28-M31 of latch circuits of selected lines W0-W4 are turned off and no drive current flows to an earth. Thus the power consumption is reduced. While FETM28-M31 of non-selected lines W0-W4 are turned on, and lines W0-W4 are grounded and kept at low potentials. Thus, it is possible to suppress the level fluctuation of the non-selected word line due to noises, etc.

Description

[Detailed Description of the Invention] [Technical Field] The present invention provides an 0MO
8 (Complementary Insulated Gate Field Effect Transistor) This relates to a technique that is effective when applied to a decoder circuit, for example, a technique that is effective when applied to a decoder circuit in a semiconductor memory circuit.

[Background technology]

As memory capacity increases and the number of addresses increases, decoder circuits become more complex and the pitch of word lines becomes smaller. Therefore, dynamic RAM (Random Access Me
ROM (Read Only Mem)
A generally known method is to divide the output of a decoder into two or four, as used in the following.

FIG. 1a shows a four-division decoder circuit used in a dynamic RAM. NO is Noah Gate,
When all address bits are low level, high level output is obtained. φx00 to φxll are two address signals Ai
−Aj, and φxoO=A
i −A J t φxo1=Ai・A 3 eφxl
o=Ai-Aj, φxll=Ai-Aj
It is. All transistors used in this circuit are N-channel type MO8FETs.

Vx is an internal voltage. ”2 signals φx00 to φxl
l is input to one electrode of MOSFET M5 to M8, and the output of the NOR gate No. is input to the MOSFET M5 to M8.
It is input to the control electrodes (gates) of s to M15. As a result, when the output of the NOR gate No is at a high level and the signal φxlO is at a high level, the word line W is driven to a high level, and the remaining word lines are driven to a low level. In this way, the output of the NOR gate NO is divided into four according to the signals φxoO to φx1.1.

In addition, MOSFETs M1 to M4 are cut M○5FE
T, and is provided to enable MOSFETs M, to M8 to perform self-boosting.

φw1 is a DC latch circuit (MOSFET M9 to
This is the input signal of M12). As a latch circuit to prevent unselected word lines from floating,
A flip-flop shown in FIG. 1 may also be used. φW
C is a word clear signal for lowering the potential of a word line selected in a cycle when precharging the memory.

In the circuit of Figure 1a, the MOSFETs M, -M1□ are
In order to latch with high resistance including the selected word line, the above M
Since the mutual conductance gm of the O8FET cannot be large, it is weak as a latch for unselected word lines, and as shown in FIG. 1, there is a problem that the layout area becomes large when a flip-flop is used.

For dynamic RAM, see Japanese Patent Application Laid-Open No. 57-8228.
It is described in detail in Publication No. 2.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a decoder circuit that can be configured with a small number of elements and can prevent level fluctuations of unselected word lines.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the signal φx0 formed by the address signal
0 to φxll to suppress level fluctuations of unselected word lines by controlling latch circuits provided in the word lines.

〔Example〕

FIG. 2 is a decoder circuit showing one embodiment of the present invention.

In this embodiment circuit, the Nant gate NA outputs are connected to CMOS inverters 1, 2, 3, . and 4.

MOSFETs constituting the above CMOS inverters 1 to 4
Clock signal φx00 and MOS are connected to the drain of M2O.
The clock signal φxo is connected to the drain of F E TM22.
1. The drain of MOS FET M24 has a clock signal φxo1, M OS F ETM
A clock signal φ11 is supplied to the drains of 26, respectively.

(4) The CMOS inverter outputs have word lines W0 to W3.
A latch MOSFET M is coupled to the C0M5 inverter at the far end of the word lines W0 to W3.
m~M3. is provided.

Inverted signals φx00 to φxll of decode signals φx00 to φxll are supplied to the gates of these MO8FETs for latch, respectively. The above signals φx00 to φxll are
It is a signal formed by decoding two address signals Ai and Aj, and φxoo=Ai” A j
+ φx01= A i −A j , φxlo=A
i − A j .

φx11=Ai−Aj. 5 to 12 are memory cells, respectively.

Next, the operation of this embodiment will be explained.

When the Nant gate NA forms a low level decode signal, this causes the word line W to become low. -W3 is selected.

When, for example, clock signal φxOO of decode signals φxOO to φxll is set to high level according to address A i yAj, word line Wo is selected.

On the other hand, the decode signal φxo1 is the address signal A
When set to high level according to i, Aj, word line W is selected. Word line W. is selected, the inverted signal φxOO of the decode signal φxoO is applied to the gate of the latch MO8FET M2g.
Since it is supplied from A1, the MO8FET M2B is turned off and non-conductive. This causes the word line W to be connected from the inverter 1 to the word line W. The drive current supplied to the MOSFE
It is possible to prevent the voltage from flowing to the ground potential of the circuit via TM2B, and it is possible to reduce power consumption. On the other hand, M29. M2O, M3. is turned on and its potential is set to low level.

This can prevent the potentials of unselected word lines from varying due to noise or the like.

Furthermore, depending on the logic of the clock signal φwe supplied to the Nant gates NAI to NA4, the latch MO8FET
M2B~M3. can also be used as a word clear circuit. That is, after a read or write operation,
If the clock signal φwe is set to a low level, all of the latching MO3FETs u28 to M3 are turned on, and the selected word line can be brought to a low potential (low level) in a short time.

In the circuit of this embodiment, only the decoder portion for the four word lines W0 to W3 is shown, but the decoder portion for the four word lines W4 to W3 is shown.
... is also provided with a decoder circuit configured in the same way as shown.

FIG. 3 shows waveforms when applied to a dynamic RAM. Precharge period (address strobe signal RA
S=high level), the above signals φxOO to φx
Since ll is set to high level, the potential of the word is pulled down by the latching MO8FET. Therefore,
When applied to a dynamic RAM, the word line clear MO8FET shown in FIG. 1 is not necessarily required. In the figure, the solid line is a waveform when selecting a word line, and the dotted line is a waveform when making a word line non-selected.

In the above explanation, 4 divisions were described as an example, but application to 2m divisions (m is a natural number) is also possible.

〔effect〕

(7) (1) The output from the Nant gate NA is received by the CMOS inverters 1 to 4, and the decode signals φxoO, φx01°φx10. By supplying φ
The effect is that the number of OSFET elements can be reduced.

(2) MO8FET for latch provided on the word line
In M2B, M2g, M2O, and M3u, the above decode signal φx00. is applied to the gates of these MOSFETs.
φx01. φx10. Inverted signal of φxll φX00゜φ
x10. φx01. By supplying φXll, the latch MO8FET on the selected word line is turned off, thereby reducing power consumption. Conversely, the latch MO8FET on the unselected word line is turned on, and the unselected word line is pulled down to low level. Therefore, even if noise or the like is added to an unselected word line, it is possible to prevent the level from fluctuating (8), and it is possible to obtain the effect that malfunction of the memory can be prevented.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the circuit of this embodiment, there are 4 word lines W. ~W3. Although only the decoder portion for the word lines W4 to W'y -We to Wtl is shown, the decoder having the same configuration as shown is also provided for the word lines W4 to W'y -We to Wtl . Although this embodiment has been described using 4 divisions as an example, it is also possible to apply □ to 2m divisions (m is a natural number).

[Application field]

The present invention can be effectively applied to, for example, a semiconductor integrated circuit in which a decoder output is divided to drive a word line.

rare

[Brief explanation of the drawing]

Figure 1a is a circuit diagram of a four-division decoder circuit used in a dynamic memory (DRAM), Figure 1 is a circuit diagram of a latch circuit, and Figure 2 is a circuit diagram of a decoder circuit of the present invention. , Figure 3 is
FIG. 3 is a waveform diagram when the present invention is applied to a DRAM. NO... Noah game 1~, M, ~Ml,...N channel MO3FET, NA-=Nant gate, Ar+s-
A n 4...AND gate, NA, ~NA4...Nand gate, 1-4...CMOS inverter, 5-1
2...Memory cell (11) Fig. 1 U Fig. 1 b

Claims (1)

[Claims] 1. A first decoder circuit that generates a word line selection output by inputting a plurality of bits of address signals, and a word line formed by the output of the first decoder circuit and the address signal. a second decoder circuit to which a clock signal is supplied for selecting the word line, and a latch circuit is provided on the word line. 2. The decoder circuit according to claim 1, wherein the first decoder circuit is constituted by a Nandt gate, and the second decoder circuit is constituted by a complementary insulated get field effect transistor. 3. The decoder circuit according to claim 1 or 2, wherein the latch circuit can also be used as a word clear circuit depending on the logic of the clock signal.