JPS6320011B2 - - Google Patents

Info

Publication number
JPS6320011B2
JPS6320011B2 JP57155862A JP15586282A JPS6320011B2 JP S6320011 B2 JPS6320011 B2 JP S6320011B2 JP 57155862 A JP57155862 A JP 57155862A JP 15586282 A JP15586282 A JP 15586282A JP S6320011 B2 JPS6320011 B2 JP S6320011B2
Authority
JP
Japan
Prior art keywords
island
single crystal
pattern
silicon
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57155862A
Other languages
Japanese (ja)
Other versions
JPS5946021A (en
Inventor
Shigenobu Akyama
Shigeji Yoshii
Koichi Kugimya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP57155862A priority Critical patent/JPS5946021A/en
Publication of JPS5946021A publication Critical patent/JPS5946021A/en
Publication of JPS6320011B2 publication Critical patent/JPS6320011B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683Continuous wave laser beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02598Microstructure monocrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691Scanning of a beam

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体集積回路、特に高密度、高性
能な半導体集積回路の製造方法に関するものであ
り、完全絶縁分離された単結晶半導体の島の形状
及びその製造方法に係わるものである。完全絶縁
分離された単結晶半導体の島の形成は、前記単結
晶半導体の島につくり込まれる素子の電気特性を
飛躍的に向上せしめ、高速、低消費電力素子の実
現をもたらす重要な技術である。また、高集積化
を目指して考えられている積層構造の3次元素子
の実現にとつて、特に重要な技術と言える。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing semiconductor integrated circuits, particularly high-density, high-performance semiconductor integrated circuits. and its manufacturing method. The formation of completely isolated single-crystal semiconductor islands is an important technology that dramatically improves the electrical characteristics of devices built into the single-crystal semiconductor islands, leading to the realization of high-speed, low-power consumption devices. . It can also be said to be a particularly important technology for realizing tertiary elements with a stacked structure, which is being considered with the aim of achieving high integration.

従来例の構成とその問題点 従来より、絶縁分離された半導体結晶の島とし
てSOS構造があることは周知の通りである。SOS
構造はサフアイヤ(単結晶アルミナAl2O3)基板
上にシリコン(Si)単結晶が形成されているもの
であり、絶縁物基板としてSiと格子定数の近い単
結晶Al2O3を用い、気相エピタキシアル成長によ
り、Al2O3基板上に単結晶Si層が形成されてい
る。しかしながらかくして得られたSi単結晶には
気相エピタキシアル成長の際にAl2O3基板よりAl
の拡散が生じたり、また、Al2O3とSiの格子定数
のわずかな違い等により欠陥が発生してしまうこ
とは避けられ得ない。したがつてSOS構造のシリ
コン単結晶に素子をつくり込んだ場合、期待され
る程の特性向上が得られ難い。さらに、エピタキ
シアル成長の際に1000℃程度の高温工程を経るこ
とや活性素子上にさらにAl2O3を形成することの
困難さなどのために、たとえば、3次元素子の実
現には程遠い。
Conventional structure and its problems It is well known that there is an SOS structure as an island of isolated semiconductor crystals. SOS
The structure consists of a silicon (Si) single crystal formed on a saphire (single crystal alumina Al 2 O 3 ) substrate, and a single crystal Al 2 O 3 with a lattice constant similar to that of Si is used as the insulator substrate. A single crystal Si layer is formed on an Al 2 O 3 substrate by phase epitaxial growth. However, the Si single crystal thus obtained has Al 2 O 3 from the Al 2 O 3 substrate during vapor phase epitaxial growth.
It is unavoidable that defects will occur due to diffusion of Al 2 O 3 and the slight difference in lattice constant between Al 2 O 3 and Si. Therefore, when an element is fabricated in a silicon single crystal with an SOS structure, it is difficult to obtain the expected improvement in characteristics. Furthermore, the realization of, for example, a tertiary element is far from being realized due to the high temperature process of about 1000° C. during epitaxial growth and the difficulty of further forming Al 2 O 3 on the active element.

こうした状況の中で、最近SiO2やSi3N4などの
非晶質絶縁物上に非単結晶Siを堆積したのち、レ
ーザや電子ビームなどのエネルギービームを照射
して単結晶化する方法が試みられており、種々の
構造が提案されている。
Under these circumstances, a method has recently been developed in which non-single crystal Si is deposited on an amorphous insulator such as SiO 2 or Si 3 N 4 and then irradiated with an energy beam such as a laser or an electron beam to form a single crystal. Attempts have been made and various structures have been proposed.

単結晶化の制御のために、たとえば、絶縁物基
板にグレーテイングを設けるグラフオーエピタキ
シアル法がある。これは、第1図にその断面図を
示すように、あらかじめ形成した絶縁物基板1上
のグレーテイングにより単結晶Si層2として所望
の方位が得られるとされている。しかしながら上
記の方法では、グレーテイングの構造やエネルギ
ービームの照射条件等の制御が困難であり、所望
の方位の単結晶Si層を得ることが困難であり、制
御困難なグレーテイングの工程が増えることにも
なるなど問題点が多い。
For controlling single crystallization, for example, there is a graph-o-epitaxial method in which a grating is provided on an insulating substrate. As shown in the cross-sectional view of FIG. 1, it is said that a desired orientation of the single crystal Si layer 2 can be obtained by grating on the insulating substrate 1 formed in advance. However, with the above method, it is difficult to control the grating structure and energy beam irradiation conditions, etc., and it is difficult to obtain a single crystal Si layer with a desired orientation, which increases the number of grating processes that are difficult to control. There are many problems such as becoming

また、第2図に断面図を示すラテラルエピタキ
シアル法と呼ばれている方法が提案されている。
この方法は、絶縁膜たとえばSiO211の一部を
開口して、下地基板の単結晶Si10の一部を露出
せしめたのち非単結晶Siたとえば多結晶Si12を
堆積し、たとえばレーザビームを照射して多結晶
Si12を再結晶化せしめる際、単結晶Si基板10
の露出部10Aを種として単結晶Si12Aが横方
向に成長してSiO211上に形成されるものであ
る。しかしながら、上記第2図の方法では、種と
しての単結晶Si基板10の露出部10Aから横方
向へ伸びた単結晶Si12Aの領域には限界があ
り、単結晶Si基板10の露出部10Aからある程
度離れた多結晶Si12Bの部分までは、再結晶化
においても成長した単結晶Si12Aが伸びて来
ず、大きな単結晶を得ることは困難である。この
ため、種となる露出部10Aを細かい間隔で数多
く形成することが考えられているが、この場合、
各々の種から成長して伸びてきた単結晶同志が接
触する部分で粒界となつてしまい、やはり、大き
な単結晶を得ることが困難であるとともに、下地
の単結晶部の開口部が多数必要となり完全絶縁分
離された単結晶半導体の島を得ることはむずかし
い。
Furthermore, a method called a lateral epitaxial method, a cross-sectional view of which is shown in FIG. 2, has been proposed.
In this method, a part of the insulating film, for example, SiO 2 11, is opened to expose a part of the single crystal Si 10 of the base substrate, and then non-single crystal Si, such as polycrystalline Si 12, is deposited, and then irradiated with, for example, a laser beam. polycrystalline
When recrystallizing Si 12, single crystal Si substrate 10
The single crystal Si 12A is grown laterally using the exposed portion 10A of the SiO 2 as a seed and is formed on the SiO 2 11. However, in the method shown in FIG. 2, there is a limit to the area of the single crystal Si 12A that extends laterally from the exposed portion 10A of the single crystal Si substrate 10 as a seed, and to a certain extent from the exposed portion 10A of the single crystal Si substrate 10. Even during recrystallization, the grown single crystal Si 12A does not extend to the distant polycrystalline Si 12B, making it difficult to obtain a large single crystal. For this reason, it has been considered to form a large number of exposed portions 10A that serve as seeds at small intervals, but in this case,
Grain boundaries occur where single crystals that have grown from each seed come into contact, making it difficult to obtain large single crystals and requiring many openings in the underlying single crystal. Therefore, it is difficult to obtain islands of single crystal semiconductor that are completely insulated.

次に第3図のaに示す5角形の平面形状を有す
るシリコン島22を用いた報告例に触れる。第3
図bはこの断面図であり、シリコン基板20上に
SiO221が形成され、さらにシリコン島22が
形成されている。この報告はマテリアルズ リサ
ーチ ソサアテイ シンポジアプロシーデイング
ス(Materials Research Society Symposia
Proceedings)vol.1の「Laser and Electron−
Beam Solid Interactions and Materials
Processing」のP493ならびにP498に示されてい
るものである。このP493にはレーザビームによ
る再結晶化に際し、尖つた先端22Aから核形
成、核成長が生じているように示されているが、
結晶成長は不充分である。特に大きな島の場合に
は、その尖つた先端22Aに最初にエネルギービ
ームが入ることは少なく、例えば、5回のビーム
走査で全域をおおうとすれば、1/5の確率で尖端
にビームがあたるのみで、他の4本は尖端に当ら
ず先端22Aは核形成源になり得ないという欠点
がある。また、P498には、核形成が島の端部で
はなく中央部から生じていることが示されてお
り、尖端の効果がないことを示している。これら
の例をみても、このような尖端の効果について
は、定説はなく不明な点が多い。
Next, we will discuss a reported example using a silicon island 22 having a pentagonal planar shape as shown in FIG. 3a. Third
Figure b is a cross-sectional view of this, in which
SiO 2 21 is formed, and silicon islands 22 are further formed. This report was published in the Materials Research Society Symposia Proceedings.
Proceedings) vol.1 “Laser and Electron−
Beam Solid Interactions and Materials
These are shown on P493 and P498 of "Processing". P493 shows that nucleation and growth occur from the sharp tip 22A during recrystallization using a laser beam.
Crystal growth is insufficient. Especially in the case of a large island, it is rare for the energy beam to first enter the pointed tip 22A. For example, if you try to cover the entire area with five beam scans, the beam will hit the tip with a probability of 1/5. However, since the other four do not touch the tip, the tip 22A cannot serve as a nucleation source. P498 also shows that nucleation occurs from the center of the island rather than the edges, indicating that there is no tip effect. Even looking at these examples, there is no established theory about the effect of such a tip, and there are many unknown points.

発明の目的 本発明は、このような従来の問題に鑑み、島の
平面形状を考慮することにより、非晶質絶縁物基
板上に完全絶縁分離した単結晶半導体の島を形成
し、かくして形成した島に素子をつくり込んで高
速、低消費電子素子の形成を可能とし、さらに活
性素子を積層したいわゆる3次元素子の実現に好
適な半導体装置を得ることを目的とする。
Purpose of the Invention In view of such conventional problems, the present invention forms a single crystal semiconductor island completely insulated and isolated on an amorphous insulator substrate by considering the planar shape of the island. It is an object of the present invention to obtain a semiconductor device which enables the formation of high-speed, low-consumption electronic elements by building elements into islands, and which is also suitable for realizing so-called tertiary element elements in which active elements are laminated.

発明の構成 本発明は、再結晶化により良質な半導体の島状
パターンを形成するに際し、半導体膜を、エネル
ギービーム走査の開始側の辺全体が平面形状にお
いて微細な凹凸を有する島状パターンに形成し、
この微細な凹凸部分を始点としてレーザや電子ビ
ームなどのエネルギービームを走査しながら照射
することにより島状パターンを再結晶化する方法
である。本発明では全てのビーム走査時にビーム
が島の端部に設けられている凹凸を覆うように再
結晶化することにより、前記半導体の島の全てを
単結晶化するかあるいは結晶粒径の極めて大きな
単結晶群を得ることを実現するものである。すな
わち、本発明は絶縁物基板上に非単結晶半導体層
を形成したのち写真蝕刻法および選択酸化法ある
いは絶縁物埋め込み法等の工程により、前記凹凸
を有する島状パターンを形成し、この島状パター
ンをエネルギービームにて再結晶化し、制御性良
く良質な単結晶半導体島を可能ならしめるもので
ある。
Composition of the Invention The present invention, when forming a high-quality semiconductor island pattern by recrystallization, forms a semiconductor film into an island pattern in which the entire side on the start side of energy beam scanning has minute irregularities in a planar shape. death,
This is a method of recrystallizing the island pattern by scanning and irradiating an energy beam such as a laser or an electron beam starting from this fine uneven portion. In the present invention, by recrystallizing the beam so as to cover the unevenness provided at the end of the island during all beam scanning, all of the semiconductor islands can be made into single crystals or crystal grains with extremely large grain size can be formed. This makes it possible to obtain a single crystal group. That is, in the present invention, after forming a non-single-crystal semiconductor layer on an insulating substrate, an island-like pattern having the above-mentioned unevenness is formed by a process such as photolithography, selective oxidation, or insulator embedding. By recrystallizing the pattern with an energy beam, it is possible to form single crystal semiconductor islands with good controllability and high quality.

実施例の説明 第4図は、本発明の第1の実施例における完全
絶縁分離された半導体単結晶の島の構造を示し、
第4図のaはたとえば第4図bの−′線断面
図であり、第4図のbは平面形状図の一例であ
る。30は半導体素子(図示せず)の作り込まれ
た単結晶シリコン基板、31,31′は基板30
上に形成したSiO2、32は完全絶縁分離され単
結晶化されたシリコン島であり、32Aはシリコ
ン島32の端部に形成した微細な矩形あるいはノ
コギリ歯状のパターンである。第4図からわかる
ように、前記島32のエネルギービーム走査が開
始される一辺全体に形成された平面形状において
凹凸を有する微細パターン32Aは、島の全体形
状に比べて小さく、しかもその形は種々選択でき
るものである。第4図bでは、種々な微細パター
ン32Aを有する島32の4つの例を示してい
る。
DESCRIPTION OF EMBODIMENTS FIG. 4 shows the structure of a completely insulated semiconductor single crystal island in a first embodiment of the present invention,
4A is, for example, a sectional view taken along the line -' in FIG. 4B, and FIG. 4B is an example of a plan view. 30 is a single crystal silicon substrate on which a semiconductor element (not shown) is built; 31 and 31' are substrates 30;
The SiO 2 layer 32 formed above is a silicon island which is completely insulated and made into a single crystal, and 32A is a fine rectangular or sawtooth pattern formed at the end of the silicon island 32. As can be seen from FIG. 4, the fine pattern 32A having unevenness in the planar shape formed on the entire side of the island 32 where energy beam scanning is started is smaller than the overall shape of the island, and its shape is various. It is a choice. FIG. 4b shows four examples of islands 32 with various fine patterns 32A.

第5図は、本実施例の製造工程を断面図によつ
て説明するものである。第5図のaに示すごとく
たとえばシリコン基板30を水蒸気雰囲気中で酸
化してSiO231を1.0μm形成したのち、たとえば
減圧気相成長法により600℃で多結晶シリコン4
2を0.5μm成長させる。次に同図のbのように、
保護酸化膜50、シリコン窒化膜51を順次成長
させ、通常の写真蝕刻法により選択的に第4図b
に示す島32と同じパターンを有する保護酸化膜
50、シリコン窒化膜51を残し、さらに残留し
ているシリコン窒化膜51の下部以外の多結晶シ
リコン42をおよそ半分の厚みになるようエツチ
ング除去する。更に続いて同図のcに示すごと
く、水蒸気雰囲気中で酸化して、シリコン窒化膜
51の下部以外の多結晶シリコン42を完全に酸
化し、選択酸化膜31′を形成して、SiO231,
31′により完全に絶縁分離されるとともに微細
パターン32Aの形成された第4図bに示す形状
の多結晶シリコンの島を形成する。その後、たと
えば、連続発振アルゴンレーザ52を2〜
18watt/cm2のパワー、1mm/sec〜10cm/secの
速さで走査して、多結晶シリコンの島42を再結
晶化させ、第4図に示したごとき単結晶シリコン
の島32を形成する。
FIG. 5 illustrates the manufacturing process of this embodiment using cross-sectional views. As shown in FIG. 5a, for example, a silicon substrate 30 is oxidized in a water vapor atmosphere to form SiO 2 31 with a thickness of 1.0 μm, and then polycrystalline silicon 4 is deposited at 600° C. by, for example, reduced pressure vapor phase epitaxy.
2 to grow 0.5 μm. Next, as shown in b in the same figure,
A protective oxide film 50 and a silicon nitride film 51 are sequentially grown, and selectively formed in FIG. 4b by ordinary photolithography.
The protective oxide film 50 and silicon nitride film 51 having the same pattern as the island 32 shown in FIG. Further, as shown in c of the same figure, polycrystalline silicon 42 other than the lower part of silicon nitride film 51 is completely oxidized by oxidation in a water vapor atmosphere to form a selective oxide film 31 '. ,
A polycrystalline silicon island having the shape shown in FIG. 4b is formed, which is completely insulated by 31' and has a fine pattern 32A formed thereon. After that, for example, the continuous wave argon laser 52 is
The polycrystalline silicon islands 42 are recrystallized by scanning at a power of 18 watt/cm 2 and a speed of 1 mm/sec to 10 cm/sec to form monocrystalline silicon islands 32 as shown in FIG. .

第5図のdは、レーザ照射によるシリコン島の
再結晶化の工程を平面図により示す。多結晶シリ
コン島42の微細パターン部分32Aからレーザ
ビーム53を矢印531の方向に走査する。
FIG. 5d shows a plan view of the process of recrystallizing a silicon island by laser irradiation. A laser beam 53 is scanned in the direction of an arrow 531 from the fine pattern portion 32A of the polycrystalline silicon island 42.

以上の実施例によれば、レーザ照射による多結
晶シリコン島の再結晶化に際し、シリコン島端部
の微細パターン部分32Aにおいて、パターンが
微細なため多数の結晶粒界が入り難くなり、シリ
コンの固化の際パターン形状に合つた結晶成長の
核発生が生じ易くなる。微細パターン32Aのな
い他のSiとSiO2との界面では核発生が生じ難い
ために微細パターン部分32Aで発生した結晶核
が多結晶シリコン島42全体を溶融して再結晶す
るときの種となる。したがつて多結晶シリコン島
42の形成において島のエネルギーム走査の開始
される一辺に平面形状が微細な凹凸パターンを形
成することにより、結晶成長の核形成を制御性良
く行うことができ、工程が簡単でしかも完全絶縁
分離した良質な単結晶シリコン島32を形成する
ことができる。
According to the above embodiment, when recrystallizing a polycrystalline silicon island by laser irradiation, in the fine pattern portion 32A at the end of the silicon island, it is difficult for many grain boundaries to enter because the pattern is fine, and the solidification of silicon is prevented. In this case, the generation of nuclei for crystal growth that matches the pattern shape is likely to occur. Since nucleation is difficult to occur at the interface between Si and SiO 2 where there is no fine pattern 32A, the crystal nuclei generated at the fine pattern portion 32A serve as seeds when the entire polycrystalline silicon island 42 is melted and recrystallized. . Therefore, in forming the polycrystalline silicon island 42, by forming a concavo-convex pattern with a fine planar shape on one side where the energetic scanning of the island is started, the formation of nuclei for crystal growth can be performed with good controllability, and the process It is possible to easily form a high-quality single crystal silicon island 32 that is completely insulated and isolated.

なお、レーザビームを多結晶シリコン島42に
対して、微細パターン部32Aの方向から矢印5
31のごとく走査するとき、ビームのスポツト径
が島の巾に対して小さくても、ビーム径内に1.5
ケ以上の凹凸パターンを含めば即ち第5図のdの
破線で示すビームスポツト54の大きさであれば
ビーム間の重なりを考えても、必らず一つのビー
ムが走査するライン中に前記凹凸パターンを一ケ
含むことになり、核形成がいずれの走査でも生じ
得る。したがつていかに大きな巾の島であつて
も、島全体を大結晶粒化しやすく、前述した従来
例のような欠点がない。
Note that the laser beam is directed toward the polycrystalline silicon island 42 from the direction of the fine pattern portion 32A in the direction of arrow 5.
When scanning as shown in Figure 31, even if the beam spot diameter is small relative to the width of the island, there will be 1.5% within the beam diameter.
If a pattern of more than 100 concavities and convexities is included, that is, if the size of the beam spot 54 is as shown by the broken line in d in FIG. One pattern will be included, and nucleation can occur in either scan. Therefore, no matter how wide the island is, the entire island can easily be made into large crystal grains, and does not have the drawbacks of the conventional example described above.

次に、本発明の第2の実施例を図面に基き説明
する。第6図は、第2の実施例の平面からみた場
合の概念図である。第6図のaは、多結晶シリコ
ン島42の大きさがビームスポツト53の大きさ
に対して走査方向に十分大きいときのたとえば連
続発振レーザビームの照射方法を示す。42は、
絶縁分離されている多結晶シリコン島であり図面
の向つて左側に微細パターンとして、たとえば、
巾0.1〜10μm、長さたとえば数μm程度の矩形の
くり返しパターン32Aが形成されており、レー
ザビームスポツト53の走査方向は、図面の向つ
て左から右の方向になつている。第6図のbは、
多結晶シリコン島42がレーザビームのスポツト
径よりビームの走査方向に対し巾及び長さともに
大きい場合の照射の途中における状態を示してい
る。即ち微細パターン32Aがきざまれているシ
リコン島の端部を入口側としてレーザビームが走
査されており、1回目の走査651の後、たとえ
ばレーザビームのスポツト53の径が重なる巾で
2回目の走査652を行つている途中の再結晶化
の状態の概念図であり、42はレーザビームの未
照射の多結晶シリコンであり、651Aは1回目
の走査651で、端部の微細パターン32Aによ
り制御された単結晶が成長している領域であり、
651Bはレーザビームの多結晶シリコン側での
端であり、前記多結晶シリコンを種として多数の
小さな単結晶群がレーザビームの走査の端に沿つ
て形成されている。652Aは、2回目のレーザ
ビームの走査によつて単結晶化した部分であり、
この場合、1回目の走査に対してスポツト径を適
当にオーバーラツプさせるように2回目の走査位
置を選ぶことにより、1回目の走査のとき形成さ
れた前記小さな単結晶群651Bは再融解して1
回目と2回目のレーザビーム走査の境界では完全
に連続した単結晶シリコンが得られる。
Next, a second embodiment of the present invention will be described based on the drawings. FIG. 6 is a conceptual diagram of the second embodiment when viewed from a plane. FIG. 6a shows an irradiation method using, for example, a continuous wave laser beam when the size of the polycrystalline silicon island 42 is sufficiently larger than the size of the beam spot 53 in the scanning direction. 42 is
It is a polycrystalline silicon island that is insulated and isolated, and is shown as a fine pattern on the left side of the drawing, for example.
A rectangular repeating pattern 32A having a width of 0.1 to 10 .mu.m and a length of, for example, several .mu.m is formed, and the scanning direction of the laser beam spot 53 is from left to right in the drawing. b in Figure 6 is
This figure shows a state in the middle of irradiation when the polycrystalline silicon island 42 is larger in width and length in the beam scanning direction than the spot diameter of the laser beam. That is, the laser beam is scanned with the end of the silicon island where the fine pattern 32A is cut out as the entrance side, and after the first scan 651, a second scan is performed at a width where the diameters of the laser beam spots 53 overlap, for example. 652 is a conceptual diagram of the state of recrystallization during the process, 42 is polycrystalline silicon that has not been irradiated with the laser beam, and 651A is the first scan 651, which is controlled by the fine pattern 32A at the end. This is the area where single crystals are growing.
651B is the end of the laser beam on the polycrystalline silicon side, and a large number of small single crystal groups are formed along the scanning end of the laser beam using the polycrystalline silicon as a seed. 652A is a portion made into a single crystal by the second laser beam scan,
In this case, by selecting the second scanning position so that the spot diameters appropriately overlap with those of the first scanning, the small single crystal group 651B formed during the first scanning is remelted to form a single crystal.
Completely continuous single crystal silicon is obtained at the boundary between the first and second laser beam scans.

以上のように本実施例によれば、連続発振のエ
ネルギービームをシリコン島の微細パターンの形
成されている方から走査することにより、はじめ
に端部の微細パターン形成領域で制御された結晶
核に従つて、ビームの走査とともに単結晶シリコ
ンが育成されることができる。また上記微細パタ
ーンとして周期性のある矩形やノコギリ歯状のパ
ターンを用いることにより巾の広い島の場合でも
数回の走査のオーバーラツプによつても全く同じ
結晶核が形成でき、更に単結晶育成の制御性がよ
くなる。
As described above, according to this embodiment, by scanning the continuous wave energy beam from the side of the silicon island where the fine pattern is formed, it first follows the crystal nuclei controlled in the fine pattern forming area at the end. Thus, single crystal silicon can be grown as the beam scans. In addition, by using a periodic rectangular or sawtooth pattern as the above-mentioned fine pattern, exactly the same crystal nucleus can be formed even in the case of a wide island even by overlapping several scans, which further improves single crystal growth. Improves controllability.

なお、第1の実施例において、エネルギービー
ムとして連続発振レーザビームを用いているが、
連続波電子ビーム、パルスレーザ、パルス電子ビ
ーム、あるいは高エネルギー密度のヒータを走査
してもよいことは言うまでもない。また、エネル
ギービーム照射前の非単結晶半導体層としては多
結晶の他非晶質半導体層を用いてよいことも言う
までもない。
Note that in the first embodiment, a continuous wave laser beam is used as the energy beam, but
It goes without saying that continuous wave electron beams, pulsed lasers, pulsed electron beams, or high energy density heaters may be used for scanning. Furthermore, it goes without saying that an amorphous semiconductor layer other than polycrystalline may be used as the non-single crystal semiconductor layer before energy beam irradiation.

更に、半導体の島を絶縁分離する方法は、選択
酸化の他にたとえば第7図に示す工程図で説明す
る絶縁分離法が用いることもできる。第7図のa
において30はシリコン基板、71は気相成長法
で形成したSiO2、42は気相成長で成長せしめ
た非単結晶シリコンである。第7図のbは、写真
蝕刻法により選択的に非単結晶シリコン42を残
した状態であり、第7図のcに示すように、この
後気相成長法によりSiO271′を形成し、さらに
第7図のdに示すごとく再び写真蝕刻法を用いて
選択的に上記SiO271′を除去し、非単結晶シリ
コンの島42を形成することができる。勿論、こ
のときシリコン島42の端部の一部には、微細な
凹凸を含むパターンが繰り返し形成されているこ
とは言うまでもない。この方法を用いれば、シリ
コンの熱酸化によりSiO2を形成場合に比べて、
全て600℃程度以下の低温工程で処理することが
可能になり、特に3次元素子の実現にとつては有
効である。
Furthermore, as a method for insulating and isolating the semiconductor islands, in addition to selective oxidation, for example, an insulating isolation method explained using the process diagram shown in FIG. 7 can be used. Figure 7a
30 is a silicon substrate, 71 is SiO 2 formed by vapor phase growth, and 42 is non-single crystal silicon grown by vapor phase growth. FIG. 7b shows a state in which non-single crystal silicon 42 is selectively left by photolithography, and as shown in FIG. 7c, SiO 2 71' is then formed by vapor phase growth. Further, as shown in FIG. 7D, the SiO 2 71' is selectively removed again using photolithography to form islands 42 of non-single crystal silicon. Needless to say, at this time, a pattern including fine irregularities is repeatedly formed on a part of the end portion of the silicon island 42. Using this method, compared to forming SiO 2 by thermal oxidation of silicon,
All processes can be performed at low temperatures of about 600°C or less, which is particularly effective for creating tertiary elements.

発明の効果 以上のように本発明は、絶縁基板上に、エネル
ギービームの走査の開始される一辺に平面形状に
おいて矩形のあるいはノコギリ歯状等の微細な凹
凸を有する半導体島状パターンを設けることによ
り、エネルギービームを微細な凹凸パターン部分
を始点として走査しながら照射し、半導体の島を
再結晶化する際に制御性よく単結晶化せしめるこ
とができる。かくして形成した絶縁分離された良
質な単結晶体の島に素子をつくり込むことによ
り、高性能素子の実現が可能となるとともに、3
次元素子の実現に大きく寄与するものである。
Effects of the Invention As described above, the present invention provides, on an insulating substrate, a semiconductor island pattern having fine irregularities such as a rectangular or sawtooth shape in plan view on one side where scanning of an energy beam starts. By irradiating the energy beam while scanning the fine uneven pattern portion as a starting point, when recrystallizing the semiconductor island, it is possible to form a single crystal with good controllability. By building elements into the isolated high-quality single-crystal islands thus formed, high-performance elements can be realized, and three
This will greatly contribute to the realization of next-dimensional elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はグラフオーエピタキシアル法の断面
図、第2図はラテラルエピタキシアル法の断面
図、第3図a,bは形状効果を示す報告例のパタ
ーン平面図、断面図、第4図aは本発明の第1の
実施例の単結晶島の断面図、第4図bは本発明の
第1の実施例の単結晶島パターンの平面形状図、
第5図a,b,cは本発明の半導体島形成の工程
断面図、第5図dはレーザスポツトとパターンの
位置関係を示す平面図、第6図a,bは本発明の
第2の実施例のレーザビームの照射法の概念図、
第7図a〜dは半導体の島形成法の他の実施例の
工程断面図である。 30……シリコン基板、31,31′,50…
…シリコン熱酸化膜、42……非単結晶シリコン
層、32,651A,652A……再結晶化した
単結晶、32A……島端部の微細パターン部分、
51……シリコン窒化膜、52……レーザビー
ム、53……レーザビームスポツト、531,5
32,533,534,651,652……レー
ザビームの走査方向、71,71′……気相成長
により形成したSiO2
Figure 1 is a cross-sectional view of the graph-o-epitaxial method, Figure 2 is a cross-sectional view of the lateral epitaxial method, Figures 3 a and b are pattern plan views and cross-sectional views of reported examples showing shape effects, and Figure 4 a is a sectional view of the single crystal island of the first embodiment of the present invention, FIG. 4b is a plan view of the single crystal island pattern of the first embodiment of the present invention,
FIGS. 5a, b, and c are cross-sectional views of the process of forming a semiconductor island according to the present invention, FIG. 5d is a plan view showing the positional relationship between the laser spot and the pattern, and FIGS. Conceptual diagram of the laser beam irradiation method of the example,
FIGS. 7a to 7d are process cross-sectional views of another embodiment of the semiconductor island forming method. 30...Silicon substrate, 31, 31', 50...
...Silicon thermal oxide film, 42...Non-single crystal silicon layer, 32, 651A, 652A...Recrystallized single crystal, 32A...Fine pattern part of island end,
51...Silicon nitride film, 52...Laser beam, 53...Laser beam spot, 531,5
32, 533, 534, 651, 652... Laser beam scanning direction, 71, 71'... SiO 2 formed by vapor phase growth.

Claims (1)

【特許請求の範囲】[Claims] 1 非晶質絶縁基板上に半導体膜を形成する工程
と、前記半導体膜を、エネルギービーム走査の開
始側の辺全体が平面形状において微細な凹凸を有
する島状パターンに形成する工程と、前記半導体
の島状パターンの微細な凹凸を有する辺を始点と
して、前記半導体の島状パターンに、前記エネル
ギービームを走査しながら照射して、前記半導体
の島状パターンを再結晶化する工程とを備えてな
ることを特徴とする半導体装置の製造方法。
1. A step of forming a semiconductor film on an amorphous insulating substrate, a step of forming the semiconductor film into an island-like pattern in which the entire side on the start side of energy beam scanning has minute irregularities in a planar shape, and Recrystallizing the semiconductor island pattern by irradiating the semiconductor island pattern with the energy beam while scanning the semiconductor island pattern starting from a side having fine irregularities of the semiconductor island pattern. A method for manufacturing a semiconductor device, characterized in that:
JP57155862A 1982-09-09 1982-09-09 Semiconductor device and its manufacture Granted JPS5946021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57155862A JPS5946021A (en) 1982-09-09 1982-09-09 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57155862A JPS5946021A (en) 1982-09-09 1982-09-09 Semiconductor device and its manufacture

Publications (2)

Publication Number Publication Date
JPS5946021A JPS5946021A (en) 1984-03-15
JPS6320011B2 true JPS6320011B2 (en) 1988-04-26

Family

ID=15615128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57155862A Granted JPS5946021A (en) 1982-09-09 1982-09-09 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS5946021A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2978117B2 (en) * 1996-07-01 1999-11-15 ティーディーケイ株式会社 Surface mount components using pot type core
JP3992976B2 (en) 2001-12-21 2007-10-17 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP4519400B2 (en) * 2001-12-27 2010-08-04 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS5946021A (en) 1984-03-15

Similar Documents

Publication Publication Date Title
US5371381A (en) Process for producing single crystal semiconductor layer and semiconductor device produced by said process
JPH0157078B2 (en)
JPH0132648B2 (en)
JPS6320011B2 (en)
JPH0351289B2 (en)
JPS6147627A (en) Manufacture of semiconductor device
JPS58139423A (en) Lateral epitaxial growing method
JPH0136972B2 (en)
JPS58190899A (en) Formation of single crystal silicon film
JPS58180019A (en) Semiconductor base body and its manufacture
JPH0442358B2 (en)
JPH0652712B2 (en) Semiconductor device
JPH0732121B2 (en) Method for manufacturing semiconductor device
JPS6362088B2 (en)
JP2793241B2 (en) SOI formation method
JPS5892209A (en) Manufacture of semiconductor device
JPS60161396A (en) Manufacture of silicon thin film
JPH0368532B2 (en)
JPS60191090A (en) Manufacture of semiconductor device
JPS5893218A (en) Manufacture of semiconductor thin film structure
JPS61106484A (en) Substrate for semiconductor device and its preparation
JPH0334847B2 (en)
JPH0461491B2 (en)
JPS62130509A (en) Manufacture of semiconductor substrate
JPH0775223B2 (en) Method for manufacturing semiconductor single crystal layer