JP4519400B2 - Method for manufacturing semiconductor device - Google Patents

Description

【００３６】
以上の構成により、スーパーラテラル成長による大結晶粒を連続的に形成させることができ、かつ、レーザー結晶化工程における基板処理効率を高めることができ、かつ、ＴＦＴの配置に合わせた結晶粒の位置制御をより確かなものとすることができ、かつ、従来のＳＬＳ法のように基板表面におけるレーザー光の強度の形状をスリット状に加工するためのマスクを光学系に組み込む必要のない簡便なレーザー照射方法を用いた半導体装置の作製方法を提供することができる。
【００３７】
尚、本発明において半導体装置とは、半導体特性を利用することで機能しうる装置全般（例えば、液晶表示パネルに代表される電子装置、およびその電子装置を部品として搭載した電気器具）を含んでいる。
【００３８】
【発明の実施の形態】
以下、本発明の実施の態様について図面を参照して詳細に説明する。
【００３９】
図１に本発明のレーザー照射方法のブロック図を示す。図１において、被処理物１０７に対するパルスレーザー光の照射位置を制御する第１の手段として、２つの方法示している。一つの方法は、ステージコントローラ１０１によってステージ１０８を駆動することで、ステージ上に設置している被処理物１０７（基板）の位置を変える方法である。もう一方は、基板位置を固定した状態で光学系１０３を用いてレーザー光スポットの照射位置を移動させる方法である。本発明では、上記２つのいずれの方法であってもよく、また、上記２つの方法を組み合わせる方法であってもよい。
【００４０】
上記２つの方法は、いずれもレーザー光スポット位置の基板に対する相対位置を変化させることを意味し、これを便宜上「（レーザー光スポットを）走査する」として示す。
【００４１】
また、レーザー照射装置１００は、パルスレーザー光を発振する第２の手段に相当するパルスレーザー発振装置１０２を有している。パルスレーザー発振装置１０２は、処理の目的によって適宜変えることが可能である。本発明では、公知のレーザーを用いることができる。レーザーは、パルス発振の気体レーザー発振装置もしくは固体レーザー発振装置を用いることができるが、本実施形態ではパルス発振の固体レーザー発振装置を用いた場合について説明する。
【００４２】
パルス発振固体レーザー発振装置として、Ｃｒ、Ｎｄ、Ｅｒ、Ｈｏ、Ｃｅ、Ｃｏ、Ｔｉ又はＴｍがドーピングされたＹＡＧレーザー、ＹＶＯ₄レーザー、ＹＬＦレーザー、ＹＡｌＯ₃レーザー、ガラスレーザー、ルビーレーザー、アレキサンドライドレーザー、Ｔｉ：サファイアレーザー、フォルステライトレーザー（Ｍｇ₂ＳｉＯ₄）。当該レーザーの基本波はドーピングする材料によって異なるが、１μm前後の基本波を有するレーザー光が得られる。基本波に対する第2高調波、第３高調波および第４高調波は、非線形光学素子を用いることで得ることができる。
【００４３】
また、レーザー照射装置１００は、レーザー発振装置１０２から発振されるレーザー光の被処理物におけるビームスポットを加工することができる、第３の手段に相当する光学系１０３を有している。レーザー発振装置１０２から射出されたレーザー光の形状は、ロッド形状が円筒形であれば円状となり、スラブ型であれば矩形状となる。このようなレーザー光を光学系により、さらに成形することにより、レーザー光の被処理物１０７の表面におけるビームスポットを所望の形状にすることができる。好適には、レーザー光の被処理物における断面形状を線形状または矩形状に成形し、その短尺方向のエネルギー分布がガウシアン形状またはフラットトップ形状にする。また、短尺方向の長さを５０μｍ以下とすることが好ましい。
【００４４】
さらに、レーザー照射装置１００は、第４の手段に相当するコンピューター１０４を有している。コンピューター１０４はレーザー発振装置１０２の発振を制御し、かつ、レーザー光のビームスポットがマスクパターンのデータに従って定められる位置を覆うように、第１の手段に相当するステージコントローラ１０１を制御することができる。
【００４５】
なお、このレーザー照射方法は、上記４つの手段の他に、被処理物の温度を調節する手段を備えていても良い。
【００４６】
図２（Ａ）は、レーザー光パルス毎に、基板とレーザー光スポットの相対位置をずらして（走査して）いく様子を示す。４００ａ、４００ｂ、４００ｃは基板上におけるビームスポットの拡大図である。４０３は島状半導体層Ａであり、その輪郭の少なくとも一部が、山形の形状が複数個連なっている形状、または、鋸刃形状をしていることが必要である。加えて、図２（Ａ）における角度θは３０°以上かつ１１０°以下にする。
【００４７】
図２（Ａ）の４００ａは、あるパルス照射時のレーザー光ビームスポット位置であり、４００ｂは次のパルス照射時のレーザー光ビームスポット位置であり、４００ｃはさらに次のパルス照射時のレーザー光ビームスポット位置を示す。本図に示すように、島状半導体層４０３において、山形の形状の山頂領域または鋸刃形状の刃先領域から、レーザー光照射され、図中のレーザー光スポット相対移動方向を示す矢印に向けて、レーザー光ビームスポット位置がパルス毎に移動していく。
【００４８】
また、４０１ａおよび４０１ｂはレーザー光の１パルス毎の基板ステージ移動距離（送りピッチ）を示している。この送りピッチは０．３μm以上かつ５μm以下、より好ましくは０．７μm以上３μm以下であることが必要である。
【００４９】
なお、結晶化後の半導体膜をＴＦＴの活性層として用いる場合、その走査方向がチャネル形成領域のキャリアが移動する方向と並行になるように定めるのが望ましい。
【００５０】
これについて、図４で示す。図４（Ａ）の４３０は、レーザー照射前に島状半導体層Ａとして形成している。図４（Ｂ）は図４（Ａ）の４３０を島状半導体層Ｂに形成した形状である。４３８〜４３３はチャネル領域であり、シングルゲートＴＦＴのチャネルを６つに分割した形状である。これらチャネル形成領域を挟んで不純物領域４３１、４３２が設けられている
本発明のレーザー発振装置を用いて半導体膜を結晶化させるとき、レーザー光の走査方向が矢印に示すように、チャネル形成領域のキャリアの移動する方向（チャネル長方向）と並行になるように、走査方向を定めるようにする。５２３はレーザー光のビームスポットを示しており、矢印の方向に走査する。
【００５１】
また、図４（Ｃ）の４４０は、レーザー照射前に島状半導体層Ａとして形成している。図４（Ｄ）は図４（Ｃ）の４４０を島状半導体層Ｂに形成した形状である。図４（Ｄ）では、チャネル形成領域が、ソース・ドレイン間に、直列に３つ設けられているトリプルゲートＴＦＴにする一例を示している。チャネル形成領域４４５を挟むように不純物領域４４１、４４３が設けられている。また、チャネル形成領域４４６を挟むように不純物領域４４３、４４４が設けられており、さらにチャネル形成領域４４７を挟むように不純物領域４４４、４４７が設けられている。そして、本発明のレーザー発振装置を用いて半導体膜を結晶化させるとき、レーザー光は図中に示す、矢印の方向に走査する。
【００５２】
ただし、アクティブマトリックスディスプレイに使われるＴＦＴは、画素部、信号線駆動回路部、走査線駆動回路部において、活性層チャネル形成領域のキャリアが移動する方向が異なることが、回路レイアウトの都合上よくある。このような場合にも、本発明は有効であることを図３を用いて説明する。
【００５３】
図３では、例えば、走査線駆動回路領域５１２とその他の領域とで、レーザー光の走査方向を変更させている場合について示す。まず、基板上に形成されているマーカーを位置基準として、図３（Ａ）に示すように、信号線駆動回路となる領域５１１と画素部となる領域５１０をレーザー照射する。
【００５４】
次に、図３（Ｂ）に示すように、基板ステージを９０°回転させて、基板上に形成されているマーカーを再度読み取り、この位置情報から、走査線駆動回路となる領域５１２をレーザー照射する。このようにすることで基板内のレーザー光スポットの相対的な移動方向を変化させて照射することが可能である。
【００５５】
また、レーザー照射処理中であっても、一時的にレーザー光を基板面に照射したくない場合もありえる。このような場合には、レーザー光を一時的に完全に遮蔽することができるＡＯ（音響光学）光変調素子を被処理物である基板とレーザー発振装置との間の光学系に設ければよい。
【００５６】
なお、レーザー光の照射位置を定めるためには、半導体膜に対するマスクの位置を定めるためのマーカーを、半導体膜に形成する必要がある。図６に、アクティブマトリクス型の半導体装置を作製するために成膜された半導体膜において、マーカーを形成する位置を示す。なお、図６（Ａ）は１つの基板から１つの半導体装置を作製する例を示しており、図６（Ｂ）は１つの基板から４つの半導体装置を作製する例を示している。
【００５７】
図６（Ａ）において５４０は基板上に成膜された半導体膜であり、破線５４１が画素部、破線５４２が信号線駆動回路、破線５４３が走査線駆動回路の形成される部分に相当する。５４４はマーカーが形成される部分（マーカー形成部）であり、半導体膜の４隅に位置するように設けられている。
【００５８】
なお図６（Ａ）ではマーカー形成部５４４を４つそれぞれ４隅に設けたが、本発明はこの構成に限定されない。半導体膜におけるレーザー光の走査部分と、半導体膜のパターニングのマスクとの位置合わせをすることができるのであれば、マーカー形成部の位置及びその数は上述した形態に限定されない。
【００５９】
図６（Ｂ）において５５０は基板上に成膜された半導体膜であり、破線５５１は後の工程において基板を分断するときのスクライブラインである。図６（Ｂ）では、スクライブライン５５１の沿って基板を分断することで、４つの半導体装置を作製することができる。なお分断により得られる半導体装置の数はこれに限定されない。
【００６０】
５５２はマーカーが形成される部分（マーカー形成部）であり、半導体膜の４隅に位置するように設けられている。なお図６（Ｂ）ではマーカー形成部５５２を４つそれぞれ４隅に設けたが、本発明はこの構成に限定されない。半導体膜におけるレーザー光の走査部分と、半導体膜のパターニングのマスクとの位置合わせをすることができるのであれば、マーカー形成部の位置及びその数は上述した形態に限定されない。
【００６１】
なおマーカーは、従来のフォトリソグラフィー技術によって、島状半導体膜Ａをパターニング形成する工程で同時に形成すればよい。
【００６２】
上記構成により、半導体膜を結晶化させた後、島状半導体膜Ｂ形成により除去される半導体膜領域にレーザー光を照射する時間を省くことができるので、レーザー光照射にかかる時間を短縮化することができ、なおかつ基板の処理速度を向上させることができ、さらに、ＴＦＴの配置に合わせた結晶粒の位置制御をより確かなものとすることができる。
【００６３】
【実施例】
（実施例１）
本実施例ではアクティブマトリクス基板の作製方法について図７〜図１０および図５を用いて説明する。ここではＣＭＯＳ回路、及び駆動回路と、画素ＴＦＴ、保持容量とを有する画素部を同一基板上に形成された基板を、便宜上アクティブマトリクス基板と呼ぶ。また、図７〜図１０と図５（Ｂ）、（Ｄ）、（Ｆ）、（Ｈ）はともに、ＴＦＴ作製工程の断面図であるが、図７〜図１０はＴＦＴをソース・ドレイン間を結ぶ直線を含む面で分断した場合の断面図（チャネル長方向の断面図）であり、図５（Ｂ）、（Ｄ）、（Ｆ）、（Ｈ）はＴＦＴをチャネル幅方向の断面図に相当する。
【００６４】
まず、本実施例ではバリウムホウケイ酸ガラス、またはアルミノホウケイ酸ガラスなどのガラスからなる基板６００を用いる。なお、基板６００としては、石英基板やシリコン基板、金属基板またはステンレス基板の表面に絶縁膜を形成したものを用いても良い。また、本実施例の処理温度に耐えうる耐熱性が有するプラスチック基板を用いてもよい。
【００６５】
次いで、基板６００上に酸化珪素膜、窒化珪素膜または酸化窒化珪素膜などの絶縁膜から成る下地膜６０１を公知の手段（スパッタ法、ＬＰＣＶＤ法、プラズマＣＶＤ法等）により形成する。本実施例では下地膜６０１として下地膜６０１ａ、６０１ｂの２層の下地膜を用いるが、前記絶縁膜の単層膜または２層以上積層させた構造を用いても良い（図７（Ａ））。
【００６６】
次いで、下地膜６０１上に、公知の手段（スパッタ法、ＬＰＣＶＤ法、プラズマＣＶＤ法等）により２５〜１５０nm（好ましくは３０〜１２０nm）の厚さで非晶質半導体膜６９２を形成する（図７（Ａ））。なお、本実施例では非晶質半導体膜を成膜しているが、微結晶半導体膜、結晶性半導体膜であっても良い。また、非晶質珪素ゲルマニウム膜などの非晶質構造を有する化合物半導体膜を用いても良い。
【００６７】
次に、非晶質半導体膜６９２をパターニングし、フッ化ハロゲン、例えば、ＣｌＦ、ＣｌＦ₃、ＢｒＦ、ＢｒＦ₃、ＩＦ、ＩＦ₃等を含む雰囲気で異方性ドライエッチング法によりエッチングすることで、図７（Ｂ）に示すように、島状半導体膜Ａとなる６９３ａ、６９３ｂ、６９３ｃ、６９３ｄ、６９３ｅを形成する。図５（Ａ）は、６９３ａの上面図であり、Ａ−Ａ‘における断面図が図５（Ｂ）に相当する。
【００６８】
次に、島状半導体膜Ａの６９３ａ、６９３ｂ、６９３ｃをレーザー結晶化法により結晶化させる。レーザー結晶化法は、本発明のレーザー照射方法を用いて行なう。具体的には、レーザー照射装置のコンピューターに入力されたマスクの情報に従って、島状半導体膜Ａの６９３ａ、６９３ｂ、６９３ｃに選択的にレーザー光を照射する。もちろん、レーザー結晶化法だけでなく、他の公知の結晶化法（ＲＴＡやファーネスアニール炉を用いた熱結晶化法、結晶化を助長する金属元素を用いた熱結晶化法等）と組み合わせて行ってもよい。
【００６９】
本発明のレーザー照射方法では、パルス発振の気体レーザー発振装置もしくは固体レーザー発振装置を用いることができる。本実施例ではパルス発振のＮｄ：ＹＬＦレーザーを用いた場合について説明する。
【００７０】
図１１はレーザー結晶化処理装置を示したものである。図１１では、Ｎｄ：ＹＬＦレーザー発振装置１０１を用いて出力１．５W、繰り返し周波数１kHzの条件で使用する場合を例にする。レーザー光源１０１は共振器の中にＹＬＦ結晶と非線形光学素子を入れて、波長５２７nmの第２高調波を射出する方式であるとするが、無論、非線形光学素子が共振器の外側にある場合でもよい。さらに、このレーザー光源１０１は、ロッド形状が円筒形であり、レーザー光源１０１から射出直後のビームスポット形状は円状であるとするが、仮にロッド形状がスラブ型であり、射出直後のビームスポット形状は矩形状であっても、以下に示すように、光学系により、ビームスポットを所望の形状に成形できる。
【００７１】
このＮｄ：ＹＬＦレーザーはビームの拡がり角が３ミリラジアンであり、ビームサイズは射出口で直径２mm程度であるが、射出口から２０cm 離れた位置では直径１cm程度に広がってしまう。この位置に焦点距離ｆ＝６００mmの凸レンズ１０２を一枚入れると、ビームサイズは直径約１０mmの平行光になる。図１１の光学ミラー１０３〜１０５で反射されたレーザー光は、図１１のY方向に曲率を有する凸シリンドリカルレンズ１０６によりレーザー光を集光する。ここでＹ方向は、半導体膜面上におけるレーザー光のビームスポットの移動方向であり、ビームスポットの短尺方向となる。また、図１１のＸ方向は半導体膜面上におけるレーザー光のビームスポットの長尺方向になり、半導体膜面上におけるレーザー光のビームスポットの移動方向と直角をなす方向である。（光学ミラー１０３〜１０５は装置のレイアウト上、入れているものであり、本質的に必要とするわけではない。）以上の構成で、照射面となる半導体膜面上におけるビームスポットは１０mm×１０μmの線形状ビームになる。
【００７２】
ただし、照射面にて、線形状または矩形状のレーザー光に成形する方法はこの限りではない。図示しないが、光学ミラー１０３と凸シリンドリカルレンズ１０６の間に凹シリンドリカルレンズをいれて、ビームスポットの長尺方向を長くすることが可能である。また、その凹シリンドリカルレンズとレーザー光源１０１との間に、レーザー光を平行光とするためのビームコリメーターや、レーザー光を広げるためのビームエキスパンダーを入れることも可能である。また、ここでは出力１．５Wのレーザー光源でビームスポットは１０mm×１０μmの線形状ビームにする方法を示したが、さらに高出力のレーザー光源の場合には、短尺方向のビームスポットサイズは変えずに、長尺方向のサイズのみ長くすることが望ましい。（現在、出力２０Wで使用可能なＬＤ励起Ｎｄ：ＹＬＦレーザー発振装置が市販されている。）
【００７３】
半導体膜面上におけるレーザー光のビームスポットの相対位置を動かすために、基板ステージ１０１をＹ方向（ビームスポットの短尺方向）にスイープ駆動する。レーザーパルスの繰り返し周波数１kHzで、基板ステージのスィープ速度を３．０mm/秒とすると、レーザーパルスを１回照射するごとに、基板とビームスポットの相対位置はY方向に３μmずれて（送りピッチが３μm）いる。
【００７４】
上述したレーザー結晶化によって、図７（Ｃ）に示すように、結晶性が高められた島状半導体膜Ａの６９４ａ、６９４ｂ、６９４ｃ、６９４ｄ、６９４ｅが形成される。図５（Ｃ）は、６９４ａの上面図であり、Ａ−Ａ‘における断面図が図５（Ｄ）に相当する。
【００７５】
次に、島状半導体膜Ａの６９４ａ、６９４ｂ、６９４ｃ、６９４ｄ、６９４ｅを所望の形状にパターニングして、図７（Ｄ）に示すように、島状半導体膜Ｂの６０２〜６０６を形成する。図５（Ｅ）は、６０２の上面図であり、Ａ−Ａ‘における断面図が図５（Ｆ）に相当する。
【００７６】
島状半導体膜Ｂの６０２〜６０６を形成した後、ＴＦＴのしきい値を制御するために微量な不純物元素（ボロンまたはリン）のドーピングを行ってもよい。また、このしきい値制御のための不純物ドーピングは、レーザー結晶化前におこなってもよいし、ゲート絶縁膜成膜後におこなうことも可能である。
【００７７】
次いで、島状の半導体膜６０２〜６０６を覆うゲート絶縁膜６０７を形成する。ゲート絶縁膜６０７はプラズマＣＶＤ法またはスパッタ法を用い、厚さを４０〜１５０nmとして珪素を含む絶縁膜で形成する。本実施例では、プラズマＣＶＤ法により１１０nmの厚さで酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）で形成した。勿論、ゲート絶縁膜は酸化窒化珪素膜に限定されるものでなく、他の珪素を含む絶縁膜を単層または積層構造として用いても良い。
【００７８】
次いで、ゲート絶縁膜６０７上に膜厚２０〜１００nmの第１の導電膜６０８と、膜厚１００〜４００nmの第２の導電膜６０９とを積層形成する。本実施例では、膜厚３０nmのＴａＮ膜からなる第１の導電膜６０８と、膜厚３７０nmのＷ膜からなる第２の導電膜６０９を積層形成した。ＴａＮ膜はスパッタ法で形成し、Ｔａのターゲットを用い、窒素を含む雰囲気内でスパッタする。また、Ｗ膜は、Ｗのターゲットを用いたスパッタ法で形成した。その他に６フッ化タングステン（ＷＦ₆）を用いる熱ＣＶＤ法で形成することもできる。いずれにしてもゲート電極として使用するためには低抵抗化を図る必要があり、Ｗ膜の抵抗率は２０μΩcm以下にすることが望ましい。
【００７９】
なお、本実施例では、第１の導電膜６０８をＴａＮ、第２の導電膜６０９をＷとしたが、特に限定されず、いずれもＴａ、Ｗ、Ｔｉ、Ｍｏ、Ａｌ、Ｃｕ、Ｃｒ、Ｎｄから選ばれた元素、または前記元素を主成分とする合金材料若しくは化合物材料で形成してもよい。また、リン等の不純物元素をドーピングした多結晶珪素膜に代表される半導体膜を用いてもよい。また、ＡｇＰｄＣｕ合金を用いてもよい。また、第１の導電膜をタンタル（Ｔａ）膜で形成し、第２の導電膜をＷ膜とする組み合わせ、第１の導電膜を窒化チタン（ＴｉＮ）膜で形成し、第２の導電膜をＷ膜とする組み合わせ、第１の導電膜を窒化タンタル（ＴａＮ）で形成し、第２の導電膜をＷとする組み合わせ、第１の導電膜を窒化タンタル（ＴａＮ）膜で形成し、第２の導電膜をＡｌ膜とする組み合わせ、第１の導電膜を窒化タンタル（ＴａＮ）膜で形成し、第２の導電膜をＣｕ膜とする組み合わせとしてもよい。
【００８０】
また、２層構造に限定されず、例えば、タングステン膜、アルミニウムとシリコンの合金（Ａｌ−Ｓｉ）膜、窒化チタン膜を順次積層した３層構造としてもよい。また、３層構造とする場合、タングステンに代えて窒化タングステンを用いてもよいし、アルミニウムとシリコンの合金（Ａｌ−Ｓｉ）膜に代えてアルミニウムとチタンの合金膜（Ａｌ−Ｔｉ）を用いてもよいし、窒化チタン膜に代えてチタン膜を用いてもよい。
【００８１】
次に、フォトリソグラフィー法を用いてレジストからなるマスク６１０〜６１５を形成し、電極及び配線を形成するための第１のエッチング処理を行う。第１のエッチング処理では第１及び第２のエッチング条件で行う。（図８（Ｂ））本実施例では第１のエッチング条件として、ＩＣＰ（Inductively Coupled Plasma：誘導結合型プラズマ）エッチング法を用い、エッチング用ガスにＣＦ₄とＣｌ₂とＯ₂とを用い、それぞれのガス流量比を２５：２５：１０（ｓｃｃｍ）とし、１Paの圧力でコイル型の電極に５００WのＲＦ（13.56MHz）電力を投入してプラズマを生成してエッチングを行う。基板側（試料ステージ）にも１５０WのＲＦ（13.56MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。この第１のエッチング条件によりＷ膜をエッチングして第１の導電層の端部をテーパー形状とする。
【００８２】
この後、レジストからなるマスク６１０〜６１５を除去せずに第２のエッチング条件に変え、エッチング用ガスにＣＦ₄とＣｌ₂とを用い、それぞれのガス流量比を３０：３０(sccm)とし、１Paの圧力でコイル型の電極に５００WのＲＦ（13.56MHz）電力を投入してプラズマを生成して約３０秒程度のエッチングを行った。基板側（試料ステージ）にも２０WのＲＦ（13.56MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。ＣＦ₄とＣｌ₂を混合した第２のエッチング条件ではＷ膜及びＴａＮ膜とも同程度にエッチングされる。なお、ゲート絶縁膜上に残渣を残すことなくエッチングするためには、１０〜２０％程度の割合でエッチング時間を増加させると良い。
【００８３】
上記第１のエッチング処理では、レジストからなるマスクの形状を適したものとすることにより、基板側に印加するバイアス電圧の効果により第１の導電層及び第２の導電層の端部がテーパー形状となる。このテーパー部の角度は１５〜４５°となる。こうして、第１のエッチング処理により第１の導電層と第２の導電層から成る第１の形状の導電層６１７〜６２２（第１の導電層６１７ａ〜６２２ａと第２の導電層６１７ｂ〜６２２ｂ）を形成する。６１６はゲート絶縁膜であり、第１の形状の導電層６１７〜６２２で覆われない領域は２０〜５０nm程度エッチングされ薄くなった領域が形成される。
【００８４】
次いで、レジストからなるマスクを除去せずに第２のエッチング処理を行う。（図８（Ｃ））ここでは、エッチングガスにＣＦ₄とＣｌ₂とＯ₂とを用い、Ｗ膜を選択的にエッチングする。この時、第２のエッチング処理により第２の導電層６２８ｂ〜６３３ｂを形成する。一方、第１の導電層６１７ａ〜６２２ａは、ほとんどエッチングされず、第２の形状の導電層６２８〜６３３を形成する。
【００８５】
そして、レジストからなるマスクを除去せずに第１のドーピング処理を行い、島状の半導体膜にｎ型を付与する不純物元素を低濃度に添加する。ドーピング処理はイオンドープ法、若しくはイオン注入法で行えば良い。イオンドープ法の条件はドーズ量を１×１０¹³〜５×１０¹⁴/cm²とし、加速電圧を４０〜８０ｋｅＶとして行う。本実施例ではドーズ量を１．５×１０¹³/cm²とし、加速電圧を６０keVとして行う。ｎ型を付与する不純物元素として１５族に属する元素、典型的にはリン（Ｐ）または砒素（Ａｓ）を用いるが、ここではリン（Ｐ）を用いる。この場合、導電層６２８〜６３３がｎ型を付与する不純物元素に対するマスクとなり、自己整合的に不純物領域６２３〜６２７が形成される。不純物領域６２３〜６２７には１×１０¹⁸〜１×１０²⁰/cm³の濃度範囲でｎ型を付与する不純物元素を添加する。
【００８６】
レジストからなるマスクを除去した後、新たにレジストからなるマスク６３４ａ〜６３４ｃを形成して第１のドーピング処理よりも高い加速電圧で第２のドーピング処理を行う。イオンドープ法の条件はドーズ量を１×１０¹³〜１×１０¹⁵/cm²とし、加速電圧を６０〜１２０keVとして行う。ドーピング処理は第２の導電層６２８ｂ〜６３２ｂを不純物元素に対するマスクとして用い、第１の導電層のテーパー部の下方の島状の半導体膜に不純物元素が添加されるようにドーピングする。続いて、第２のドーピング処理より加速電圧を下げて第３のドーピング処理を行って図９（Ａ）の状態を得る。イオンドープ法の条件はドーズ量を１×１０¹⁵〜１×１０¹⁷/cm²とし、加速電圧を５０〜１００keVとして行う。第２のドーピング処理および第３のドーピング処理により、第１の導電層と重なる低濃度不純物領域６３６、６４２、６４８には１×１０¹⁸〜５×１０¹⁹/cm³の濃度範囲でｎ型を付与する不純物元素を添加され、高濃度不純物領域６３５、６３８、６４１、６４４、６４７には１×１０¹⁹〜５×１０²¹/cm³の濃度範囲でｎ型を付与する不純物元素を添加される。
【００８７】
次いで、レジストマスクを除去した後、新たにレジストマスク６５０ａ〜６５０ｃを形成して第４のドーピング処理を行う。この第４のドーピング処理により、ｐチャネル型ＴＦＴの活性層となる島状の半導体膜に前記一導電型とは逆の導電型を付与する不純物元素が添加された不純物領域６５３〜６５６、６５９、６６０を形成する。第２の導電層６２８ａ〜６３２ａを不純物元素に対するマスクとして用い、ｐ型を付与する不純物元素を添加して自己整合的に不純物領域を形成する。本実施例では、不純物領域６５３〜６５６、６５９、６６０はジボラン（Ｂ₂Ｈ₆）を用いたイオンドープ法で形成する。（図９（Ｂ））この第４のドーピング処理の際には、ｎチャネル型ＴＦＴを形成する島状の半導体膜はレジストからなるマスク６５０ａ〜６５０ｃで覆われている。第１乃至３のドーピング処理によって、不純物領域６３８、６３９にはそれぞれ異なる濃度でリンが添加されているが、そのいずれの領域においてもｐ型を付与する不純物元素の濃度を１×１０¹⁹〜５×１０²¹atoms/cm³となるようにドーピング処理することにより、ｐチャネル型ＴＦＴのソース領域およびドレイン領域として機能するために何ら問題は生じない。
【００８８】
以上までの工程で、それぞれの島状の半導体膜に不純物領域が形成される。次いで、活性化処理をおこなう。活性化処理は、公知のレーザー活性化、熱活性化またはＲＴＡ活性化のいずれでもよい。また、レーザー活性化処理工程の位置は、第１の層間絶縁膜を形成した後でも良い。
【００８９】
次いで、レジストからなるマスク６５０ａ〜６５０ｃを除去して第１の層間絶縁膜６６１を形成する。この第１の層間絶縁膜６６１としては、プラズマＣＶＤ法またはスパッタ法を用い、厚さを１００〜２００nmとして珪素を含む絶縁膜で形成する。本実施例では、プラズマＣＶＤ法により膜厚１５０nmの酸化窒化珪素膜を形成した。勿論、第１の層間絶縁膜６６１は酸化窒化珪素膜に限定されるものでなく、他の珪素を含む絶縁膜を単層または積層構造として用いても良い。
【００９０】
そして、加熱処理（３００〜５５０℃で１〜１２時間の熱処理）を行うと水素化を行うことができる。この工程は第１の層間絶縁膜６６１に含まれる水素により島状の半導体膜のダングリングボンドを終端する工程である。第１の層間絶縁膜の存在に関係なく島状の半導体膜を水素化することができる。水素化の他の手段として、プラズマ水素化（プラズマにより励起された水素を用いる）や、３〜１００％の水素を含む雰囲気中で３００〜６５０℃で１〜１２時間の加熱処理を行っても良い。
【００９１】
次いで、第１の層間絶縁膜６６１上に無機絶縁膜材料または有機絶縁物材料から成る第２の層間絶縁膜６６２を形成する。本実施例では、膜厚１．６μmのアクリル樹脂膜を形成したが、粘度が１０〜１０００cp、好ましくは４０〜２００cpのものを用いる。
【００９２】
次に、第２の層間絶縁膜６６２を形成した後、第２の層間絶縁膜６６２に接するように、第３の層間絶縁膜６７２を形成する。
【００９３】
そして、駆動回路６８６において、各不純物領域とそれぞれ電気的に接続する配線６６４〜６６８を形成する。なお、これらの配線は、膜厚５０nmのＴｉ膜と、膜厚５００nmの合金膜（ＡｌとＴｉとの合金膜）との積層膜をパターニングして形成する。もちろん、二層構造に限らず、単層構造でもよいし、三層以上の積層構造にしてもよい。また、配線の材料としては、ＡｌとＴｉに限らない。例えば、ＴａＮ膜上にＡｌやＣｕを形成し、さらにＴｉ膜を形成した積層膜をパターニングして配線を形成してもよい。図５（Ｇ）は、図１０のnチャネル型ＴＦＴ６８１の上面図であり、Ａ−Ａ‘における断面図が図５（Ｈ）に相当する。
【００９４】
また、画素部６８７においては、画素電極６７０、ゲート配線６６９、接続電極６６８を形成する。この接続電極６６８によりソース配線（６４３ａと６４３ｂの積層）は、画素ＴＦＴと電気的な接続が形成される。また、ゲート配線６６９は、画素ＴＦＴのゲート電極と電気的な接続が形成される。また、画素電極６７０は、画素ＴＦＴのドレイン領域６４２と電気的な接続が形成され、さらに保持容量を形成する一方の電極として機能する島状の半導体膜６５８と電気的な接続が形成される。また、画素電極６７１としては、ＡｌまたはＡｇを主成分とする膜、またはそれらの積層膜等の反射性の優れた材料を用いることが望ましい。
【００９５】
以上の様にして、ｎチャネル型ＴＦＴ６８１とｐチャネル型ＴＦＴ６８２からなるＣＭＯＳ回路、及びｎチャネル型ＴＦＴ６８３を有する駆動回路６８６と、画素ＴＦＴ６８４、保持容量６８５とを有する画素部６８７を同一基板上に形成することができる。こうして、アクティブマトリクス基板が完成する。
【００９６】
駆動回路６８６のｎチャネル型ＴＦＴ６８１はチャネル形成領域６３７、ゲート電極の一部を構成する第１の導電層６２８ａと重なる低濃度不純物領域６３６（ＧＯＬＤ領域）、ソース領域またはドレイン領域として機能する高濃度不純物領域６５２と、ｎ型を付与する不純物元素およびｐ型を付与する不純物元素が導入された不純物領域６５１を有している。このｎチャネル型ＴＦＴ６８１と電極６６６で接続してＣＭＯＳ回路を形成するｐチャネル型ＴＦＴ６８２にはチャネル形成領域６４０、ソース領域またはドレイン領域として機能する高濃度不純物領域６５４と、ｎ型を付与する不純物元素およびｐ型を付与する不純物元素が導入された不純物領域６５３を有している。また、ｎチャネル型ＴＦＴ６８３にはチャネル形成領域６４３、ゲート電極の一部を構成する第１の導電層６３０ａと重なる低濃度不純物領域６４２（ＧＯＬＤ領域）、ソース領域またはドレイン領域として機能する高濃度不純物領域６５６と、ｎ型を付与する不純物元素およびｐ型を付与する不純物元素が導入された不純物領域６５５を有している。
【００９７】
画素部の画素ＴＦＴ６８４にはチャネル形成領域６４６、ゲート電極の外側に形成される低濃度不純物領域６４５（ＬＤＤ領域）、ソース領域またはドレイン領域として機能する高濃度不純物領域６５８と、ｎ型を付与する不純物元素およびｐ型を付与する不純物元素が導入された不純物領域６５７を有している。また、保持容量６８５の一方の電極として機能する島状の半導体膜には、ｎ型を付与する不純物元素およびｐ型を付与する不純物元素が添加されている。保持容量６８５は、絶縁膜６１６を誘電体として、電極（６３２ａと６３２ｂの積層）と、島状の半導体膜とで形成している。
【００９８】
本実施例の画素構造は、ブラックマトリクスを用いることなく、画素電極間の隙間が遮光されるように、画素電極の端部をソース配線と重なるように配置形成する。
【００９９】
（実施例２）
本実施例では、本発明のレーザー照射方法を用いたＴＦＴの作製方法について説明する。
【０１００】
まず、図１３（Ａ）に示すように、絶縁表面上に非晶質半導体膜を成膜し、該非晶質半導体膜をエッチングすることで、島状の半導体膜６００１、６００２を形成する。図１３（Ｇ）は、図１３（Ａ）の上面図であり、Ａ−Ａ‘における断面図が図１３（Ａ）に相当する。次に図１３（Ｂ）に示すように、島状の半導体膜６００１、６００２を覆うように非晶質半導体膜６００３を成膜する。成膜直前に希フッ酸洗浄によって表面酸化膜を除去後、直ちに成膜することが望ましい。図１３（Ｈ）は、図１３（Ｂ）の上面図であり、Ａ−Ａ‘における断面図が図１３（Ｂ）に相当する。
【０１０１】
次に、図１３（Ｃ）に示すように、非晶質半導体膜６００３をパターニング加工することで、島状の半導体膜６００１、６００２を覆った島状半導体膜Ａの６００４が形成される。図１３（Ｉ）は、図１３（Ｃ）の上面図であり、Ａ−Ａ‘における断面図が図１３（Ｃ）に相当する。次に、図１３（Ｄ）に示すように、島状半導体膜Ａの６００４に、選択的にレーザー光を照射して、結晶性を高める。図１３（Ｊ）は、図１３（Ｄ）の上面図であり、Ａ−Ａ‘における断面図が図１３（Ｄ）に相当する。
【０１０２】
次に、図１３（Ｅ）に示すように、結晶性が高められた島状半導体膜Ａの６００４をパターニングし、島状半導体膜Ｂとなる６００８を形成する。図１３（Ｋ）は、図１３（Ｅ）の上面図であり、Ａ−Ａ‘における断面図が図１３（Ｅ）に相当する。そして、図１３（Ｆ）に示すように、島状半導体膜Ｂの６００８を活性層とする、ＴＦＴを形成する。以下の具体的な作製工程はＴＦＴの形状によって異なるが、代表的には島状半導体膜Ｂの６００８に接するようにゲート絶縁膜６００９を形成する工程と、ゲート絶縁膜上にゲート電極６０１０を形成する工程と、アイランド６００８に不純物領域６０１１、６０１２とチャネル形成領域６０１３を形成する工程と、ゲート絶縁膜６００９、ゲート電極６０１０及びアイランド６００８を覆って層間絶縁膜６０１４を形成する工程と、不純物領域６０１１、６０１２に接続した配線６０１５、６０１６を層間絶縁膜６０１４上に形成する工程とが行われる。図１３（Ｌ）は、図１３（Ｆ）の上面図であり、Ａ−Ａ‘における断面図が図１３（Ｆ）に相当する。
【０１０３】
本実施例で作製するＴＦＴの特徴として、不純物領域６０１１、６０１２の半導体膜厚は、チャネル形成領域６０１３の半導体膜厚よりも厚くなっている。一般に、チャネル領域に最適な膜厚の場合、不純物領域のシート抵抗の低減には限界があり、また、不純物領域に最適な膜厚の場合、チャネル領域が厚いためにオフリーク電流の増加がみられる。それぞれの最適膜厚はＴＦＴ特性に対してトレードオフの関係にある。本実施例の方法では、個々に最適な膜厚構成にすることができ、良好なトランジスタ特性に好ましい。
【０１０４】
（実施例３）
本実施例では、触媒を用いて半導体膜を結晶化させる工程を含む場合の、実施例を示す。実施例１とは異なる点のみ示す。触媒元素を用いる場合、特開平７−１３０６５２号公報、特開平８−７８３２９号公報で開示された技術を用いることが望ましい。
【０１０５】
非晶質半導体膜を成膜後にＮｉを用いて固相結晶化させる。例えば特開平７−１３０６５２号公報に開示されている技術を用いる場合、重量換算で５〜１００ｐｐｍのニッケルを含む酢酸ニッケル塩溶液をスピンコート法で非晶質半導体膜に塗布して、ニッケル含有層を形成し、５００℃、１時間の脱水素工程の後、５００〜６５０℃で４〜１２時間、例えば５５０℃、８時間の熱処理を行い結晶化する。尚、使用可能な触媒元素は、ニッケル（Ｎｉ）の以外にも、ゲルマニウム（Ｇｅ）、鉄（Ｆｅ）、パラジウム（Ｐｄ）、スズ（Ｓｎ）、鉛（Ｐｂ）、コバルト（Ｃｏ）、白金（Ｐｔ）、銅（Ｃｕ）、金（Ａｕ）、といった元素を用いても良い。
【０１０６】
また、酢酸ニッケル塩溶液を塗布する工程および熱処理工程は、島状半導体膜Ａをエッチング形成した後に、処理してもよい。
【０１０７】
ニッケル触媒元素を用いて固相結晶化させた膜は、柱状の結晶粒（グレイン）が集まった多結晶シリコン膜である。特徴として、そのグレイン間の粒界には対応粒界からなる領域が数多く存在することがわかっている。対応粒界は、通常の粒界とは異なり、粒界を挟む２つの結晶粒のそれぞれの結晶格子点のうち、ある一定の割合の格子点が両結晶粒で共通であるような特殊な方位関係にある粒界（連続性のよい粒界）である。一方で、従来の熱結晶化やレーザー結晶化のみで形成する多結晶では、粒界を挟む２つの結晶粒間の方位関係はランダムである。そのため、ニッケル触媒元素を用いて固相結晶化させた膜は、従来の熱結晶化やレーザー結晶化のみで形成する多結晶膜と比較して、電気的な障壁が小さい粒界から構成される多結晶シリコン膜であると考えている。
【０１０８】
そして、ニッケル触媒元素を用いて固相結晶化させた島状半導体膜Ａに対して、本発明のレーザー照射方法を適用することで、さらに結晶性の高められた半導体膜を得られることができる。つまり、ニッケル触媒元素を用いて固相結晶化させた時点で、すでに、グレイン間の粒界の連続性は、ある程度、形成されているが、さらに本発明のレーザー照射方法によって、グレイン内の点欠陥を消滅させることができる。
【０１０９】
ただし、レーザー光照射により得られた多結晶半導体膜は触媒元素を含んでおり、このままＴＦＴの活性層とすると、オフリーク電流を増大させる可能性がある。
【０１１０】
そのため、レーザー結晶化後にその触媒元素を結晶質半導体膜から除去する工程（ゲッタリング）を行う必要がある。ゲッタリングは特開平１０−１３５４６８号公報または特開平１０−１３５４６９号公報等に記載された技術を用いることができる。
【０１１１】
具体的には、レーザー照射後に得られる多結晶半導体膜の一部にリンを添加し、窒素雰囲気中で５５０〜８００℃、５〜２４時間、例えば６００℃、１２時間の熱処理を行う。本発明に適用する場合には、島状半導体膜ＡのうちＴＦＴのチャネル領域以外の半導体領域に、選択的にリンを添加した後、熱処理するのがよい。例えば、図５（Ｃ）で示す島状半導体領域Ａの場合、４５２（ａ）〜（ｈ）を除く半導体領域に選択的にリンを添加する。
【０１１２】
すると多結晶半導体膜のリンが添加された領域は、ニッケルの固溶度が大きいため、ゲッタリングサイトとして働き、多結晶半導体膜中に存在するニッケルをリンが添加された領域に偏析させることができる。これにより、ＴＦＴのチャネル領域のニッケルの濃度を１×１０¹⁷atoms/cm³以下好ましくは１×１０¹⁶atoms/cm³程度にまで低減された島状の半導体膜を得ることができる。
【０１１３】
なお、本実施例は実施例１または実施例２と組み合わせて実施することが可能である。
【０１１４】
（実施例４）
本実施例では、本発明のレーザー照射方法を用いて形成されるＴＦＴの構造について説明する。
【０１１５】
図１４（Ａ）に示すＴＦＴは、チャネル形成領域７００１と、チャネル形成領域７００１を挟んでいる第１の不純物領域７００２と、第１の不純物領域７００２とチャネル形成領域７００１との間に形成された第２の不純物領域とを含む活性層を有している。そして該活性層に接しているゲート絶縁膜７００４と、該ゲート絶縁膜上に形成されたゲート電極７００５とを有している。該ゲート電極の側面に接するように、サイドウォール７００６が形成されている。
【０１１６】
サイドウォール７００６はゲート絶縁膜７００４を間に介して第２の不純物領域７００３と重なっており、導電性を有していても絶縁性を有していても良い。サイドウォール７００６が導電性を有する場合、サイドウォール７００６を含めてゲート電極としても良い。
【０１１７】
図１４（Ｂ）に示すＴＦＴは、チャネル形成領域７１０１と、チャネル形成領域７１０１を挟んでいる第１の不純物領域７１０２と、第１の不純物領域７１０２とチャネル形成領域７１０１との間に形成された第２の不純物領域とを含む活性層を有している。そして該活性層に接しているゲート絶縁膜７１０４と、該ゲート絶縁膜上に積層された２層の導電膜７１０５、７１０６からなるゲート電極とを有している。該導電膜７１０５の上面及び導電膜７１０６の側面に接するように、サイドウォール７１０７が形成されている。
【０１１８】
サイドウォール７１０７は導電性を有していても絶縁性を有していても良い。サイドウォール７００６が導電性を有する場合、サイドウォール７００６を含めてゲート電極としても良い。
【０１１９】
図１４（Ｃ）に示すＴＦＴは、チャネル形成領域７２０１と、チャネル形成領域７２０１を挟んでいる第１の不純物領域７２０２と、第１の不純物領域７２０２とチャネル形成領域７２０１との間に形成された第２の不純物領域とを含む活性層を有している。そして該活性層に接しているゲート絶縁膜７２０４と、該ゲート絶縁膜上に導電膜７２０５と、該導電膜７２０５の上面と側面を覆っている導電膜７２０６と、該導電膜７２０６の側面に接するサイドウォール７２０７が形成されている。導電膜７２０５と、導電膜７２０６とはゲート電極として機能している。
【０１２０】
サイドウォール７２０７は導電性を有していても絶縁性を有していても良い。サイドウォール７００６が導電性を有する場合、サイドウォール７００６を含めてゲート電極としても良い。
【０１２１】
なお、本実施例は実施例１〜実施例３のいずれか一と組み合わせて実施することが可能である。
【０１２２】
【発明の効果】
スーパーラテラル成長による大結晶粒を連続的に形成させることができ、レーザー結晶化工程における基板処理効率を高めることができ、かつ、従来のＳＬＳ法のような特殊な光学系を必要としない簡便なレーザー照射方法を用いた半導体装置の作製方法を提供することができる。
【図面の簡単な説明】
【図１】 本発明に用いるレーザー照射装置の構成を示す図。
【図２】 島状半導体層Ａに対する、レーザー光スポットの走査方法を示す図。
【図３】 基板を回転させることで、基板内でのレーザー光スポットの相対的な移動方向を変化させて照射することを示す図。
【図４】 島状半導体層Ａと島状半導体層Ｂの形成位置との関係を示す図。
【図５】 島状半導体層Ａにおいて粒界の少ない領域のみをチャネル領域としたＴＦＴ作製方法を示す図。
【図６】 マーカー形成位置を示す図。
【図７】 アクティブマトリクス基板の作製方法を示す図。
【図８】 アクティブマトリクス基板の作製方法を示す図。
【図９】 アクティブマトリクス基板の作製方法を示す図。
【図１０】 アクティブマトリクス基板の作製方法を示す図。
【図１１】 実施例１で示すレーザー照射装置の光学系を示す図。
【図１２】 島状半導体層Ａと島状半導体層Ｂの形状例を示す図。
【図１３】 実施例２で示す本発明のレーザー照射方法を用いた半導体装置の作製方法を示す図。
【図１４】 実施例４で示す本発明のレーザー照射方法を用いた半導体装置の作製方法を示す図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a thin film transistor, and more particularly to a technique for forming a crystalline semiconductor film that forms an active layer of a thin film transistor.
[0002]
[Prior art]
As a method for forming an active layer of a thin film transistor (hereinafter referred to as TFT), there is a technique in which an amorphous semiconductor film is formed on a substrate having an insulating surface and crystallized by a laser annealing method or a thermal annealing method. Has been developed.
[0003]
The laser annealing method is known as a crystallization technique that does not raise the temperature of a glass substrate so much and can crystallize only an amorphous semiconductor film by applying high energy. In particular, an excimer laser that oscillates short-wavelength light having a wavelength of 400 nm or less is a typical laser that has been used since the development of this laser annealing method. In the laser annealing method, a laser beam is processed by an optical system so as to be spot-like or linear on the irradiated surface, and the irradiated surface on the substrate is scanned with the processed laser beam (the position where the laser beam is irradiated). Is moved relative to the irradiated surface).
[0004]
However, the crystalline semiconductor film produced by the laser annealing method is a collection of a plurality of crystal grains (the crystal grain size by the conventional excimer laser crystallization method is usually about 0.1 to 0.5 μm), The position and size of the crystal grains were random.
[0005]
A TFT fabricated on a glass substrate is formed by separating a crystalline semiconductor film into island-like patterns for element isolation, and cannot be formed by specifying the position and size of crystal grains. It was. For this reason, it has been almost impossible to form a channel formation region using a single crystal semiconductor film by eliminating the influence of crystal grain boundaries.
[0006]
The crystal grain interface (grain boundary) is a region where the translational symmetry of the crystal is broken. Due to crystal defects, the recombination centers of carriers, trap centers, and the influence of potential barriers at the grain boundaries. It is known that the current transport property of the carrier is deteriorated and the off current is increased in the TFT.
[0007]
By the way, a technique called super lateral growth is known which can form a large grain size as compared with a crystal grain size obtained by a conventional excimer laser crystallization method (see, for example, Non-Patent Document 1).
[0008]
[Non-Patent Document 1]
James S. Im, HJ Kim, “On the Super Lateral Growth Phenominone Observed in Excimer Laser Induced Crystallization of・ On the super lateral growth phenomenon observed in excimer laser-induced crystallization of thin Si films ”, Applied Physics Letters (Appl. Phys. Lett.), Vol. 64, No. 17, 1996 April 25, p2303-2305
[0009]
In the super lateral growth, a portion where the semiconductor film is completely melted by laser light irradiation and a portion where the solid phase semiconductor region remains are formed, and crystal growth starts using the solid phase semiconductor region as a crystal nucleus. Since it takes some time for nucleation to occur in the complete melting region, the solid phase semiconductor region is used as a crystal nucleus in the horizontal direction with respect to the film surface of the semiconductor film until nucleation occurs in the complete melting region ( Hereinafter, the crystal grows in the lateral direction). Therefore, the crystal grains grow to a length of several tens of times the film thickness. For example, lateral crystal growth with a length of 1 μm to 2 μm occurs with respect to a silicon film thickness of 60 nm. Hereinafter, this phenomenon is referred to as super lateral growth.
[0010]
In the case of the super lateral growth, relatively large crystal grains can be obtained, but the energy intensity region of the laser beam realized by the super lateral growth is much stronger than the intensity used in normal excimer laser crystallization. Further, the range of the energy intensity region is very narrow, and the position where the large crystal grains are obtained cannot be controlled from the viewpoint of crystal grain position control. Further, the region other than the large crystal grains is a microcrystalline region or an amorphous region where innumerable nucleation occurs, the crystal size is nonuniform, and the surface roughness of the crystal is very large. Therefore, generally used for manufacturing a semiconductor device is an irradiation condition in which a crystal grain size of about 0.1 μm to 0.5 μm can be easily made uniform.
[0011]
Also, ““ Sequential lateral solidification of thin silicon films on SiO₂”Robert S. Sposili and James S. Im, Appl. Phys. Lett. 69 (19), 4 November 1996, pp2864-2866”, James S. Im et al. Sequential Lateral Solidification method (hereinafter referred to as SLS method) that can realize super lateral growth is published. In this SLS method, a sample is irradiated with pulsed excimer laser light through a slit-shaped mask. For each shot, crystallization is performed by shifting the relative position of the sample and the laser beam by about the crystal length by super lateral growth (about 0.75 μm), so that the crystal by artificially controlled super lateral growth can be continuously produced. It is a method of forming.
[0012]
[Problems to be solved by the invention]
As described above, the SLS method can produce crystal grains that are artificially controlled and super laterally grown at an arbitrary place. However, there are the following problems.
[0013]
First, as a first problem, the substrate processing efficiency (throughput) is poor. As described above, in the SLS method, the crystallization distance per laser beam shot is about 1 μm. Therefore, the relative movement distance (feed pitch) between the beam spot of the laser beam on the sample surface and the sample substrate needs to be 1 μm or less. Under the conditions used in normal laser crystallization using a pulsed excimer laser, the feed pitch per shot of laser light is several tens of μm or more. Of course, a crystal peculiar to the SLS method cannot be produced under such conditions. In the SLS method, a pulsed XeCl excimer laser is used. The pulsed XeCl excimer laser has a maximum oscillation frequency of 300 Hz. This only produces a crystallization region with a distance of about 300 μm at maximum in one second with respect to the scanning direction of the laser beam. At such a processing speed, the substrate size becomes large. For example, in the case of 600 mm × 720 mm, the conventional SLS method requires a huge amount of processing time per substrate.
[0014]
The processing time per substrate is not only a time and cost problem. Actually, when the amorphous semiconductor film is crystallized, the surface treatment is important. For example, as a pretreatment, the natural oxide film may be removed with dilute hydrofluoric acid and then laser irradiation may be performed. There is a possibility that the natural oxide film will re-grow in the region where the laser is irradiated last, compared with the region where the laser is irradiated first in the substrate surface. In this case, there is a possibility that the amount of contaminant impurities such as carbon, oxygen, nitrogen element and boron incorporated into the finished crystal will be different within the substrate surface, which in turn will cause variations in transistor properties within the substrate surface. there is a possibility.
[0015]
The second problem is that the conventional SLS method tends to make the optical system complicated. It is necessary to incorporate a mask for processing the shape of the intensity of the laser beam on the substrate surface into a slit shape in the optical system. Usually, the film thickness of the active layer silicon used for the polycrystalline silicon thin film transistor is several tens of nm or more. When a pulsed excimer laser is used, the laser energy density required for laser crystallization is at least 200 mJ / cm.²(Typically, an amorphous silicon film of 50 nm is 400 mJ / cm with an XeCl excimer laser having a pulse width of 30 nsec.²Degree). In the SLS method, there is an optimum super lateral growth condition in a slightly stronger energy density region. It is difficult to produce a slit-shaped mask that can withstand such a strong laser energy density. In a mask made of metal, irradiation with a pulsed laser beam with high energy density causes the temperature of the film to rise and cool locally, and peeling and fine pattern shapes are destroyed by long-term use. (Chromium and other materials are used for resist exposure photolithography, but hard mask materials are used, but they are used at low energy densities that are not comparable to the laser energy density required for silicon crystallization. Therefore, there is no problem that the peeling or fine pattern shape collapses). As described above, in the conventional SLS method, there are elements that make the optical system complicated and make apparatus maintenance difficult.
[0016]
An object of the present invention is to solve the above-described problems and to simultaneously solve the problem of controlling the position of crystal grains in accordance with the arrangement of TFTs and improving the processing speed of the crystallization process. More specifically, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can continuously form large crystals by super lateral growth and increase the substrate processing efficiency in the laser crystallization process. .
[0017]
Furthermore, the present invention can continuously form large crystal grains by super lateral growth, can increase the substrate processing efficiency in the laser crystallization process, and can also apply laser light on the substrate surface as in the conventional SLS method. An object of the present invention is to provide a method for manufacturing a semiconductor device using a simple laser irradiation method that does not require a mask for processing a shape having a high intensity into a slit shape to be incorporated in an optical system.
[0018]
[Means for Solving the Problems]
A laser irradiation apparatus applied to the present invention includes a first means for controlling the irradiation position of a laser beam on a workpiece (a substrate and a thin film formed on the substrate), and a second means (laser for oscillating the laser beam). Oscillation device), a third means (optical system) for processing the laser light, and a laser beam spot controlled by the third means for controlling the oscillation of the second means. And a fourth means for controlling the first means so as to cover a position determined according to shape data (pattern information).
[0019]
There are two methods as the first means for controlling the irradiation position of the laser beam on the workpiece. One method is a method of changing the position of an object to be processed installed on a stage by driving the stage with a stage controller. The other is a method of moving the irradiation position of the laser light spot using a laser optical system with the substrate position fixed. In the present invention, any of the above two methods may be used, or a method combining the above two methods may be used.
[0020]
Note that the position determined in accordance with the photomask shape data (pattern information) is obtained by patterning the island-shaped semiconductor layer B by photolithography technique after crystallization in the semiconductor film, and the channel region of the transistor , A source region and a drain region.
[0021]
In the present invention, it is necessary to pattern the semiconductor film into the island-shaped semiconductor film A by photolithography technique and to form a marker on a part of the semiconductor film before laser beam irradiation. This marker is necessary for realizing the fourth means. The island-shaped semiconductor layer A is slightly larger than the island-shaped semiconductor layer B. FIG. 4A shows 430 as an example of the island-shaped semiconductor layer A, and 448 as an example of the island-shaped semiconductor layer B corresponding thereto. FIG. 4B shows 440 as an example of the island-shaped semiconductor layer A, and 449 as an example of the island-shaped semiconductor layer B corresponding thereto. That is, the island-shaped semiconductor layer B that finally becomes the channel region, the source region, and the drain region of the transistor is included in the island-shaped semiconductor layer A. Further, the island-shaped semiconductor layer A needs to have a shape in which at least a part of its outline is formed by connecting a plurality of chevron shapes or a saw blade shape. In addition, the angle θ in FIGS. 4A and 4C is preferably 30 ° or more and 110 ° or less. After the island-shaped semiconductor layer A having this shape is formed, laser light irradiation is performed, and then the island-shaped semiconductor layer B that becomes the active layer of the transistor is formed by controlling the position of the crystal grains in accordance with the TFT arrangement. It is necessary to make it more certain.
[0022]
The reason for this will be described with reference to FIGS. FIG. 2A illustrates 403 as the island-shaped semiconductor layer A. In the island-shaped semiconductor layer 403, the laser beam spot 400a is first irradiated with a pulse in a mountain-shaped peak region or a saw-blade tip region. Since the relative position of the sample and the laser beam is shifted every shot, the beam spot of the laser beam at the time of the next pulse irradiation is at the position 400b. Furthermore, the beam spot of the laser beam at the next pulse is at a position 400c. Here, the lateral crystal growth is easier to grow continuously as the pitch width between pulses is smaller. However, the laser beam spot of the island-shaped semiconductor layer A from the peak-shaped region of the mountain shape or the blade-shaped region of the saw blade shape. The crystal 411 formed in the direction of relative movement with respect to the substrate can further reduce the number of crystal grain boundaries because lateral crystal growth is more easily connected. FIG. 2B shows the regions having different crystallinity after laser light irradiation. The region α of 420 (a) to 420 (h) has few crystal grain boundaries, and other regions. In β (shaded area in FIG. 2B), the region has a relatively large number of crystal grain boundaries.
[0023]
FIG. 4 shows how the island-shaped semiconductor layer B is formed on the island-shaped semiconductor layer A having regions having different crystallinity after laser light irradiation. FIG. 4B shows an island-shaped semiconductor layer B corresponding to 430 of the island-shaped semiconductor layer A in FIG. In FIG. 4B, 438 to 433 are assumed to be TFT channel regions, and 431 and 432 are assumed to be impurity regions. What is important is that the crystal regions 438 to 433 serving as channel regions are formed from the mountain-shaped peak region or the saw-blade edge region in the island-shaped semiconductor layer A to the relative movement direction of the laser light spot with respect to the substrate. It corresponds to. That is, only the region α (420) to 420 (h) in FIG. 2B is selectively used as the channel region, and the other region β (the hatched portion in FIG. 2B) is the island-shaped semiconductor layer B. Remove during formation. However, since the crystallinity of the impurity region is not as high as that of the channel region, the region β can be left as an impurity region. Similarly, an island-shaped semiconductor layer B corresponding to 440 of the island-shaped semiconductor layer A in FIG. 4C is illustrated in FIG.
[0024]
As another example of the island-shaped semiconductor layer, the shapes of 900 in FIG. 12A and 903 in FIG. 12C may be used. As the island-shaped semiconductor layer B corresponding to these island-shaped semiconductor layers A, the shapes shown in FIGS. 12B and 12D can be considered.
[0025]
The island-shaped semiconductor layer A is crystallized using a laser irradiation apparatus having the first to fourth means. At this time, the fourth means is used to grasp the portion of the semiconductor film formed on the insulating surface that is left as the island-shaped semiconductor layer B on the substrate after patterning according to the photomask shape data. Then, using the marker as a position reference, the island-shaped semiconductor layer A is selectively irradiated with laser light to form a crystallized region. Next, a part of the island-shaped semiconductor layer A is etched by a photolithography technique and patterned into the island-shaped semiconductor layer B. This island-like semiconductor layer B is used as an active layer of the transistor.
[0026]
As described above, in the present invention, the entire semiconductor film in the substrate surface is not scanned and irradiated with the laser beam, but the laser beam is irradiated so that at least an indispensable portion can be crystallized at least. That is, after the semiconductor film is crystallized, the time for irradiating the portion to be removed with laser light can be saved by patterning the island-shaped semiconductor layer B. Therefore, the time required for laser crystallization can be shortened, and the processing speed of the substrate can be improved.
[0027]
By applying the above configuration, the problem that the substrate processing efficiency (throughput) of the conventional SLS method is poor is solved, and the position control of the crystal grains in accordance with the arrangement of the TFT is made more reliable. It becomes the means of.
[0028]
Furthermore, according to the present invention, it is possible to shorten the time required for laser crystallization, improve the processing speed of the substrate, and more surely control the position of crystal grains in accordance with the arrangement of TFTs. In addition to this method, there is provided a simple method that does not require the incorporation of a mask for processing the shape of the intensity of laser light on the substrate surface into a slit shape as in the conventional SLS method.
[0029]
In order to perform super lateral growth, it is necessary to rapidly change the spatial energy distribution of laser light in the direction of lateral crystal growth (that is, the direction in which the solid-liquid interface of the semiconductor film moves after laser irradiation). That is, it is necessary to minimize the attenuation region width of the light intensity between the laser light irradiation region and the non-irradiation region. When the attenuation region width capable of good super lateral growth is defined, the attenuation region width from the peak position of the light intensity until the intensity reaches 50% is 10 μm or less.
[0030]
In the conventional SLS method, since an excimer laser is used, the light condensing property necessary for the super lateral growth cannot be obtained only with a normal optical system. Therefore, it is considered that it was necessary to use a slit-shaped mask in order to partially shield the laser beam.
[0031]
The light source of the laser light is a device that irradiates the second harmonic (or the third harmonic and the fourth harmonic) of a pulsed solid-state laser oscillation device. With this laser configuration, it is possible to focus the beam on the spatial beam intensity profile of the laser beam, which is optimal for superlateral growth, using only a cylindrical lens used as a normal optical system lens.
[0032]
  In order to increase the substrate processing efficiency, it is desirable to set the repetition frequency and the feed pitch that are optimal for the SLS method. The conditions will be described below. The feed pitch is the substrate stage movement distance for each pulse of laser light. In the SLS method, there is a limit to the super lateral growth distance for each shot. Therefore, simply increasing the feed pitch does not increase the substrate processing efficiency. If the feed pitch is increased, the repetition frequency of the laser light must be increased accordingly. The XeCl excimer laser used in the conventional SLS method has a maximum frequency of 300 Hz. On the other hand, the pulsed solid-state laser oscillation device can set the repetition frequency to a maximum of several MHz. Therefore, a pulse oscillation solid-state laser oscillation device has a high repetition frequency.(0.5KHz or higher)As compared with the conventional SLS method, the processing capability can be greatly improved. The upper limit of the repetition frequency may be determined within a range in which the energy density necessary for super lateral growth can be ensured for each laser light shot, and this is determined by the maximum output of the main body of the pulsed solid-state laser oscillation device. (If other conditions are the same, increasing the frequency decreases the energy density for each laser light shot.)
[0033]
Further, in the solid-state laser oscillation device, it is preferable to use a semiconductor laser excitation solid-state laser oscillation device instead of the conventional flash lamp excitation because the stability of laser light energy is greatly improved.
[0034]
The following table shows a comparison between an XeCl gas laser irradiation apparatus and an Nd: YLF solid laser irradiation apparatus based on the SLS method.
[0035]
[Table 1]

[0036]
With the above configuration, large crystal grains can be continuously formed by super lateral growth, the substrate processing efficiency in the laser crystallization process can be increased, and the position of the crystal grains in accordance with the TFT arrangement A simple laser that can be controlled more reliably and does not need to incorporate a mask for processing the shape of the intensity of the laser light on the substrate surface into a slit like the conventional SLS method. A method for manufacturing a semiconductor device using an irradiation method can be provided.
[0037]
In the present invention, the semiconductor device includes all devices that can function by utilizing semiconductor characteristics (for example, an electronic device typified by a liquid crystal display panel and an electric appliance in which the electronic device is mounted as a component). Yes.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0039]
FIG. 1 shows a block diagram of the laser irradiation method of the present invention. In FIG. 1, two methods are shown as the first means for controlling the irradiation position of the pulse laser beam to the workpiece 107. One method is to change the position of the workpiece 107 (substrate) placed on the stage by driving the stage 108 by the stage controller 101. The other is a method of moving the irradiation position of the laser beam spot using the optical system 103 with the substrate position fixed. In the present invention, any of the above two methods may be used, or a method combining the above two methods may be used.
[0040]
The above two methods both mean changing the relative position of the laser light spot position with respect to the substrate, and this is indicated as “scanning the laser light spot” for convenience.
[0041]
The laser irradiation apparatus 100 includes a pulse laser oscillation apparatus 102 corresponding to a second means for oscillating pulse laser light. The pulse laser oscillation device 102 can be changed as appropriate depending on the purpose of processing. In the present invention, a known laser can be used. As the laser, a pulsed gas laser oscillating device or a solid laser oscillating device can be used. In this embodiment, a case where a pulsed oscillating solid laser oscillating device is used will be described.
[0042]
As pulse oscillation solid-state laser oscillator, YAG laser doped with Cr, Nd, Er, Ho, Ce, Co, Ti or Tm, YVO_FourLaser, YLF laser, YAlO_ThreeLaser, glass laser, ruby laser, alexandride laser, Ti: sapphire laser, forsterite laser (Mg₂SiO_Four). Although the fundamental wave of the laser differs depending on the material to be doped, laser light having a fundamental wave of around 1 μm can be obtained. The second harmonic, the third harmonic, and the fourth harmonic with respect to the fundamental wave can be obtained by using a nonlinear optical element.
[0043]
  In addition, the laser irradiation apparatus 100 includes an optical system 103 corresponding to a third means that can process a beam spot on an object to be processed of laser light oscillated from the laser oscillation apparatus 102. The shape of the laser beam emitted from the laser oscillation device 102 is circular if the rod shape is cylindrical, and rectangular if it is a slab type.Shape andBecome. By further shaping such laser light with an optical system, the beam spot of the laser light on the surface of the workpiece 107 can be formed into a desired shape.Preferably, the cross-sectional shape of the laser beam to be processed is formed into a linear shape or a rectangular shape, and the energy distribution in the short direction is a Gaussian shape or a flat top shape. Further, the length in the short direction is preferably 50 μm or less.
[0044]
Furthermore, the laser irradiation apparatus 100 has a computer 104 corresponding to a fourth means. The computer 104 can control the oscillation of the laser oscillator 102 and can control the stage controller 101 corresponding to the first means so as to cover the position where the beam spot of the laser beam is determined according to the mask pattern data. .
[0045]
Note that this laser irradiation method may include means for adjusting the temperature of the object to be processed in addition to the above four means.
[0046]
FIG. 2A shows a state where the relative position of the substrate and the laser beam spot is shifted (scanned) for each laser beam pulse. Reference numerals 400a, 400b, and 400c are enlarged views of beam spots on the substrate. Reference numeral 403 denotes the island-shaped semiconductor layer A, and at least a part of the outline of the island-shaped semiconductor layer A needs to have a shape in which a plurality of chevron shapes are continuous or a saw blade shape. In addition, the angle θ in FIG. 2A is 30 ° or more and 110 ° or less.
[0047]
In FIG. 2A, 400a is a laser beam spot position at the time of a certain pulse irradiation, 400b is a laser beam spot position at the time of the next pulse irradiation, and 400c is a laser beam beam at the time of the next pulse irradiation. Indicates the spot position. As shown in the figure, in the island-shaped semiconductor layer 403, laser light irradiation is performed from the peak-shaped region of the mountain shape or the blade edge region of the saw blade shape, toward the arrow indicating the relative movement direction of the laser light spot in the drawing, The laser beam spot position moves for each pulse.
[0048]
Reference numerals 401a and 401b denote substrate stage movement distances (feed pitches) for each pulse of laser light. This feed pitch needs to be 0.3 μm or more and 5 μm or less, more preferably 0.7 μm or more and 3 μm or less.
[0049]
Note that when the crystallized semiconductor film is used as an active layer of a TFT, it is desirable that the scanning direction be parallel to the direction in which carriers in the channel formation region move.
[0050]
This is shown in FIG. 4A is formed as an island-shaped semiconductor layer A before laser irradiation. FIG. 4B shows a shape in which 430 in FIG. Reference numerals 438 to 433 denote channel regions each having a shape obtained by dividing the channel of the single gate TFT into six. Impurity regions 431 and 432 are provided across the channel formation regions.
When the semiconductor film is crystallized using the laser oscillation device of the present invention, as indicated by the arrow, the scanning direction of the laser beam is parallel to the carrier moving direction (channel length direction) of the channel formation region. The scanning direction is determined. Reference numeral 523 denotes a beam spot of the laser beam, which scans in the direction of the arrow.
[0051]
Further, reference numeral 440 in FIG. 4C is formed as an island-shaped semiconductor layer A before laser irradiation. FIG. 4D shows a shape in which the 440 in FIG. FIG. 4D shows an example in which the channel formation region is a triple gate TFT provided in series between the source and drain. Impurity regions 441 and 443 are provided so as to sandwich the channel formation region 445. Impurity regions 443 and 444 are provided so as to sandwich the channel formation region 446, and impurity regions 444 and 447 are further provided so as to sandwich the channel formation region 447. When the semiconductor film is crystallized using the laser oscillation device of the present invention, the laser beam scans in the direction of the arrow shown in the figure.
[0052]
However, the TFT used for the active matrix display is convenient in terms of circuit layout in that the carrier movement direction of the active layer channel formation region is different in the pixel portion, the signal line drive circuit portion, and the scanning line drive circuit portion. . Even in such a case, the effectiveness of the present invention will be described with reference to FIG.
[0053]
In FIG. 3, for example, a case where the scanning direction of the laser light is changed in the scanning line driving circuit region 512 and other regions is shown. First, with reference to a marker formed on the substrate, a region 511 serving as a signal line driver circuit and a region 510 serving as a pixel portion are irradiated with laser as shown in FIG.
[0054]
Next, as shown in FIG. 3B, the substrate stage is rotated by 90 °, the marker formed on the substrate is read again, and the region 512 serving as the scanning line driving circuit is irradiated with the laser from this position information. To do. By doing so, it is possible to irradiate by changing the relative moving direction of the laser light spot in the substrate.
[0055]
Further, there may be a case where it is not desired to temporarily irradiate the substrate surface with laser light even during the laser irradiation process. In such a case, an AO (acousto-optic) light modulation element capable of temporarily and completely shielding laser light may be provided in the optical system between the substrate to be processed and the laser oscillation device. .
[0056]
Note that in order to determine the irradiation position of the laser beam, a marker for determining the position of the mask with respect to the semiconductor film needs to be formed on the semiconductor film. FIG. 6 shows a position where a marker is formed in a semiconductor film formed for manufacturing an active matrix semiconductor device. 6A illustrates an example in which one semiconductor device is manufactured from one substrate, and FIG. 6B illustrates an example in which four semiconductor devices are manufactured from one substrate.
[0057]
In FIG. 6A, reference numeral 540 denotes a semiconductor film formed over the substrate. A broken line 541 corresponds to a pixel portion, a broken line 542 corresponds to a signal line driver circuit, and a broken line 543 corresponds to a portion where a scanning line driver circuit is formed. Reference numeral 544 denotes a portion where a marker is formed (marker forming portion), and is provided so as to be positioned at the four corners of the semiconductor film.
[0058]
In FIG. 6A, four marker forming portions 544 are provided at four corners, respectively, but the present invention is not limited to this configuration. The position and the number of marker forming portions are not limited to the above-described modes as long as the laser beam scanning portion of the semiconductor film can be aligned with the mask for patterning the semiconductor film.
[0059]
In FIG. 6B, reference numeral 550 denotes a semiconductor film formed over the substrate, and a broken line 551 denotes a scribe line for dividing the substrate in a later step. In FIG. 6B, four semiconductor devices can be manufactured by dividing the substrate along the scribe line 551. Note that the number of semiconductor devices obtained by dividing is not limited thereto.
[0060]
Reference numeral 552 denotes a portion where a marker is formed (marker forming portion), which is provided so as to be positioned at the four corners of the semiconductor film. In FIG. 6B, four marker forming portions 552 are provided at the four corners, respectively, but the present invention is not limited to this configuration. The position and the number of marker forming portions are not limited to the above-described modes as long as the laser beam scanning portion of the semiconductor film can be aligned with the mask for patterning the semiconductor film.
[0061]
The marker may be formed simultaneously in the process of patterning the island-shaped semiconductor film A by a conventional photolithography technique.
[0062]
With the above structure, after the semiconductor film is crystallized, the time for irradiating the semiconductor film region removed by the formation of the island-shaped semiconductor film B with the laser light can be saved, so the time required for the laser light irradiation can be shortened. In addition, the processing speed of the substrate can be improved, and the position control of the crystal grains in accordance with the arrangement of the TFTs can be made more reliable.
[0063]
【Example】
Example 1
In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. Here, a substrate in which a pixel portion having a CMOS circuit, a driver circuit, a pixel TFT, and a storage capacitor is formed over the same substrate is referred to as an active matrix substrate for convenience. FIGS. 7 to 10 and FIGS. 5B, 5D, 5F, and 5H are cross-sectional views of the TFT manufacturing process. FIGS. FIG. 5B is a cross-sectional view (cross-sectional view in the channel length direction) when divided by a plane including a straight line connecting FIGS. 5B, 5D, 5F, and 5H are cross-sectional views in the channel width direction. It corresponds to.
[0064]
First, in this embodiment, a substrate 600 made of glass such as barium borosilicate glass or alumino borosilicate glass is used. Note that as the substrate 600, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.
[0065]
Next, a base film 601 formed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 600 by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). In this embodiment, the base film 601 includes two base films 601a and 601b, but a single layer film of the insulating film or a structure in which two or more layers are stacked may be used (FIG. 7A). .
[0066]
Next, an amorphous semiconductor film 692 is formed on the base film 601 with a thickness of 25 to 150 nm (preferably 30 to 120 nm) by a known means (sputtering method, LPCVD method, plasma CVD method, or the like) (FIG. 7). (A)). Note that although an amorphous semiconductor film is formed in this embodiment, a microcrystalline semiconductor film or a crystalline semiconductor film may be used. Alternatively, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used.
[0067]
Next, the amorphous semiconductor film 692 is patterned and halogen fluoride, for example, ClF, ClF_Three, BrF, BrF_Three, IF, IF_ThreeEtching is performed by an anisotropic dry etching method in an atmosphere including the like, thereby forming 693a, 693b, 693c, 693d, and 693e to be island-shaped semiconductor films A as shown in FIG. FIG. 5A is a top view of 693a, and a cross-sectional view taken along line A-A ′ corresponds to FIG.
[0068]
Next, 693a, 693b, and 693c of the island-shaped semiconductor film A are crystallized by a laser crystallization method. Laser crystallization is performed using the laser irradiation method of the present invention. Specifically, laser light is selectively irradiated to 693a, 693b, and 693c of the island-shaped semiconductor film A in accordance with mask information input to the computer of the laser irradiation apparatus. Of course, not only the laser crystallization method but also other known crystallization methods (thermal crystallization method using RTA or furnace annealing furnace, thermal crystallization method using metal element for promoting crystallization, etc.) You may go.
[0069]
In the laser irradiation method of the present invention, a pulsed gas laser oscillation device or a solid-state laser oscillation device can be used. In this embodiment, a case where a pulsed Nd: YLF laser is used will be described.
[0070]
FIG. 11 shows a laser crystallization treatment apparatus. FIG. 11 shows an example in which the Nd: YLF laser oscillation device 101 is used under the conditions of an output of 1.5 W and a repetition frequency of 1 kHz. The laser light source 101 is a system in which a YLF crystal and a nonlinear optical element are put in a resonator and a second harmonic wave having a wavelength of 527 nm is emitted. Of course, even when the nonlinear optical element is outside the resonator, Good. Further, in this laser light source 101, the rod shape is cylindrical, and the beam spot shape immediately after emission from the laser light source 101 is circular. However, the rod shape is slab type, and the beam spot shape immediately after emission. Even if it is rectangular, as shown below, the beam spot can be shaped into a desired shape by an optical system.
[0071]
This Nd: YLF laser has a beam divergence angle of 3 milliradians, and the beam size is about 2 mm in diameter at the exit, but spreads to about 1 cm in diameter at a position 20 cm away from the exit. If one convex lens 102 with a focal length f = 600 mm is inserted at this position, the beam size becomes parallel light with a diameter of about 10 mm. The laser light reflected by the optical mirrors 103 to 105 in FIG. 11 is condensed by the convex cylindrical lens 106 having a curvature in the Y direction in FIG. Here, the Y direction is the moving direction of the beam spot of the laser beam on the semiconductor film surface, and is the short direction of the beam spot. Further, the X direction in FIG. 11 is the long direction of the beam spot of the laser beam on the semiconductor film surface, and is a direction perpendicular to the moving direction of the beam spot of the laser beam on the semiconductor film surface. (The optical mirrors 103 to 105 are included in the layout of the apparatus and are not essential.) With the above configuration, the beam spot on the semiconductor film surface serving as the irradiation surface is 10 mm × 10 μm. Becomes a linear beam.
[0072]
However, the method for forming a linear or rectangular laser beam on the irradiated surface is not limited to this. Although not shown, a concave cylindrical lens can be inserted between the optical mirror 103 and the convex cylindrical lens 106 to lengthen the longitudinal direction of the beam spot. Further, a beam collimator for making the laser beam parallel light and a beam expander for spreading the laser beam can be inserted between the concave cylindrical lens and the laser light source 101. In addition, here, a method has been described in which the beam spot is a 10 mm × 10 μm linear beam with a laser light source of 1.5 W output. In addition, it is desirable to lengthen only the size in the longitudinal direction. (Currently, an LD-pumped Nd: YLF laser oscillator that can be used with an output of 20 W is commercially available.)
[0073]
In order to move the relative position of the beam spot of the laser beam on the semiconductor film surface, the substrate stage 101 is swept in the Y direction (short direction of the beam spot). If the repetition rate of the laser pulse is 1 kHz and the sweep speed of the substrate stage is 3.0 mm / sec, the relative position of the substrate and the beam spot is shifted by 3 μm in the Y direction each time the laser pulse is irradiated (feed pitch is 3 μm).
[0074]
By the laser crystallization described above, 694a, 694b, 694c, 694d, and 694e of the island-shaped semiconductor film A with improved crystallinity are formed as shown in FIG. 7C. FIG. 5C is a top view of 694a, and a cross-sectional view taken along line A-A ′ corresponds to FIG.
[0075]
Next, the island-shaped semiconductor film A 694a, 694b, 694c, 694d, and 694e are patterned into a desired shape to form the island-shaped semiconductor film B 602 to 606 as shown in FIG. FIG. 5E is a top view of 602, and a cross-sectional view taken along line A-A ′ corresponds to FIG.
[0076]
After forming the island-like semiconductor films B 602 to 606, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT. Further, the impurity doping for controlling the threshold value may be performed before laser crystallization or after the gate insulating film is formed.
[0077]
Next, a gate insulating film 607 is formed to cover the island-shaped semiconductor films 602 to 606. The gate insulating film 607 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0078]
Next, a first conductive film 608 with a thickness of 20 to 100 nm and a second conductive film 609 with a thickness of 100 to 400 nm are stacked over the gate insulating film 607. In this example, a first conductive film 608 made of a TaN film with a thickness of 30 nm and a second conductive film 609 made of a W film with a thickness of 370 nm were stacked. The TaN film is formed by sputtering, and is sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by sputtering using a W target. In addition, tungsten hexafluoride (WF₆It can also be formed by a thermal CVD method using In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less.
[0079]
In this embodiment, the first conductive film 608 is TaN and the second conductive film 609 is W. However, there is no particular limitation, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the element selected from these, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. In addition, the first conductive film is formed using a tantalum (Ta) film, the second conductive film is formed using a W film, the first conductive film is formed using a titanium nitride (TiN) film, and the second conductive film is formed. The first conductive film is formed of tantalum nitride (TaN), the second conductive film is formed of W, the first conductive film is formed of a tantalum nitride (TaN) film, Alternatively, the second conductive film may be a combination of Al films, the first conductive film may be a tantalum nitride (TaN) film, and the second conductive film may be a Cu film.
[0080]
The structure is not limited to the two-layer structure, and for example, a three-layer structure in which a tungsten film, an aluminum-silicon alloy (Al-Si) film, and a titanium nitride film are sequentially stacked may be employed. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten, or an aluminum / titanium alloy film (Al—Ti) is used instead of an aluminum / silicon alloy film (Al—Si) film. Alternatively, a titanium film may be used instead of the titanium nitride film.
[0081]
Next, resist masks 610 to 615 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. (FIG. 8 (B)) In this embodiment, ICP (Inductively Coupled Plasma) etching is used as the first etching condition, and CF is used as an etching gas._FourAnd Cl₂And O₂The gas flow ratio is 25:25:10 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered.
[0082]
Thereafter, the resist masks 610 to 615 are not removed and the second etching condition is changed, and the etching gas is changed to CF._FourAnd Cl₂The gas flow ratio is 30:30 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil type electrode at a pressure of 1 Pa to generate plasma and etching for about 30 seconds. Went. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF_FourAnd Cl₂Under the second etching condition in which is mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0083]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 617 to 622 (the first conductive layers 617 a to 622 a and the second conductive layers 617 b to 622 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form. Reference numeral 616 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 617 to 622 is etched by about 20 to 50 nm to form a thinned region.
[0084]
Next, a second etching process is performed without removing the resist mask. (FIG. 8C) Here, CF is used as an etching gas._FourAnd Cl₂And O₂Then, the W film is selectively etched. At this time, second conductive layers 628b to 633b are formed by a second etching process. On the other hand, the first conductive layers 617a to 622a are hardly etched, and the second shape conductive layers 628 to 633 are formed.
[0085]
Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the island-shaped semiconductor film at a low concentration. The doping process may be performed by ion doping or ion implantation. The condition of the ion doping method is a dose of 1 × 10¹³~ 5x10¹⁴/cm²The acceleration voltage is set to 40 to 80 keV. In this embodiment, the dose is 1.5 × 10¹³/cm²The acceleration voltage is 60 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 628 to 633 serve as a mask for the impurity element imparting n-type, and the impurity regions 623 to 627 are formed in a self-aligning manner. Impurity regions 623 to 627 have 1 × 10¹⁸~ 1x10²⁰/cm^ThreeAn impurity element imparting n-type is added in a concentration range of.
[0086]
After removing the resist mask, new resist masks 634a to 634c are formed, and the second doping process is performed at an acceleration voltage higher than that of the first doping process. The condition of the ion doping method is a dose of 1 × 10¹³~ 1x10¹⁵/cm²The acceleration voltage is set to 60 to 120 keV. In the doping treatment, the second conductive layers 628b to 632b are used as masks against the impurity element, and doping is performed so that the impurity element is added to the island-shaped semiconductor film below the tapered portion of the first conductive layer. Subsequently, the third doping process is performed by lowering the acceleration voltage than the second doping process to obtain the state of FIG. The condition of the ion doping method is a dose of 1 × 10¹⁵~ 1x10¹⁷/cm²The acceleration voltage is 50-100 keV. The low-concentration impurity regions 636, 642, and 648 overlapping with the first conductive layer by the second doping process and the third doping process have 1 × 10¹⁸~ 5x10¹⁹/cm^ThreeAn impurity element imparting n-type is added in the concentration range of 1 × 10 in the high-concentration impurity regions 635, 638, 641, 644 and 647.¹⁹~ 5x10^{twenty one}/cm^ThreeAn impurity element imparting n-type is added in a concentration range of.
[0087]
Next, after removing the resist mask, new resist masks 650a to 650c are formed, and a fourth doping process is performed. By this fourth doping treatment, impurity regions 653 to 656, 659, in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the island-shaped semiconductor film serving as the active layer of the p-channel TFT, 660 is formed. The second conductive layers 628a to 632a are used as masks for the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligning manner. In this embodiment, the impurity regions 653 to 656, 659, and 660 are diborane (B₂H₆) Using an ion doping method. (FIG. 9B) During the fourth doping process, the island-shaped semiconductor film forming the n-channel TFT is covered with masks 650a to 650c made of resist. Phosphorus is added to the impurity regions 638 and 639 at different concentrations by the first to third doping treatments, and the concentration of the impurity element imparting p-type is 1 × 10 5 in any of the regions.¹⁹~ 5x10^{twenty one}atoms / cm^ThreeBy performing the doping treatment so as to become, no problem arises because it functions as the source region and drain region of the p-channel TFT.
[0088]
Through the above steps, an impurity region is formed in each island-shaped semiconductor film. Next, an activation process is performed. The activation process may be any of known laser activation, thermal activation, and RTA activation. Further, the position of the laser activation process may be after the first interlayer insulating film is formed.
[0089]
Next, the resist masks 650a to 650c are removed, and a first interlayer insulating film 661 is formed. The first interlayer insulating film 661 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by plasma CVD. Needless to say, the first interlayer insulating film 661 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0090]
Then, hydrogenation can be performed by heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). This step is a step of terminating dangling bonds of the island-shaped semiconductor film with hydrogen contained in the first interlayer insulating film 661. The island-shaped semiconductor film can be hydrogenated regardless of the presence of the first interlayer insulating film. As other means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or heat treatment at 300 to 650 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen good.
[0091]
Next, a second interlayer insulating film 662 made of an inorganic insulating film material or an organic insulating material is formed over the first interlayer insulating film 661. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed, but one having a viscosity of 10 to 1000 cp, preferably 40 to 200 cp is used.
[0092]
Next, after the second interlayer insulating film 662 is formed, a third interlayer insulating film 672 is formed so as to be in contact with the second interlayer insulating film 662.
[0093]
In the driver circuit 686, wirings 664 to 668 that are electrically connected to the impurity regions are formed. Note that these wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm. Of course, not only a two-layer structure but also a single-layer structure or a laminated structure of three or more layers may be used. Further, the wiring material is not limited to Al and Ti. For example, a wiring may be formed by patterning a laminated film in which Al or Cu is formed on a TaN film and a Ti film is further formed. FIG. 5G is a top view of the n-channel TFT 681 in FIG. 10, and a cross-sectional view taken along line A-A ′ corresponds to FIG.
[0094]
In the pixel portion 687, a pixel electrode 670, a gate wiring 669, and a connection electrode 668 are formed. With this connection electrode 668, the source wiring (stacked layer of 643a and 643b) is electrically connected to the pixel TFT. The gate wiring 669 is electrically connected to the gate electrode of the pixel TFT. In addition, the pixel electrode 670 is electrically connected to the drain region 642 of the pixel TFT, and is further electrically connected to an island-shaped semiconductor film 658 that functions as one electrode forming a storage capacitor. Further, as the pixel electrode 671, it is desirable to use a highly reflective material such as a film containing Al or Ag as a main component or a laminated film thereof.
[0095]
As described above, a CMOS circuit including an n-channel TFT 681 and a p-channel TFT 682, a driver circuit 686 having an n-channel TFT 683, a pixel portion 687 having a pixel TFT 684 and a storage capacitor 685 are formed over the same substrate. can do. Thus, the active matrix substrate is completed.
[0096]
An n-channel TFT 681 in the driver circuit 686 has a channel formation region 637, a low concentration impurity region 636 (GOLD region) overlapping with the first conductive layer 628a which forms part of the gate electrode, and a high concentration functioning as a source region or a drain region. An impurity region 652 and an impurity region 651 into which an impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity are introduced are provided. The p-channel TFT 682, which is connected to the n-channel TFT 681 by the electrode 666 to form a CMOS circuit, includes a channel formation region 640, a high-concentration impurity region 654 that functions as a source region or a drain region, and an impurity element that imparts n-type conductivity And an impurity region 653 into which an impurity element imparting p-type conductivity is introduced. In the n-channel TFT 683, a channel formation region 643, a low-concentration impurity region 642 (GOLD region) that overlaps with the first conductive layer 630a that forms part of the gate electrode, and a high-concentration impurity that functions as a source region or a drain region The region 656 includes an impurity region 655 into which an impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity are introduced.
[0097]
A pixel TFT 684 in the pixel portion is provided with a channel formation region 646, a low concentration impurity region 645 (LDD region) formed outside the gate electrode, a high concentration impurity region 658 functioning as a source region or a drain region, and an n-type. An impurity region 657 into which an impurity element and an impurity element imparting p-type conductivity are introduced is provided. In addition, an impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity are added to the island-shaped semiconductor film functioning as one electrode of the storage capacitor 685. The storage capacitor 685 is formed of an electrode (stack of 632a and 632b) and an island-shaped semiconductor film using the insulating film 616 as a dielectric.
[0098]
In the pixel structure of this embodiment, the end portions of the pixel electrodes are arranged and formed so as to overlap the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.
[0099]
(Example 2)
In this example, a method for manufacturing a TFT using the laser irradiation method of the present invention will be described.
[0100]
First, as illustrated in FIG. 13A, an amorphous semiconductor film is formed over an insulating surface, and the amorphous semiconductor film is etched, whereby island-shaped semiconductor films 6001 and 6002 are formed. FIG. 13G is a top view of FIG. 13A, and a cross-sectional view taken along line A-A ′ corresponds to FIG. Next, as shown in FIG. 13B, an amorphous semiconductor film 6003 is formed so as to cover the island-shaped semiconductor films 6001 and 6002. It is desirable to form the film immediately after removing the surface oxide film by dilute hydrofluoric acid cleaning immediately before the film formation. FIG. 13H is a top view of FIG. 13B, and a cross-sectional view taken along line A-A ′ corresponds to FIG.
[0101]
Next, as shown in FIG. 13C, by patterning the amorphous semiconductor film 6003, an island-shaped semiconductor film A 6004 covering the island-shaped semiconductor films 6001 and 6002 is formed. FIG. 13I is a top view of FIG. 13C, and a cross-sectional view taken along line A-A ′ corresponds to FIG. Next, as illustrated in FIG. 13D, the island-shaped semiconductor film A 6004 is selectively irradiated with laser light to increase crystallinity. FIG. 13J is a top view of FIG. 13D, and a cross-sectional view taken along line A-A ′ corresponds to FIG.
[0102]
Next, as shown in FIG. 13E, the island-shaped semiconductor film A 6004 with improved crystallinity is patterned to form an island-shaped semiconductor film B 6008. FIG. 13K is a top view of FIG. 13E, and a cross-sectional view taken along line A-A ′ corresponds to FIG. Then, as shown in FIG. 13F, a TFT having the island-shaped semiconductor film B 6008 as an active layer is formed. Although the following specific manufacturing steps differ depending on the shape of the TFT, typically, a step of forming the gate insulating film 6009 so as to be in contact with the island-shaped semiconductor film B 6008 and a gate electrode 6010 are formed on the gate insulating film. A step of forming impurity regions 6011 and 6012 and a channel formation region 6013 in the island 6008, a step of forming an interlayer insulating film 6014 covering the gate insulating film 6009, the gate electrode 6010 and the island 6008, and an impurity region 6011. , 6012 are formed on the interlayer insulating film 6014. FIG. 13L is a top view of FIG. 13F, and a cross-sectional view taken along line A-A ′ corresponds to FIG.
[0103]
As a feature of the TFT manufactured in this embodiment, the semiconductor thickness of the impurity regions 6011 and 6012 is larger than that of the channel formation region 6013. In general, when the film thickness is optimal for the channel region, there is a limit to reducing the sheet resistance of the impurity region, and when the film thickness is optimal for the impurity region, the off-leakage current increases due to the thick channel region. . Each optimum film thickness has a trade-off relationship with TFT characteristics. In the method of this embodiment, an optimum film thickness configuration can be obtained individually, which is preferable for good transistor characteristics.
[0104]
(Example 3)
In this example, an example in which a step of crystallizing a semiconductor film using a catalyst is included is shown. Only differences from the first embodiment are shown. In the case of using a catalyst element, it is desirable to use the techniques disclosed in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329.
[0105]
After the amorphous semiconductor film is formed, solid phase crystallization is performed using Ni. For example, when using the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652, a nickel-containing layer is formed by applying a nickel acetate salt solution containing 5 to 100 ppm of nickel on a weight basis to an amorphous semiconductor film by spin coating. After the dehydrogenation step at 500 ° C. for 1 hour, crystallization is performed by heat treatment at 500-650 ° C. for 4-12 hours, for example, 550 ° C., 8 hours. In addition to nickel (Ni), usable catalyst elements include germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum ( Elements such as Pt), copper (Cu), and gold (Au) may be used.
[0106]
Further, the step of applying the nickel acetate salt solution and the heat treatment step may be performed after the island-shaped semiconductor film A is formed by etching.
[0107]
The film obtained by solid phase crystallization using a nickel catalyst element is a polycrystalline silicon film in which columnar crystal grains (grains) are collected. As a feature, it is known that there are many regions composed of corresponding grain boundaries at grain boundaries between the grains. Unlike normal grain boundaries, the corresponding grain boundaries have a special orientation in which a certain percentage of the lattice points of each of the two crystal grains sandwiching the grain boundaries are common to both crystal grains. It is a related grain boundary (a grain boundary with good continuity). On the other hand, in a conventional polycrystal formed only by thermal crystallization or laser crystallization, the orientation relationship between two crystal grains sandwiching the grain boundary is random. For this reason, a film obtained by solid-phase crystallization using a nickel catalyst element is composed of grain boundaries having a smaller electrical barrier than a polycrystalline film formed only by conventional thermal crystallization or laser crystallization. It is considered to be a polycrystalline silicon film.
[0108]
A semiconductor film with further improved crystallinity can be obtained by applying the laser irradiation method of the present invention to the island-shaped semiconductor film A that is solid-phase crystallized using a nickel catalyst element. . In other words, at the time of solid-phase crystallization using a nickel catalyst element, the continuity of grain boundaries between grains has already been formed to some extent. Defects can be eliminated.
[0109]
However, the polycrystalline semiconductor film obtained by laser light irradiation contains a catalytic element, and if it is used as the active layer of the TFT as it is, there is a possibility of increasing off-leakage current.
[0110]
Therefore, it is necessary to perform a step (gettering) of removing the catalytic element from the crystalline semiconductor film after laser crystallization. For the gettering, a technique described in JP-A-10-135468 or JP-A-10-135469 can be used.
[0111]
Specifically, phosphorus is added to part of the polycrystalline semiconductor film obtained after laser irradiation, and heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours. In the case of applying to the present invention, it is preferable that phosphorus is selectively added to a semiconductor region other than the channel region of the TFT in the island-shaped semiconductor film A and then heat-treated. For example, in the case of the island-shaped semiconductor region A shown in FIG. 5C, phosphorus is selectively added to the semiconductor regions excluding 452 (a) to (h).
[0112]
Then, the region of the polycrystalline semiconductor film to which phosphorus is added has a high solid solubility of nickel, so that it functions as a gettering site and segregates nickel present in the polycrystalline semiconductor film to the region to which phosphorus is added. it can. As a result, the concentration of nickel in the channel region of the TFT is reduced to 1 × 10.¹⁷atoms / cm^ThreePreferably 1 × 10¹⁶atoms / cm^ThreeAn island-shaped semiconductor film reduced to the extent can be obtained.
[0113]
Note that this embodiment can be implemented in combination with Embodiment 1 or Embodiment 2.
[0114]
Example 4
In this embodiment, a structure of a TFT formed using the laser irradiation method of the present invention will be described.
[0115]
A TFT illustrated in FIG. 14A is formed between a channel formation region 7001, a first impurity region 7002 sandwiching the channel formation region 7001, and the first impurity region 7002 and the channel formation region 7001. An active layer including a second impurity region; A gate insulating film 7004 in contact with the active layer and a gate electrode 7005 formed on the gate insulating film are provided. A sidewall 7006 is formed so as to be in contact with the side surface of the gate electrode.
[0116]
The sidewall 7006 overlaps with the second impurity region 7003 with the gate insulating film 7004 interposed therebetween, and may be conductive or insulating. In the case where the sidewall 7006 has conductivity, the gate electrode including the sidewall 7006 may be used.
[0117]
The TFT illustrated in FIG. 14B is formed between a channel formation region 7101, a first impurity region 7102 sandwiching the channel formation region 7101, and the first impurity region 7102 and the channel formation region 7101. An active layer including a second impurity region; A gate insulating film 7104 in contact with the active layer and a gate electrode formed of two conductive films 7105 and 7106 stacked on the gate insulating film are provided. A sidewall 7107 is formed so as to be in contact with the upper surface of the conductive film 7105 and the side surface of the conductive film 7106.
[0118]
The sidewall 7107 may have conductivity or insulation. In the case where the sidewall 7006 has conductivity, the gate electrode including the sidewall 7006 may be used.
[0119]
The TFT illustrated in FIG. 14C is formed between the channel formation region 7201, the first impurity region 7202 sandwiching the channel formation region 7201, and the first impurity region 7202 and the channel formation region 7201. An active layer including a second impurity region; Then, the gate insulating film 7204 in contact with the active layer, the conductive film 7205 over the gate insulating film, the conductive film 7206 covering the top and side surfaces of the conductive film 7205, and the side surface of the conductive film 7206 are contacted. Sidewalls 7207 are formed. The conductive film 7205 and the conductive film 7206 function as gate electrodes.
[0120]
The sidewall 7207 may be conductive or insulating. In the case where the sidewall 7006 has conductivity, the gate electrode including the sidewall 7006 may be used.
[0121]
In addition, a present Example can be implemented in combination with any one of Example 1- Example 3.
[0122]
【The invention's effect】
Large crystal grains can be continuously formed by super lateral growth, the substrate processing efficiency in the laser crystallization process can be increased, and a simple optical system that does not require a special optical system such as the conventional SLS method is easy. A method for manufacturing a semiconductor device using a laser irradiation method can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a laser irradiation apparatus used in the present invention.
FIG. 2 is a view showing a scanning method of a laser beam spot with respect to an island-shaped semiconductor layer A.
FIG. 3 is a diagram showing irradiation by changing the relative moving direction of a laser beam spot in the substrate by rotating the substrate.
FIG. 4 is a diagram showing a relationship between formation positions of island-shaped semiconductor layers A and island-shaped semiconductor layers B.
FIG. 5 is a view showing a TFT manufacturing method in which only a region with few grain boundaries in the island-shaped semiconductor layer A is used as a channel region;
FIG. 6 is a diagram showing a marker formation position.
FIGS. 7A and 7B illustrate a method for manufacturing an active matrix substrate. FIGS.
FIGS. 8A and 8B illustrate a method for manufacturing an active matrix substrate. FIGS.
FIGS. 9A and 9B illustrate a method for manufacturing an active matrix substrate. FIGS.
10A and 10B illustrate a method for manufacturing an active matrix substrate.
11 is a diagram showing an optical system of the laser irradiation apparatus shown in Example 1. FIG.
12A and 12B are diagrams showing examples of shapes of island-shaped semiconductor layers A and island-shaped semiconductor layers B.
13 shows a method for manufacturing a semiconductor device using the laser irradiation method of the present invention shown in Embodiment 2. FIG.
14A and 14B illustrate a method for manufacturing a semiconductor device using the laser irradiation method of the present invention described in Embodiment 4. FIGS.

Claims (11)

Forming an amorphous semiconductor film on the substrate;
The amorphous semiconductor film is etched to form a marker, and a first island-shaped semiconductor layer a part of the contour is a plurality of chevron of continuous form shape,
Using the marker as a position reference, the first island-shaped semiconductor layer is selectively irradiated with a laser beam having an attenuation region width of 10 μm or less until the intensity reaches 50% from the peak position of the light intensity. Crystallizing the first island-like semiconductor layer;
A portion of the crystallized first island-shaped semiconductor layer is etched to form a second island-shaped semiconductor layer that becomes a channel region, a source region, and a drain region of the transistor,
The channel region includes a region between the mountain-shaped peak region and an end facing the peak region,
The laser beam uses a pulsed solid laser oscillation device as a light source,
The laser light beam spot has a cross-sectional shape of a linear shape or a rectangular shape, and is simultaneously irradiated to each peak region of the plurality of chevron shapes of the first island-shaped semiconductor layer, and A plurality of chevron-shaped shapes moving from the summit region toward the end facing the summit region;
Movement direction before millet Musupotto a method for manufacturing a semiconductor device which is a parallel to the channel length direction of said transistor. Forming an amorphous semiconductor film on the substrate;
Etching the amorphous semiconductor film to form a marker and a first island-shaped semiconductor layer whose part of the contour is a saw- tooth shape,
Using the marker as a position reference, the first island-shaped semiconductor layer is selectively irradiated with a laser beam having an attenuation region width of 10 μm or less until the intensity reaches 50% from the peak position of the light intensity. Crystallizing the first island-like semiconductor layer;
A portion of the crystallized first island-shaped semiconductor layer is etched to form a second island-shaped semiconductor layer that becomes a channel region, a source region, and a drain region of the transistor,
The channel region includes a region between the saw blade-shaped blade region and an end facing the blade region,
The laser beam uses a pulsed solid laser oscillation device as a light source,
The beam spot of the laser beam has a cross-sectional shape of a linear shape or a rectangular shape, and is simultaneously irradiated to each of the plurality of saw blade-shaped regions of the first island-shaped semiconductor layer, and the saw Moving from each of the plurality of blade-shaped regions of the blade shape toward the end facing the blade region,
Movement direction before millet Musupotto a method for manufacturing a semiconductor device which is a parallel to the channel length direction of said transistor. In claim 1 or claim 2,
Forming a gate insulating film covering the second island-shaped semiconductor layer;
A method for manufacturing a semiconductor device, comprising forming a gate electrode over the gate insulating film. In any one of Claims 1 thru | or 3 ,
The solid laser oscillator includes a YAG laser oscillator, a YVO ₄ laser oscillator, a YLF laser oscillator, a YAlO ₃ laser oscillator, a glass laser oscillator, a ruby laser oscillator, a Ti: sapphire laser oscillator, and a forsterite laser oscillator. device or Nd: YLF method for manufacturing a semiconductor device comprising one or more der Rukoto selected from the laser oscillator. In any one of Claims 1 thru | or 3 ,
The solid-state laser oscillating device, a method for manufacturing a semiconductor device according to a semiconductor laser excitation solid-state laser oscillator der wherein Rukoto. In any one of Claims 1 thru | or 5 ,
The method of manufacturing a semiconductor device, wherein the laser light is second harmonic, third harmonic, or fourth harmonic. In any one of Claims 1 thru | or 6 ,
Wherein the laser beam is pulsed Rugoto, the beam spot position of the laser beam, a method for manufacturing a semiconductor device, characterized in that to move the distance of 0.3μm or more and 5μm or less. In any one of Claims 1 thru | or 7 ,
The energy distribution of the short direction of the bi-over beam spot, a method for manufacturing a semiconductor device according to a Gaussian shape or flat top shape der wherein Rukoto. In any one of Claims 1 thru | or 8 ,
The method of manufacturing a semiconductor device, wherein a length of the beam spot in a short direction is 50 μm or less. In any one of claims 1 to 9,
The method of manufacturing a semiconductor device, wherein an angle between a central axis in the longitudinal direction of the beam spot and a moving direction of the beam spot is a right angle. In any one of Claims 1 to 10 ,
A method for manufacturing a semiconductor device, wherein a moving direction of the beam spot is parallel to a straight line connecting a source region and a drain region of the transistor.

Images