JPS6319903B2 - - Google Patents

Info

Publication number
JPS6319903B2
JPS6319903B2 JP55046669A JP4666980A JPS6319903B2 JP S6319903 B2 JPS6319903 B2 JP S6319903B2 JP 55046669 A JP55046669 A JP 55046669A JP 4666980 A JP4666980 A JP 4666980A JP S6319903 B2 JPS6319903 B2 JP S6319903B2
Authority
JP
Japan
Prior art keywords
data
memory
bus
circuit
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55046669A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56143069A (en
Inventor
Kenji Oomori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP4666980A priority Critical patent/JPS56143069A/ja
Publication of JPS56143069A publication Critical patent/JPS56143069A/ja
Publication of JPS6319903B2 publication Critical patent/JPS6319903B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
JP4666980A 1980-04-09 1980-04-09 Bus coupling system Granted JPS56143069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4666980A JPS56143069A (en) 1980-04-09 1980-04-09 Bus coupling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4666980A JPS56143069A (en) 1980-04-09 1980-04-09 Bus coupling system

Publications (2)

Publication Number Publication Date
JPS56143069A JPS56143069A (en) 1981-11-07
JPS6319903B2 true JPS6319903B2 (enrdf_load_stackoverflow) 1988-04-25

Family

ID=12753756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4666980A Granted JPS56143069A (en) 1980-04-09 1980-04-09 Bus coupling system

Country Status (1)

Country Link
JP (1) JPS56143069A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61170859A (ja) * 1985-01-25 1986-08-01 Hitachi Ltd 計算機結合方式

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55134459A (en) * 1979-04-06 1980-10-20 Hitachi Ltd Data processing system

Also Published As

Publication number Publication date
JPS56143069A (en) 1981-11-07

Similar Documents

Publication Publication Date Title
US6088770A (en) Shared memory multiprocessor performing cache coherency
US4404628A (en) Multiprocessor system
US5029074A (en) Bus adapter unit for digital processing system
EP0764905A1 (en) An invalidation bus optimisation for multiprocessors using directory-based coherence protocols
US6647469B1 (en) Using read current transactions for improved performance in directory-based coherent I/O systems
US5249297A (en) Methods and apparatus for carrying out transactions in a computer system
US6141736A (en) Arrangement with master and slave units
CA1303229C (en) Bus adapter unit for digital data processing system
JP2000029776A (ja) メモリ要求取消し方法
US5089953A (en) Control and arbitration unit
JPH07152647A (ja) 共有メモリマルチプロセッサ
CN117389483B (zh) 一种内存管理方法、装置、电子设备及可读存储介质
JPS6319903B2 (enrdf_load_stackoverflow)
EP0169909B1 (en) Auxiliary memory device
JPS6342303B2 (enrdf_load_stackoverflow)
USRE38514E1 (en) System for and method of efficiently controlling memory accesses in a multiprocessor computer system
JP2885640B2 (ja) データバス転送方法
JPH04195576A (ja) キャッシュメモリ方式
JPH0750466B2 (ja) 並列計算機キャッシュ・メモリ制御方式
JP2971119B2 (ja) 複数プロセッサシステムにおける高速データ転送方式
JPH0522939B2 (enrdf_load_stackoverflow)
JPH03176754A (ja) マルチプロセッサシステム
JP3036809B2 (ja) マイクロコンピュータにおけるバッファ管理方式
JPH05233443A (ja) マルチプロセッサシステム
JP2696899B2 (ja) マルチプロセッサシステム