JPS6319846A - Composite semiconductor device for amplification - Google Patents

Abstract

PURPOSE:To contrive an increase in gm/gd by reducing the drain conductance gd in a current saturated region by a method wherein the title composite semiconductor device is composed of the first conductive channel type insulating gate type field effect transistor and the second conductive channel type junction gate type field effect transistor, and a current bypass circuit is provided between the source terminals of both transistors. CONSTITUTION:To the composite semiconductor device consisting of an N- channel type MOSFET 10 and a P-channel type junction gate field effect transistor JFET 11, a current bypass circuit 12 composed of a resistor, for example, is added. To be more precise, current-voltage characteristics are controlled by providing a current bypass circuit 12 between the terminals 17 and 18 of the composite semiconductor device having a differential negative condactance. As a result, the current-voltage characteristics are added to the current-voltage characteristics of the MOSFET, and besides, the drain conductance gd in the current saturated region becomes very small by, receiving the effect of bypass of the drain current of the current bypass circuit, and the gm/gd is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a composite semiconductor device for signal amplification.

[Conventional technology]

Conventionally, differential amplifiers using complementary field effect transistors (hereinafter abbreviated as CMOS) have often been used to amplify signals on semiconductor integrated circuits. CMO3 is n
Channel insulated gate field effect transistor (hereinafter referred to as
(abbreviated as MOS FET) and n-channel MOS F
The circuit diagram of FIG. 9 shows one stage of a differential amplifier constructed using such a CMO3. In the same figure, 1 and 2 are p-channel type MO3FE
T, 3 to 5 are n-channel type MOS FETs, 6 is a power supply voltage (DD) terminal, 7 is a first input terminal, 8 is a second input terminal, 9 is an output terminal, and 10 is a control terminal.

The amplification gain G in such an amplifier is MOSFE
Transconductance gm of T (mi ΔIl, /ΔVG)
and drain conductance g4 (=ΔΔIo/ΔV
It is known that it is given by the following equation using

G-20log+o(g,%/ga) −(
1) Therefore, in order to obtain a large G, it is necessary to make g,/ga as large as possible. To increase g, /g, (i) Increase g-.

(ii) Reduce gd.

(iii) Do both.

You have no choice but to take one of these methods. In the case of (i), if the manufacturing conditions of the semiconductor integrated circuit are not changed, MOS F
The only way to do this is to widen the ET gate width, shorten the gate length, or do both. However, widening the gate width increases the dimensions of the semiconductor integrated circuit, which is not a good idea, and shortening the gate length increases the
Although I increases, gd also increases at a similar rate, so there is virtually no effect. In the case of (ii), the only way to obtain this effect in a normal MOSFET is to make the gate length as long as possible, unless the manufacturing conditions of the semiconductor integrated circuit are changed. However, in this method, the gate width must be increased in order to maintain the magnitude of g, which forces the size of the semiconductor integrated circuit to increase.

Under such circumstances, the gate length actually adopted at present is about 2 to 3 μm. this is,
Considering the operating speed of MOS FET g. It was decided to increase the value of , sacrificing gd to some extent. And a commercial like this
In S, gm/ga is 30 (G is about 30dB)
It is well known from experience that this value is the limit value.

On the other hand, it is said that the gain required for an amplifier is usually 50 dB or more, and at present, to achieve this, it is necessary to connect two stages of CMO3 differential amplifiers as shown in Figure 9. ing.

[Problem that the invention seeks to solve]

However, connecting two CMO3 differential amplifiers naturally increases the size of the integrated circuit. Further, a feedback circuit is usually provided to stabilize the operation of the amplifier, but if feedback is applied as is, oscillation will occur because the input and output signals are in phase. Therefore, it is usually necessary to add an extra circuit called a phase compensation circuit.

More than several hundred differential amplifiers are used in high-speed analog/digital converter LSIs and high-speed digital/analog converter LSIs, which have recently become increasingly necessary.
The above problems caused by the need to connect two MO3 differential amplifiers have no negative impact on circuit design or integrated circuit connections (complicated design, poor yield, etc. on product prices). It is very large.

[Means for solving problems]

The amplification composite semiconductor device of the present invention has been made in view of the above problems, and includes a first conductive channel type MOSFET.
and a second conductive channel type JFET, the source terminal of the MOS FET is connected to the drain terminal of the JFET, the drain terminal of the MO3FET is connected to the gate terminal of the JFET, and the MOS FET is connected to the drain terminal of the JFET. F
A current bypass circuit is provided between the source terminal of the ET and the source terminal of the JFET.

[Effect]

If you treat the drain of the MOSFET as the drain terminal, the source of the JFET as the source terminal, and the gate of the MOSFET as the gate terminal and operate it like a normal MOSFET, the current-voltage characteristics of the MOSFET will differ from those of the JFET. is added, and the drain conductance g4 in the current saturation region becomes extremely small due to the effect of bypassing the drain current by the current bypass circuit, and gm/g4 increases.

〔Example〕

Hereinafter, the present invention will be described in detail along with examples.

Both FIG. 1 and FIG. 2 are circuit diagrams showing one embodiment of the present invention, and in the case of FIG. 1, an n-channel type MO3FE
A current bypass circuit 12 composed of, for example, a resistor is added to a composite semiconductor device consisting of a TIO and a p-channel junction gate field effect transistor (hereinafter abbreviated as JFET) 11, and in the case of FIG. Channel type MO
A current bypass circuit 12 is added to a composite semiconductor device consisting of a 3FET 13 and an n-channel type JFET 14. In FIGS. 1 and 2, numerals 15 to 18 are external connection terminals, and terminal 15 is a normal MOSFET.
The drain terminal of the ET, the terminal 16, corresponds to the gate terminal of a normal MOSFET, and the terminal 17 corresponds to the source terminal of a normal MOSFET.

Note that the terminal 18 is connected to the current bypass circuit 12 and M O5FE.
This is a connection terminal to the source of TIO.

Figure 3 shows the n-type MO3FETIO in the embodiment of Figure 1.
2 is a diagram showing a specific configuration of a composite semiconductor device consisting of a p-type JFET II and a p-type JFETII, in which FIG.
) is a sectional view taken along line BB' in figure (a), and figure (c) is a sectional view taken along line c-c' in figure (a). In the figure, 20 is a semiconductor substrate, 21 is an insulating layer, 22 is an active region made of a p-type semiconductor, 23 and 24 are n-type high impurity concentration regions, 25 and 26 are p-type high impurity concentration regions, 2
7 is a gate insulator layer. Note that the electrodes 15-18 are nothing but the terminals 15-18 in FIG. As can be seen from this figure, the n-channel MO3FETIO of FIG.
A p-channel type JFET 14 is formed by the p-type high impurity concentration regions 25, 26 and the p-type active region 22, and these two FETs 10 and 11 overlap each other orthogonally.

4(a) and 4(b) are both diagrams showing a specific configuration of the current bypass circuit 12 in the embodiment of FIG. 1, and FIG. 4(a) is an example using a diffusion layer resistor, and FIG. (b) is a cross-sectional view showing an example using a polycrystalline silicon resistor. In this figure, the same or corresponding parts as in FIG. 3 are given the same reference numerals. 30 is a p-type impurity region, 31.32
3 is a p-type high impurity concentration region, 33 is an insulating layer, 34 is polycrystalline silicon, 35 is an insulating layer, electrode 17a or 17b is connected to electrode 17 in FIG.
8b is connected to the electrode 18 in FIG.

Next, the operation and characteristics of this embodiment shown in FIG. 1 will be explained. Before explaining the overall operating characteristics, the current bypass circuit 12 is removed from the composite semiconductor device shown in FIG. 3 consisting of MO3FETIO and JFETII, that is, the circuit shown in FIG. The characteristics of the composite semiconductor device will be explained. In such a composite semiconductor device, the terminal 17 is grounded, and the terminal 16 is connected to a positive voltage VC.
A current value I flowing through the terminal 15 when a positive voltage VDS is applied to the terminal 15. The results of measuring , are shown in the current-voltage characteristic diagram in FIG. Table 1 shows the main structural constants of the semiconductor device used in this experiment.

Table 1 As is clear from FIG. 5, differential negative conductance appears in the current region indicated by rBJ in the figure. This differential conductance is a phenomenon unique to this composite semiconductor device, and is not observed in ordinary MOSFETs.

FIG. 10 is a current-voltage characteristic diagram of a normal MO3I"ET (for example, the one used in the differential amplifier in FIG. 9 and the MO3FETIO used in this embodiment). As is clear from this diagram, In a normal MOS FET, even in the saturation region, the drain current increases slightly as the drain-source voltage increases, and the drain conductance shows a positive value.

The reason why differential negative conductance is obtained in this composite semiconductor device as shown in FIG. 5 is as follows. First, in the region rAJ of FIG. 5, since VDS is small, the internal DC resistance of MO3FETIO is almost constant.

Further, since V D 5 also serves as the gate bias of the JFET, when this value is small, the JFET II is not pinched off. Therefore, ■. , with the increase of ID
S increases approximately linearly. On the other hand, the area rBJ
In this case, since the internal DC resistance of MO3FETIO increases approximately in proportion to the drain-source voltage, MO3FETIO
The drain current in IO saturates. On the other hand, terminal 15
voltage V. An increase in JFET II means that the gate bias of JFET II becomes deeper, and the conduction current of the JFET decreases. Therefore, the IDS is reduced in the entire composite semiconductor device, and a differential negative conductance as shown in FIG. 5 is obtained.

Note that in order to obtain a sufficiently large differential negative conductance using the composite semiconductor device having the structure shown in FIG.
It is necessary that the gate length of the ETIO be as long as the thickness of the depletion layer extending from the drain junction 24, and that the active region 22 be as thick as the depth of the drain junction 24.

Now, the device according to the present invention has terminals 18 and 17 of a composite semiconductor device having such differential negative conductance.
A current bypass circuit 12 is provided in between to further control the current-voltage characteristics.

6(a) to (c) respectively show the current bypass circuit 1
2 as 5. These are the results of measuring current-voltage characteristics, mutual conductance g, and drain conductance g when using an OkΩ resistor.

Note that the broken line part of the characteristic shown in Figure (c) is the part that cannot be measured due to the relationship with the measuring device, and is
This means that the value is less than or equal to 0-'S.

As can be seen from FIG. 6(a), the drain current ■ in the saturation region. , are almost constant regardless of the voltage VDI, unlike in FIG. This is caused by the current limited by JFET11 being conducted through the current bypass circuit 12, and can be achieved by appropriately setting the resistance value. The g obtained at this time is as shown in FIG. 6(b), as shown in FIG.
However, as shown in the same figure (C), the value of g4 becomes an extremely small value of 1 μs or less at its minimum value. .

This value is 1/1000 or less of the value obtained when operating a normal MOSFET. therefore,
The g-/gaO value is 300 or more, and an amplification gain G of 50 dB or more can be obtained.

In order to demonstrate the validity of such characteristic estimation, the seventh
We constructed a differential amplifier as shown in the figure and measured the amplification gain. In the figure, 41 to 44 are the amplification composite semiconductor devices of this embodiment, 45 is an input terminal, 46 is an output terminal,
47 is a feedback circuit, and 48 is an auxiliary output terminal for measurement. Note that Table 2 shows the main structural constants of the semiconductor device used here.

Further, Table 3 shows the measurement conditions for the amplification gain.

Table 2 Table 3 Figure 8 is a waveform diagram showing the measurement results.
The output signal voltage amplitude obtained from is 1.3 V. That is, the amplification gain is 309 (50 dB). This value is almost the same as the expected amplification gain, and confirms that it is easy to obtain a very high amplification gain by using the composite semiconductor device of the present invention.

〔Effect of the invention〕

As explained above, according to the composite semiconductor device for amplification of the present invention, the current-voltage characteristics of the JFET are added to the current-voltage characteristics of the MOS FET, and the current saturation is further affected by the bypass of the drain current by the current bypass circuit. The drain conductance g4 in the region becomes very small and ga/ga increases. Therefore, when a differential amplifier is configured using the composite semiconductor device for amplification of the present invention, 1
The amplification gain of the stage can be 50 dB or more. Therefore, it is not necessary to use two stages of differential amplifiers in order to obtain an amplification gain of 50 dB or more as in the conventional case.

As a result, the circuit is simplified and the design becomes easier.

Furthermore, the dimensions of the LSI are reduced and the manufacturing yield is improved.

[Brief explanation of the drawing]

1 and 2 are both circuit diagrams showing one embodiment of the present invention, FIG. 3 is a specific configuration diagram showing a composite semiconductor device consisting of MOS F ETlo and JFET II shown in FIG. 1, and FIG. A specific configuration diagram of the current bypass circuit shown in Fig. 1, and Fig. 5
6 is a characteristic diagram of the embodiment of FIG. 1, and FIG. 7 is a circuit showing a differential amplifier constructed using the amplifying composite semiconductor device of the present invention. 8 is a waveform diagram showing the characteristics of the differential amplifier shown in FIG. 7, and FIG. 9 is a circuit diagram showing a conventional differential amplifier using CMO3.
FIG. 10 is a current-voltage characteristic diagram of a normal MOS FET. 10...n-channel type MOS FET, 11 ・p
Channel type JFET, 12 current bypass circuit, 13...
・P-channel type MOS FET, 14...N-channel type JFET14. 15 to 18 are external connection terminals, respectively.

Claims (1)

[Claims] It is composed of a first conductive channel type insulated gate field effect transistor and a second conductive channel type junction gate field effect transistor, the source terminal of the insulated gate field effect transistor and the drain of the junction gate field effect transistor. a terminal of the insulated gate field effect transistor, a drain terminal of the insulated gate field effect transistor and a gate terminal of the junction gate field effect transistor, and a source terminal of the insulated gate field effect transistor and the junction gate field effect transistor. A compound semiconductor device for amplification that has a current bypass circuit between it and the source terminal.