JPH02176811A - Reference voltage generating circuit - Google Patents

Abstract

PURPOSE:To improve the power supply variance suppression ratio of the output voltage by setting a load MOSFET at the earth side to perform the differential single conversion at a differential input part. CONSTITUTION:When a power supply varies by DELTAV, the gate-source voltage of a constant current generating N channel depletion MOSFET 118 of a constant voltage generating circuit 120 has no change and therefore the drain current of a PMOSFET 117 has no change. Thus the potential of a node 122 serving as the gate voltage varies by DELTAV so that the drain current of the FET 117 is set at its unchanged level. Therefore the drain currents of MOSFET 107 - 109, 111 and 113 - 116 connected by the current mirror structure are not changed from their unchanged levels. Furthermore the potential of a node 123 serving as the gate voltage of the load MOSFET 103 and 104 which perform the differential single conversion at a differential input part 119 is not changed from its unchanged level. Thus a node 124, i.e., the output of the part 119 is not changed from its unchanged level. As a result, the variance of the power supply never leaks out to an output node 125 of an amplifying circuit 121.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a circuit configuration of a reference voltage generation circuit with an extremely high power supply fluctuation suppression ratio mounted on a semiconductor integrated circuit.

[Conventional technology]

Conventionally, this type of circuit is known as a ΔvT type fixed pressure voltage generation circuit.
As an example is shown in FIG. 2, an N-channel MO8 type field effect transistor (hereinafter abbreviated as MOSFET) 201
．． A differential input section 213 is composed of a differential input section 202 (abbreviated as DNMOSFET) and an N-channel diplarge 3F DNMOSFET, and an amplification section 214 (composed of 206 and 207 in FIG. 2) that amplifies the output of this differential input section. a single-stage inverter), and a constant voltage generation circuit 21 connected to these differential input sections and amplifier sections in a current mirror configuration.
5 (consisting of 208, 209, 210, and 211 in Fig. 2) and a phase compensation circuit 219 for stable operation of the circuit.
The gate electrode of MOSFET 202 is grounded.

In addition, MOSFET 2 0 3, 2 0 4 in Fig. 2. .

206, 208, 210, and 212 are P-channel MO8 field effect transistors (hereinafter abbreviated as PMOS FETs), and the remaining MOSFETs are all NMOSFETs, and the substrate potentials of the PMOSFETs are all connected to the power supply voltage. All substrate potentials of T are grounded.

However, the DNMOSFET 2 0 2 must be designed to have a threshold value that allows it to operate in the saturation region when a substrate bias is applied.

Further, an output voltage compensation circuit called a trimming circuit is generally provided between the output 216 and the inverting input 201, but it is omitted because it is not directly related to the present invention.

The outline of the circuit operation is as follows.

Since the output 216 is input to the inverting input NMOSFET 201, negative feedback is applied, and the output 216 has the NMOSFET 201.
A voltage appears such that the drain current ratio flowing through the SFETs 201 and 202 is the same as the W/L ratio of the PMOSFETs 203 and 204, and its value is expressed by the following equation.

However, μ is mobility, C6 is gate capacitance per unit area,
V (is is the gate-source voltage % V? is the threshold voltage, μp I t of each transistor) H V Q'
l rvT with the same subscript as the least significant digit of the respective MOSFET number, i.e., μ, is MOSFET I
(indicates the mobility of OI) W2 W.

L!　　　　　L＋ shall be.

[Problem to be solved by the invention]

The above-described conventional technology has a drawback that the power supply fluctuation suppression ratio (hereinafter abbreviated as PSRR) of the output voltage is small.

The reason for this will be explained below.

For example, if there is a fluctuation of ΔV in the power supply, the potential of the node 217, which is the gate electrode of the loads PMO3FBT203 and 204 that perform differential-to-single conversion in the differential input section, is P
The drain current of MOSFET203 and 204 is
The output node 218 of the differential input section fluctuates by ΔV so as to have the same magnitude as before the fluctuation in the power supply, and the output node 218 of the differential input section also fluctuates by ΔV.

Therefore, the greater the frequency of the fluctuation, the more this fluctuation leaks through the phase compensation capacitor 200 to the output node 216.

[Means to solve the problem]

The reference voltage generating circuit of the present invention has a gate electrode.

The first DN whose source electrode and substrate electrode are both grounded.
MOSFET and a first PMOSFET connected in diode form to the drain electrode of the DNMO3F'ET.
and second, third, and fourth PMOSFETs connected to the first PMOSFET in a current mirror configuration, the gate electrodes of which are constant biased, and the source electrodes of which are connected to the second,
and a fourth PMOSFET connected to the drain electrode of the third PMOSFET, a gate electrode and a drain electrode connected to the drain electrode of the fourth PMOSFET, and a source electrode and a substrate electrode connected to the drain electrode of the fourth PMOSFET. A first NMOSFET, both of which are grounded, and a second NMOSFET, whose gate electrode is common to the gate electrode of the first NMOSFET, whose source electrode and substrate electrode are both grounded, and whose gate electrode is A third NMO with a constant bias and a grounded source and substrate electrode.
SFET, the source electrode is connected to the third NMOSFET and the drain electrode, the gate electrode is connected to the input, the substrate electrode is grounded, and the drain electrode is connected to the second PM SFET.
40th NMOS connected to the drain electrode of OSFET
FET, a second DNMOSFET whose source electrode is connected to the drain electrode of the third PMOSFET, whose gate electrode and substrate electrode are grounded, and whose drain electrode is connected to the drain electrode of the third PMOSFET; from a fifth NMOS FET to which an electrode and a substrate electrode are connected, a gate electrode is connected to the drain/in electrode of the second NMOSFET, and a drain electrode is connected to the drain electrode of the fourth PMOSFET. The fifth NMOSFET is provided with a phase compensation circuit including at least a capacitor between the gate electrode and the drain electrode.

According to the present invention, the load MOSFET that performs differential-to-single conversion in the differential input section is located on the ground side rather than on the power supply side, so even if there is a fluctuation in the power supply, the fluctuation will not appear at the output node of the differential input section. There is an effect that there is no.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail with reference to the drawings. However, in the following explanation, it is assumed that the MOSFET has a sufficiently large channel length so that the channel length modulation effect of the drain current in the saturation region can be ignored.

FIG. 1(a) is a circuit diagram showing one embodiment of the present invention.

Now, if there is a fluctuation of ΔV in the power supply, the gate-source voltage of the constant current generation DNMOSFET 118 of the constant voltage generation circuit 120 does not change, so the drain current of the 2MOSFET 117 remains the same as before the fluctuation. Therefore, PMOS
The potential of the node 122, which is the gate electrode, also changes by ΔV so that the drain-to-drain current of the FET 117 becomes the same as before the change. Therefore, MOSFETs connected in a current mirror configuration
107.108,109,111,113,114゜1
The drain currents of is and ia are also unchanged from before the change. Furthermore, a load MOSF that performs differential-to-single conversion at the differential input section
Node 12 which is the gate electrode of ET103 and 104
Since the potential at node 3 remains the same as before the change, the output of the differential input section 124 is also the same as before the change. the result,
Fluctuations in the power supply do not leak to the output node 125.

FIG. 1(b) shows a comparison of the PSRH frequency characteristics of the reference voltage generating circuit of the prior art and the present invention.

It can be seen that while the PSRR characteristic 127 of the prior art deteriorates as the frequency increases, the PSRR characteristic 128 of the present invention has a DC PSRR extending to high frequencies, and the PSRR characteristic is significantly improved.

As is clear from the above explanation, the main focus of the present invention is NMO
Since the SFET input ΔV type reference voltage generation circuit is based on the fact that the MOSFET that performs differential-to-single conversion in the differential input section is on the ground side, for example, PMOSFET105, 106 as shown in Figure 1(e). The bias voltage supplied to the gate of the PMOSFET 115 can be generated by a diode-connected NMOSFET 129 vertically stacked with the PMOSFET 115, or an output voltage compensation circuit (generally called a trimming circuit) 131 can be used as shown in FIG. 1(d). In order to flow enough current to drive, the output 1 of the reference electrical generator circuit
It goes without saying that various variations are possible within the scope of the present invention, such as receiving 25 by the source follower of the DNMOSFET 131.

〔Effect of the invention〕

As explained above, in the present invention, the load MOSFET that performs differential-to-single conversion in the differential input section is located on the ground side rather than on the power supply side, so even if there is a fluctuation in the power supply, the output node of the differential input section remains unchanged. This has the effect of improving the PSRR of the circuit without causing fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram for explaining the prior art. 100.200...Capacitor, 105゜1
06.107,108,111,113,115゜11
7...PMOSFET, 203,204°20
6.208,210,212,101,102゜103
．． 104, 110, 112, 114.1/16...
・・NMOSFET% 118,129,201゜20
2.205,207,209,211,102゜118
．． 130...DNMOSFET, 119°21
3... Differential input section, 121, 214...
・Amplifier circuit, 120, 215... Constant voltage generation circuit, 126° 219... Phase compensation circuit, 131
...Trimming circuit, 122, 1.23...
... Gate node, 124°218 ... Output node of differential input section, 125°216 ... Output node, 127 ... PSRR characteristics of conventional technology,
128...PSRR characteristics of the present invention. Agent Patent Attorney Shintoshi Uchihara Profit (dB) /ρρ......Ten Yaha 5 Tar 10! ;, 106. IθZ/Tsuba...! 'MOSF
ET Mefl, 11 Yu 113i, 117 1θ Rodar/α,! ρ number・・・～MOδFETy1
0. Gui2. ii4. t16 tz2 . . . Gate node f6 . . . Rokanote 81 (o) 1. F / - ・ ... NMOSFET Fig. 1 (C) /3 - ... . . . Ll)

Claims (1)

[Claims] a first one-channel depletion MOSFET whose gate electrode, source electrode, and substrate electrode are all grounded; and the first one-channel depletion MOSFET.
a first other channel type MOSFET diode-connected to the drain electrode of the first other channel type MOSFET;
the second, third, and fourth other-channel type MOSFETs connected to T in a current mirror configuration; the gate electrodes are biased at a constant rate; and the source electrodes are the drain electrodes of the second and third other-channel type MOSFETs. the fourth and fifth other channel type MOSFETs connected to the fourth other channel type MOSFET, respectively, and the gate electrode and the drain electrode connected to the fourth other channel type MOSFET
The first one-channel MOSFET is connected to the drain electrode of the OSFET, and the source electrode and the substrate electrode are both grounded, and the gate electrode is common to the gate electrode of the first one-channel MOSFET, and the source electrode and the second one-channel MOSFET whose substrate electrodes are both grounded, the third one-channel MOSFET whose gate electrode is biased at a constant level, whose source electrode and substrate electrode are grounded, and whose source electrode is grounded. A fourth transistor is connected to the drain electrode of the third one-channel MOSFET, has a gate electrode connected to the input terminal, has a substrate electrode grounded, and has a drain electrode connected to the drain electrode of the second multi-channel MOSFET. The one-channel MOSFET has a source electrode connected to the drain electrode of the third one-channel MOSFET, a gate electrode and a substrate electrode that are grounded, and a drain electrode of the third other-channel MOSFET.
The second one-channel depletion MOSFET is connected to the drain electrode of the FET, the source electrode and the substrate electrode are grounded, the gate electrode is connected to the drain electrode of the second one-channel MOSFET, and the drain the fifth one-channel MOSFET, the electrode of which is connected to the drain electrode of the fourth other-channel MOSFET;
1. A reference voltage generation circuit comprising an ET and comprising a phase compensation circuit including at least a capacitor between the gate electrode and the drain electrode of the fifth one-channel MOSFET.