JPH0797605B2 - Amplification compound semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a composite semiconductor device for signal amplification.

[Conventional technology]

Conventionally, a differential amplifier using complementary field effect transistors (hereinafter abbreviated as CMOS) has often been used to amplify a signal on a semiconductor integrated circuit. The CMOS is composed of an n-channel insulated gate field effect transistor (hereinafter abbreviated as MOSFET) and a p-channel MOSFET, and one stage of a differential amplifier configured using such CMOS is shown in FIG. Shown in the circuit diagram. In the figure, 1 and 2 are p-channel MOSFETs, 3 to 5 are n-channel MOSFETs, 6
Is a power supply voltage _VDD terminal, 7 is a first input terminal, 8 is a second input terminal, 9 is an output terminal, and 10 is a control terminal. The amplification gain G in such an amplifier can be given by the following equation using the mutual conductance g _m (≡ΔI _D / ΔV _G ) and the drain conductance g _d (≡ΔΔI _D / ΔV _D ) of the MOSFET. Are known.

G = 20 log ₁₀ (g _m / g _d ) ... (1) Therefore, in order to obtain a large G, it is necessary to make g _m / g _d as large as possible. To increase g _m / g _d , (i) increase g _m . (Ii) Reduce g _d . (Iii) Do both. There is no choice but to take either method. In the case of (i), if the manufacturing conditions of the semiconductor integrated circuit are not changed, the only method is to widen the gate width of the MOSFET, shorten the gate length, or widen both of them. However, widening the gate width increases the size of the semiconductor integrated circuit, which is not a good idea. Shortening the gate length increases g _m ,
Since g _d also increases at the same rate, it has practically no effect. In the case of (ii), in order to obtain this effect in a normal MOSFET, the gate length has to be as long as possible unless the manufacturing conditions of the semiconductor integrated circuit are changed. But,
In this method, the gate width must be increased in order not to change the size of g _{m, and} the size of the semiconductor integrated circuit must be increased.

Under such circumstances, the gate length actually used at present is about 2 to 3 μm. this is,
It was decided to increase the value of g _m considering the operating speed of the MOSFET, and sacrifices g _d to some extent. And in such CMOS, g _m / g _d is 30
It is empirically well known that the value (G is about 30 dB) is the limit value.

On the other hand, it is said that the gain required as an amplifier is usually 50 dB or more.
It is necessary to connect two stages of CMOS differential amplifiers as shown in the figure.

[Problems to be solved by the invention]

However, connecting two stages of CMOS differential amplifiers means
Naturally, the size of the integrated circuit becomes large. A normal feedback circuit is provided in order to stabilize the operation of the amplifier, but if feedback is applied as it is, oscillation occurs because the input and output signals have the same phase. Therefore, it is usually necessary to add an extra circuit called a phase compensation circuit.

Several hundred or more differential amplifiers are used in high-speed analog / digital converter LSIs and high-speed digital / analog converter LSIs, which have become increasingly necessary recently, and CMOS differential amplifiers are connected in two stages. The above-mentioned problems caused by the necessity of having the above-mentioned problems have a great adverse effect on circuit design and integrated circuit connection (complexity of design, influence on product price due to poor yield, etc.).

[Means for Solving the Problems] The amplifying composite semiconductor device of the present invention has been made in view of the above problems, and includes a first conductive channel type MOSFET and a second conductive channel type MOSFET.
And a source terminal of the MOSFET and a source terminal of the JFET are connected to each other.
The drain terminal of ET and the gate terminal of the JFET are connected, and a current bypass circuit is provided between the source terminal of the MOSFET and the drain terminal of the JFET.

[Action]

When the drain of the MOSFET is regarded as the drain terminal, the drain of the JFET is regarded as the source terminal, and the gate of the MOSFET is regarded as the gate terminal and operated like a normal MOSFET, the current-voltage characteristic of the JFET is added to the current-voltage characteristic of the MOSFET. Further, the drain conductance g _d in the current saturation region becomes very small under the influence of the drain current bypass by the current bypass circuit, and g _m / g _d increases.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to Examples.

1 and 2 are circuit diagrams showing an embodiment of the present invention. In the case of FIG. 1, an n-channel MOSFET 10 and a p-channel junction gate field effect transistor (hereinafter
This is a composite semiconductor device consisting of a JFET (abbreviated as JFET) 11 and a current bypass circuit 12 composed of, for example, a resistor, and in the case of FIG. 2, a composite semiconductor consisting of a p-channel MOSFET 13 and an n-channel JFET 14. Current bypass circuit in device
12 is added. In FIGS. 1 and 2, reference numerals 15 to 18 are external connection terminals, terminal 15 is a drain terminal of a normal MOSFET, terminal 16 is a gate terminal of a normal MOSFET, and terminal 17 is a source terminal of a normal MOSFET. Equivalent to. The terminal 18 is a connection terminal between the current bypass circuit 12 and the source of the MOSFET 10.

FIG. 3 shows the n-type MOSFET 10 and p-type JF in the embodiment of FIG.
It is a figure which shows the concrete structure of the composite semiconductor device which consists of ET11, The figure (a) is a plane layout figure, The figure (b) is the figure (a).
11B is a cross-sectional view taken along the line BB ′ in FIG. In the figure, 20 is a semiconductor substrate, 21 is an insulating layer, 22 is an active region made of p-type semiconductor,
23 and 24 are n-type high impurity concentration regions, 25 and 26 are p-type high impurity concentration regions, and 27 is a gate insulating layer. In addition,
The electrodes 15-18 are nothing but the terminals 15-18 of FIG. As can be seen from the figure, the n-type high impurity concentration regions 23 and 24 and the p-type active region 22 form the n-channel MOSFET 10 of FIG. 1, and the p-type high impurity concentration regions 25 and 26 and the p-type active region 22 form the n-channel MOSFET 10. A p-channel JFET 14 is formed, and these two FETs 10 and 11 are orthogonal to each other and overlap each other.

FIGS. 4 (a) and 4 (b) are diagrams showing a concrete configuration of the current bypass circuit 12 in the embodiment of FIG. 1, and FIG. 4 (a) is an example using a diffusion layer resistor. (B) is a sectional view showing an example using a polycrystalline silicon resistor. In the figure, the same or corresponding parts as those in FIG. 3 are designated by the same reference numerals. Reference numeral 30 is a p-type impurity region, 31 and 32 are p-type high impurity concentration regions, 33 is an insulating layer, 34 is polycrystalline silicon, and 35 is an insulating layer. The electrode 17a or 17b is the electrode 17 of FIG. And 18a or 18b is connected to the electrode 18 of FIG.

Next, the operation and characteristics of this embodiment shown in FIG. 1 will be described. Before explaining the overall operating characteristics, it is shown in FIG.
The characteristics of the composite semiconductor device composed of the MOSFET 10 and the JFET 11, that is, the composite semiconductor device in which the current bypass circuit 12 is removed from the circuit of FIG. In such a composite semiconductor device, when the terminal 17 is grounded, the positive voltage V _GS is applied to the terminal 16, and the positive voltage V _DS is applied to the terminal 15, the result of measuring the current value I _DS flowing in the terminal 15 is shown. It is shown in the current-voltage characteristic diagram of FIG. The main structural constants of the semiconductor device used in this experiment are shown in Table 1.
Shown in.

As is clear from FIG. 5, it is understood that the differential negative conductance appears in the current region shown by “B” in the figure. This differential negative conductance is a phenomenon peculiar to this composite semiconductor device and is not seen in ordinary MOSFETs. 10th
The figure shows an ordinary MOSFET (for example, the one used in the differential amplifier of FIG. 9 and the MOSFET 10 used in this embodiment).
3 is a current-voltage characteristic diagram of FIG. As is apparent from this figure, in the normal MOSFET, the drain current also slightly increases with the increase of the drain-source voltage even in the saturation region, and the drain conductance shows a positive value.

As shown in FIG. 5, the reason why the differential negative conductance is obtained in this composite semiconductor device is as follows. First, since V _DS is small in area “A” in FIG. 5, M
The internal DC resistance of OSFET10 is almost constant. Also, V _DS
Since it is also the gate bias of JFET, JFET11 is not pinched off when this value is small. therefore,
I _DS increases almost linearly as V _DS increases. On the other hand, in the region “B”, the internal DC resistance of the MOSFET 10 increases almost in proportion to the drain-source voltage, so that the MOSFET
The drain current at 10 saturates. On the other hand, the increase in the voltage V _{DS at the} terminal 15 means that the gate bias of the JFET 11 becomes deeper, and the conduction current of the JFET decreases.
Therefore, as a whole of the composite semiconductor device, I _DS is reduced and the differential negative conductance is obtained as shown in FIG.

In order to obtain a sufficiently large differential negative conductance using the composite semiconductor device having the structure shown in FIG.
It is necessary that the gate length of the active region 22 be as long as the depletion layer extending from the drain junction 24 and the active region 22 be as thick as the depth of the drain junction 24.

In the device according to the present invention, the current-voltage characteristic is further controlled by providing the current bypass circuit 12 between the terminals 18 and 17 of the composite semiconductor device having such a differential negative conductance. 6 (a) to 6 (c) respectively,
Current-voltage characteristics when a 5.0 kΩ resistor is used as the current bypass circuit 12, mutual conductance g _m and drain
This is the result of measuring the conductance g _d . The broken line portion of the characteristic shown in FIG. 7C is a portion in which measurement is impossible due to the relation with the measuring device, which means that the value is 2.24 × 10 ⁻⁷ S or less.

As can be seen from FIG. 6 (a), the drain region I _DS in the saturation region is almost constant regardless of the voltage V _DS , unlike FIG. This is caused by the conduction of the current limited by the JFET 11 through the current bypass circuit 12, and can be achieved by setting the resistance value appropriately. As shown in FIG. 6 (b), the g _m obtained at this time is reduced to about one-third of the value obtained when the normal MOSFET is operated. As shown in the figure, the value of g _d is extremely small such that its minimum value is 1 μS or less. This value is the normal MO
It is 1/1000 or less of the value obtained when the SFET is operated. Therefore, the value of g _m / g _d becomes 300 or more, and the amplification gain G of 50 dB or more can be obtained.

In order to demonstrate the validity of such characteristic estimation,
The differential amplifier as shown in the figure was constructed and the amplification gain was measured. In the figure, 41 to 44 are composite semiconductor devices for amplification of this embodiment, 45 is an input terminal, 46 is an output terminal, 47 is a feedback circuit, and 48 is a measurement auxiliary output terminal. Table 2 shows main structural constants of the semiconductor device used here. Also,
Table 3 shows the measurement conditions of the amplification gain.

FIG. 8 is a waveform diagram showing the measurement results, and the output signal voltage amplitude obtained from the terminal 48 is 1.3 V with respect to the input signal having the voltage amplitude of 4.2 mV shown in FIG. In other words, the amplification gain is 309 (50dB). This is almost the same value as the expected amplification gain, which proves that it is easy to obtain a very high amplification gain by using the composite semiconductor device of the present invention.

〔The invention's effect〕

As described above, according to the amplifying composite semiconductor device of the present invention, the current-voltage characteristic of the JFET is added to the current-voltage characteristic of the MOSFET, and the influence of the bypass of the drain current by the current bypass circuit affects the current saturation region. The drain conductance g _d becomes very small and g _m / g _d increases. Therefore, when a differential amplifier is configured using the amplifying composite semiconductor device of the present invention, the amplification gain of one stage can be set to 50 dB or more. Therefore, 50 dB as in the past
It is not necessary to provide the differential amplifier in two stages in order to obtain the above amplification gain. As a result, the circuit is simplified and the design is facilitated. In addition, the size of the LSI is reduced and the manufacturing yield is improved.

[Brief description of drawings]

1 and 2 are circuit diagrams showing an embodiment of the present invention, FIG. 3 is a concrete configuration diagram showing a composite semiconductor device comprising MOSFET 10 and JFET 11 of FIG. 1, and FIG. Figure 5 is a concrete configuration diagram of the current bypass circuit.
FIG. 6 is a characteristic diagram of the current-voltage characteristic of the composite semiconductor device including the JFET 11 and JFET 11. FIG. 6 is a characteristic diagram of the embodiment of FIG. 1, and FIG. 7 is a differential amplifier formed by using the amplification composite semiconductor device of the present invention. Circuit diagram, FIG. 8 is a waveform diagram showing the characteristic of the differential amplifier of FIG. 7, FIG. 9 is a circuit diagram showing a conventional differential amplifier by CMOS, and FIG. 10 is a current-voltage characteristic diagram of a normal MOSFET. is there. 10 …… n-channel MOSFET, 11 …… p-channel JFET,
12 current bypass circuit, 13 ... p-channel MOSFET, 14 ...
... n-channel type JFETs 14 and 15 to 18 are external connection terminals.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 27/095 29/78 29/808 H03F 3/345 B 8943-5J 9171-4M H01L 29/80 E 9171- 4M C

Claims (1)

[Claims] 1. An insulated gate field effect transistor of a first conductive channel type and a junction gate type field effect transistor of a second conductive channel type, wherein a source terminal of the insulated gate field effect transistor and the junction gate type. A source terminal of the field effect transistor is connected, a drain terminal of the insulated gate field effect transistor is connected to a gate terminal of the junction gate field effect transistor, and a source terminal of the insulated gate field effect transistor is connected to the junction. A compound semiconductor device for amplification that has a current bypass circuit between it and the drain terminal of a gate-type field effect transistor.