JPS63198375A - Mes-type fet device - Google Patents
Mes-type fet deviceInfo
- Publication number
- JPS63198375A JPS63198375A JP3100187A JP3100187A JPS63198375A JP S63198375 A JPS63198375 A JP S63198375A JP 3100187 A JP3100187 A JP 3100187A JP 3100187 A JP3100187 A JP 3100187A JP S63198375 A JPS63198375 A JP S63198375A
- Authority
- JP
- Japan
- Prior art keywords
- region
- drain
- concentration
- edge
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000002344 surface layer Substances 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 17
- 230000001681 protective effect Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005865 ionizing radiation Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010802 sludge Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0891—Source or drain regions of field-effect devices of field-effect transistors with Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＧａＡｓ結昂を基板とするＭＢＳ型ＦＥＴ装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MBS type FET device using a GaAs sludge as a substrate.
従来のオフセット型ＭＥＳＦＥＴの構造の一例として、
第３図に示すものがある。すなわち、ＧａＡｓ基板１０
上にソース領域３．ドレイン領域４を設け、これらの間
に活性層５を有し、この活性層５上に金属のゲート電極
１を設け、ソース領域３、ドレイン領域４上にそれぞれ
オーミックコンタクト７を設け、これらオーミックコン
タクト７とゲート電極１との間にパッシベーション膜と
なる表面保護膜８を設けたものである。As an example of the structure of a conventional offset type MESFET,
There is one shown in Figure 3. That is, the GaAs substrate 10
Source area 3 on top. A drain region 4 is provided, an active layer 5 is provided therebetween, a metal gate electrode 1 is provided on this active layer 5, ohmic contacts 7 are provided on each of the source region 3 and drain region 4, and these ohmic contacts A surface protection film 8 serving as a passivation film is provided between the gate electrode 7 and the gate electrode 1 .
従来のＧ ａ Ａ ｓ −Ｍ Ｅ Ｓ Ｆ Ｅ Ｔにお
いては、ゲート・ドレイン間耐圧を向上させるように、
ゲート端部とドレイン端部との距離を適当にとり、ショ
ットキー空乏層のドレイン端部での電界集中を制御する
ことにより、所望の電極間耐圧を得ていた。In the conventional GaAs-MESFET, in order to improve the gate-drain breakdown voltage,
A desired interelectrode breakdown voltage was obtained by appropriately setting the distance between the gate end and the drain end and controlling the electric field concentration at the drain end of the Schottky depletion layer.
しかし、この従来技術では、比較的低濃度の活性層５も
しくはエピタキシャル成長層が表面に露出し、この露出
部分をシリコン酸化膜もしくはシリコン窒化膜等の表面
保護膜８で被覆している。However, in this prior art, the relatively low concentration active layer 5 or epitaxially grown layer is exposed at the surface, and this exposed portion is covered with a surface protection film 8 such as a silicon oxide film or a silicon nitride film.
従って、ゲート・ドレイン間の耐圧は、これら被覆した
絶縁膜８の荷電状態（正電荷または負電荷およびこれら
の電荷量）に依存し、しかもこれら電荷状態とは同一膜
種であっても、化成膜、プラズマ膜、ＣＶＤ膜等の形成
条件によって大きく変動するため、耐圧の制御性がよく
なかった。すなわち、耐圧はドレインのオフセット量の
みならず、膜質（膜種）依存性をもっこととなり、その
耐圧制御が困難となる。Therefore, the breakdown voltage between the gate and the drain depends on the charge state (positive charge or negative charge and the amount of these charges) of the insulating film 8 coated, and even if the film type is the same, the charge state is different from the charge state. The controllability of breakdown voltage was not good because it varied greatly depending on the formation conditions of the film, plasma film, CVD film, etc. That is, the breakdown voltage depends not only on the offset amount of the drain but also on the film quality (film type), making it difficult to control the breakdown voltage.
本発明の目的は、これらの問題点を解決し、表面保護膜
の荷電状態により影響されず、耐圧の制御性をよくした
ＭＥＳ型ＦＥＴ装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a MES type FET device that is not affected by the charging state of the surface protective film and has improved controllability of withstand voltage.
本発明の構成は、Ｇ ａ Ａ ｓからなる基板上にソー
ス領域、ドレイン領域およびこれら領域の間に活性層領
域を設け、この活性領域上にゲート金属を設け、このゲ
ート金属が前記ソース領域、ドレイン領域に対して偏在
したオフセットゲート構造からなるＭＥＳ型ＦＥＴ装置
において、前記ゲート金属の端部と前記ドレイン領域の
端部との間の中間領域の表面層に、前記活性層と同じ導
電型となる不純物をイオン注入して前記ソース領域、ド
レイン領域よりは低濃度で前記活性層よりは高濃度の中
間濃度領域を形成したことを特徴とする。The structure of the present invention is to provide a source region, a drain region, and an active layer region between these regions on a substrate made of GaAs, provide a gate metal on the active region, and provide the gate metal with the source region, In a MES type FET device having an offset gate structure unevenly distributed with respect to a drain region, a surface layer of an intermediate region between an end of the gate metal and an end of the drain region has the same conductivity type as the active layer. The present invention is characterized in that an intermediate concentration region having a lower concentration than the source region and the drain region and a higher concentration than the active layer is formed by ion-implanting an impurity.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。この図
において、１はゲート電極、２は中濃度活性領域で、２
１はゲート電極１に対しセルフ・アライン構造、２２は
オフセット構造の領域となっている。これら中濃度領域
端部２１，２２の遷択は、目標とするゲート・ドレイン
間耐圧の値により決る。比較的低耐圧の場合はセルフ・
アライン構造の中濃度の領域２１となり、高耐圧の場合
はオフセット構造の領域２２が適している。なお、この
領域２２をより高耐圧とするには、この領域２２がドレ
イン側に接近させる。しかし、ドレイン側ヘシフトする
ほど中濃度領域の表面電位緩和効果は薄れるので、目標
耐圧の許容する範囲で中濃度領域２２の端部はゲート側
へ接近することが好ましい。FIG. 1 is a sectional view of a first embodiment of the invention. In this figure, 1 is the gate electrode, 2 is the medium concentration active region, and 2 is the gate electrode.
1 is a region with a self-aligned structure with respect to the gate electrode 1, and 22 is a region with an offset structure. The transition of these intermediate concentration region ends 21 and 22 is determined by the target gate-drain breakdown voltage value. In the case of relatively low withstand voltage, self-
The medium concentration region 21 of the aligned structure is suitable, and the offset structure region 22 is suitable for high breakdown voltage. Note that in order to make this region 22 have a higher breakdown voltage, this region 22 is made closer to the drain side. However, as it shifts toward the drain side, the surface potential relaxation effect of the intermediate concentration region becomes weaker, so it is preferable that the end of the intermediate concentration region 22 approaches the gate side within the range allowed by the target breakdown voltage.
第２図は本発明の第２の実施例の断面図を示す。図中、
６はソース側に設けられた中濃度領域で、ソース抵抗を
減少させると同時にソース領域３とドレイン領域４とを
反転して使用することも可能となる例である。FIG. 2 shows a cross-sectional view of a second embodiment of the invention. In the figure,
Reference numeral 6 denotes a medium concentration region provided on the source side, which is an example in which the source resistance can be reduced and at the same time, the source region 3 and drain region 4 can be used inverted.
この中濃度の表面薄層２により、ゲート・ドレイン間耐
圧が表面保護膜８の荷電状態にはまず無関係になり、ゲ
ート端をドレイン端との距離のオフセット量のみに依存
することとなる。Due to this medium-concentration thin surface layer 2, the gate-drain breakdown voltage becomes independent of the charge state of the surface protection film 8, and depends only on the amount of offset of the distance between the gate end and the drain end.
また、γ線、Ｘ線等のイオン化放射線を照射して表面保
護膜中に発生したエレクトロン・ホールペアによって前
述の荷電状態が変化しても、ニレクロトンに比べてホー
ル膜中にトラップされ易いので中間濃度薄層により表面
電位変化が緩和される。In addition, even if the above-mentioned charge state changes due to electron-hole pairs generated in the surface protective film by irradiation with ionizing radiation such as gamma rays and The thin concentration layer alleviates surface potential changes.
以上説明したように、本発明によればゲート・ドレイン
間耐圧が、ゲート端とドレイン端との距離にのみ依存し
、表面保護膜・荷電状態には影響されず、耐圧制御が確
実にでき、表面保護膜の荷電状態の変動に対して安定な
素子が得られるという効果がある。As explained above, according to the present invention, the gate-drain breakdown voltage depends only on the distance between the gate end and the drain end, and is not affected by the surface protective film or charge state, and the breakdown voltage can be reliably controlled. This has the effect of providing a device that is stable against fluctuations in the charge state of the surface protective film.
第１図、第２図は本発明の第１および第２の実施例の断
面図、第３図は従来のＭＥＳ型ＦＥＴの構成を示す断面
図である。
１・・・ゲート電極（金属）、２．２１．２２・・・中
濃度領域、３・・・ソース領域、４・・・ドレイン領域
、５・・・活性層、６・・・ソース側中濃度領域、７・
・・オーミックコンタクト、８・・・表面保護膜（パッ
シベーション膜）、１０・・・基板。1 and 2 are cross-sectional views of the first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view showing the structure of a conventional MES type FET. 1... Gate electrode (metal), 2.21.22... Medium concentration region, 3... Source region, 4... Drain region, 5... Active layer, 6... Source side middle Concentration region, 7.
...Ohmic contact, 8...Surface protection film (passivation film), 10...Substrate.
Claims (1)
よびこれら領域の間に活性層領域を設け、この活性領域
上にゲート金属を設け、このゲート金属が前記ソース領
域、ドレイン領域に対して偏在したオフセットゲート構
造からなるＭＥＳ型ＦＥＴ装置において、前記ゲート金
属の端部と前記ドレイン領域の端部との間の中間領域の
表面層に、前記活性層と同じ導電型となる不純物をイオ
ン注入して前記ソース領域、ドレイン領域よりは低濃度
で前記活性層よりは高濃度の中間濃度領域を形成したこ
とを特徴とするＭＥＳ型ＦＥＴ装置。A source region, a drain region, and an active layer region between these regions are provided on a substrate made of GaAs, a gate metal is provided on the active region, and the gate metal is unevenly distributed with respect to the source region and the drain region. In the MES type FET device, an impurity having the same conductivity type as the active layer is ion-implanted into a surface layer in an intermediate region between an end of the gate metal and an end of the drain region. 1. A MES type FET device characterized in that an intermediate concentration region is formed with a lower concentration than the active layer and a higher concentration than the active layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3100187A JPS63198375A (en) | 1987-02-13 | 1987-02-13 | Mes-type fet device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3100187A JPS63198375A (en) | 1987-02-13 | 1987-02-13 | Mes-type fet device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63198375A true JPS63198375A (en) | 1988-08-17 |
Family
ID=12319336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3100187A Pending JPS63198375A (en) | 1987-02-13 | 1987-02-13 | Mes-type fet device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63198375A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2650915A1 (en) * | 1989-08-11 | 1991-02-15 | Thomson Composants Microondes | Field-effect transistor and method of producing it |
| JPH0499334A (en) * | 1990-08-18 | 1992-03-31 | Nec Corp | Field-effect transistor |
| JPH04188635A (en) * | 1990-11-19 | 1992-07-07 | Nec Corp | Manufacture of semiconductor device |
| US5324969A (en) * | 1991-08-20 | 1994-06-28 | Sanyo Electric Co., Ltd. | High-breakdown voltage field-effect transistor |
-
1987
- 1987-02-13 JP JP3100187A patent/JPS63198375A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2650915A1 (en) * | 1989-08-11 | 1991-02-15 | Thomson Composants Microondes | Field-effect transistor and method of producing it |
| JPH0499334A (en) * | 1990-08-18 | 1992-03-31 | Nec Corp | Field-effect transistor |
| JPH04188635A (en) * | 1990-11-19 | 1992-07-07 | Nec Corp | Manufacture of semiconductor device |
| US5324969A (en) * | 1991-08-20 | 1994-06-28 | Sanyo Electric Co., Ltd. | High-breakdown voltage field-effect transistor |
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