FR2650915A1 - Field-effect transistor and method of producing it - Google Patents
Field-effect transistor and method of producing it Download PDFInfo
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- FR2650915A1 FR2650915A1 FR8910829A FR8910829A FR2650915A1 FR 2650915 A1 FR2650915 A1 FR 2650915A1 FR 8910829 A FR8910829 A FR 8910829A FR 8910829 A FR8910829 A FR 8910829A FR 2650915 A1 FR2650915 A1 FR 2650915A1
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- source
- gate
- active layer
- drain
- doped
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- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title description 7
- 238000001465 metallisation Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052711 selenium Inorganic materials 0.000 claims description 2
- 239000011669 selenium Substances 0.000 claims description 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims 1
- 239000011810 insulating material Substances 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- -1 selenium ions Chemical class 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
TRANSISTOR.A EFFET DE CHAMP
ET SON PROCEDE DE REALISATION.TRANSISTOR.A FIELD EFFECT
AND ITS IMPLEMENTATION PROCESS.
La présente invention concerne un transistor à effet de champ, et le procédé de réalisation de ce transistor, dont la structure est asymétrique de façon à s'opposer à l'échauffement dans la région située entre source et grille. The present invention relates to a field effect transistor, and to the method of making this transistor, the structure of which is asymmetric so as to oppose heating in the region situated between source and gate.
Il est connu que dans un transistor à effet de champ tel que celui schématisé en figure 1, comportant une couche active 2 supportée par un substrat 1, c'est la région 6, située entre et sous les électrodes de source 3 et de grille 4 qui est soumise à un échauffement maximum. Cela correspond d'ailleurs aux lois de la physique, et à la répartition des courants et des champs. It is known that in a field effect transistor such as that shown diagrammatically in FIG. 1, comprising an active layer 2 supported by a substrate 1, it is region 6, located between and under the source 3 and gate 4 electrodes. which is subjected to maximum heating. This corresponds moreover to the laws of physics, and to the distribution of currents and fields.
Quelles que soient la structure, plane, creusée' ou en V, d'un transistor, ainsi que le nombre et la nature des. couches semiconductrices qui constituent la couche active 2, les transistors connus sont symétriques, c'est à dire que les niveaux de dopages sont les mêmes entre la grille et la source, ou entre la grille et le drain. Whatever the structure, plane, hollowed out 'or in V, of a transistor, as well as the number and the nature of. semiconductor layers which constitute the active layer 2, known transistors are symmetrical, ie the doping levels are the same between the gate and the source, or between the gate and the drain.
Cet échauffement peut présenter de graves inconvénients, allant jusqu a la destruction du transistor, si le dispositif est soumis à de fortes contraintes en tension de claquage ou en transconductance, donc en tension ou en courant. This heating can present serious drawbacks, going as far as the destruction of the transistor, if the device is subjected to strong stresses in breakdown voltage or in transconductance, therefore in voltage or in current.
Pour diminuer la résistance d'accès grille-source RGS, donc diminuer l'échauffement dans la région correspondante 6, soit on utilise des caissons fortement dopés, donc bons conducteurs, soit on décale la metallisation de grille vers la source. Ce déplacement a des limites : avec les transistors hyperfréquences dont la longueur source-drain est de tordre de 3 microns, il est très délicat, en fabrication, de décentrer la grille de quelques fractions de microns. In order to reduce the gate-source access resistance RGS, and therefore to reduce the heating in the corresponding region 6, either heavily doped wells, and therefore good conductors, are used, or the gate metallization is shifted towards the source. This movement has limits: with microwave transistors whose source-drain length is to twist by 3 microns, it is very difficult, in manufacture, to offset the gate by a few fractions of microns.
L'invention propose un procédé simple pour la réalisation d'un transistor a effet de champ de structure asymétrique : le caisson fortement dopé de type N+, sous la métallisation de source, est prolongé jusqu'à la grille, tandis que le caisson sous la métallisation de drain, est conforme à l'art connu, et' donc limité sensiblement à l'aire du contact ohmlque. La grille est donc en contact avec un matériau N du côté source, et avec un matériau N du côté drain. The invention proposes a simple method for producing a field effect transistor with an asymmetric structure: the heavily doped N + type well, under the source metallization, is extended to the gate, while the well under the drain metallization, is in accordance with the known art, and 'therefore limited substantially to the area of the ohmic contact. The gate is therefore in contact with a material N on the source side, and with a material N on the drain side.
De façon plus précise, l'invention concerne un transistor à effet de champ, comportant, supportées par un substrat en matériau semiconducteur, au moins une couche active contrôlée par une métallisation de grille et deux caissons de prises de contact, avec les métallisations d'accès, dites source et drain, ce transistor étant caractérisé par sa dissymétrie par rapport à la métallisation de grille, le caisson de source, plus dopé que la couche active, s'étendant jusqu'à la métallisation de grille. More precisely, the invention relates to a field effect transistor, comprising, supported by a substrate made of semiconductor material, at least one active layer controlled by a gate metallization and two contact socket wells, with the metallizations of access, called source and drain, this transistor being characterized by its asymmetry with respect to the gate metallization, the source well, more doped than the active layer, extending to the gate metallization.
L'invention sera mieux comprise par la description suivante d'un exemple de réalisation, qui aboutit à un exemple de transistor, en liaison avec les figures jointes en annexe, qui représentent - figure 1 : coupe schématisée d'un transistor à effet de champ selon l'art connu - fig. 2 à 5 : différentes étapes de réalisation d'un
#slstor, selon le procédé de l'invention.The invention will be better understood from the following description of an exemplary embodiment, which results in an example of a transistor, in conjunction with the appended figures, which represent - Figure 1: schematic section of a field effect transistor according to the known art - fig. 2 to 5: different stages of realization of a
#slstor, according to the method of the invention.
Le procédé concerne les transistors en silicium, en n'atérlaux du groupe III-V tel que GaAs ou encore en matériaux tel que GaAlAs épitaxié sur silicium ou un substrat semi-isolant. Cependant, afin de rendre les explications plus claires, l'invention sera exposée en s'appuyant sur l'exemple non limitatif d'un transistor à effet de champ en GaAs. The method relates to transistors in silicon, in non-atérlaux group III-V such as GaAs or else in materials such as GaAlAs epitaxied on silicon or a semi-insulating substrate. However, in order to make the explanations clearer, the invention will be explained by relying on the non-limiting example of a GaAs field effect transistor.
La première étape du procédé, en figure Z; consiste à protéger la surface d'une plaquette 1 de GaAs semi-isolant, qui sert de substrat, par une couche 7 de nitrure de silicium, sur une épaisseur de 0, 05 micron; cette encapsulation servira ultérieurement à protéger le matériau semiconducteur pendant les opérations de recuit. The first step of the process, in figure Z; consists in protecting the surface of a semi-insulating GaAs wafer 1, which serves as a substrate, with a layer 7 of silicon nitride, to a thickness of 0.05 microns; this encapsulation will subsequently serve to protect the semiconductor material during the annealing operations.
Un caisson 8, dopé de type N, et correspondant à l'aire du futur transistor, est obtenu par implantation profonde sur 0,2 micron d'ions de silicium ou de sélénium, sous une énergie comprise entre 100 et 350 KeV, dans le substrat semi-isolant 1. A well 8, doped with N type, and corresponding to the area of the future transistor, is obtained by deep implantation on 0.2 microns of silicon or selenium ions, at an energy of between 100 and 350 KeV, in the semi-insulating substrate 1.
Après implantation ionique, la plaquette est recuite pendant une quinzaine de minutes, à une température comprise entre 800 et 900 C, sous atmosphère de.... ?
Une seconde implantation ionique, en figure 3, d'ions de même nature que précédemment mais sous une énergie plus faible de l'ordre de 60-70 KeV, permet de réaliser, à l'intérieur du caisson N, deux petits caissons 9 et 10, moins profonds, 0,05 microns, mais dopés N
L'originalité de ces opérations, en soi connues, est que l'un des caissons N, celui qui correspond au futur contact ohmique de source, est prolongé jusqu'à l'axe de symétrie Il du transistor, qui correspond à la position du futur contact de grille.Il y a donc une dissymétrie qui est introduite, le caisson 10 de prise de contact 'de source est #longé jusqu'à l'emplacement de la grille, dans l'axe 11. Ces deux caissons N 9 et 10 sont séparés par une portion 12 du caisson N 8, qui -n'a pas reçue la seconde implantation ionique.After ion implantation, the wafer is annealed for about fifteen minutes, at a temperature between 800 and 900 C, under an atmosphere of ....?
A second ion implantation, in FIG. 3, of ions of the same nature as above but at a lower energy of the order of 60-70 KeV, makes it possible to produce, inside the N well, two small wells 9 and 10, shallower, 0.05 microns, but N doped
The originality of these operations, known per se, is that one of the N wells, the one which corresponds to the future ohmic source contact, is extended as far as the axis of symmetry II of the transistor, which corresponds to the position of the future gate contact. There is therefore an asymmetry which is introduced, the source contact box 10 is # skirted to the location of the gate, in axis 11. These two boxes N 9 and 10 are separated by a portion 12 of the N box 8, which has not received the second ion implantation.
Cette seconde implantation ionique ne requiert pas une extrême précision dans le positionnement du caisson de source 9 par rapport à l'axe de symétrie 11. Si on appelle "d" la distance entre le bord du caisson 9 et l'axe de symétrie 11, cette distance peut être nulle, ou positive ou négative de quelque 0,5 micron par rapport à l'axe 11, pour r --3istor dans lequel la distance source-drain est de l'ordre de 3 microns. En effet, ultérieurement, une tranchée ou "recess" sera gravée, qui éliminera les matériaux semiconducteurs voisins de l'axe de symétrie 11. This second ion implantation does not require extreme precision in the positioning of the source box 9 relative to the axis of symmetry 11. If we call "d" the distance between the edge of the box 9 and the axis of symmetry 11, this distance may be zero, or positive or negative by some 0.5 microns with respect to axis 11, for r --3istor in which the source-drain distance is of the order of 3 microns. Indeed, subsequently, a trench or "recess" will be etched, which will eliminate the semiconductor materials neighboring the axis of symmetry 11.
La plaquette est soumise à un second recuit, dans les mêmes conditions que le premier recuit, après la seconde implantation ionique. The wafer is subjected to a second annealing, under the same conditions as the first annealing, after the second ion implantation.
La couche 7 de nitrure de silicium est alors gravée à l'emplacement des contacts de source et de drain, et les métallisations de contacts ohmiques 3 et 5 sont déposées, ainsi que représenté en figure 4. Puis une tranchée ou "recess" est gravée par des moyens connus, tel que la gravure sèche ionique ou RIE (Réaction Ion Etching). Ce "recessn est marqué sur la figure 4 par un pointillé : il est symétrique par rapport à l'axe de symétrie 11, a une ouverture correspondant à la longueur de la grille, 0,5 micron par exemple, et pénètre partiellement dans le caisson N de source 9. Le "recess"- doit être au moins aussi profond que le caisson 9, du sorte qu'il a un flanc constitué de matériaux dopé N+ (caisson 9) et un flanc constitué de matériau dopé N (portion 12 du caisson 8). The layer 7 of silicon nitride is then etched at the location of the source and drain contacts, and the metallizations of ohmic contacts 3 and 5 are deposited, as shown in FIG. 4. Then a trench or "recess" is etched. by known means, such as dry ionic etching or RIE (Reaction Ion Etching). This "recessn is marked in Figure 4 by a dotted line: it is symmetrical with respect to the axis of symmetry 11, has an opening corresponding to the length of the grid, 0.5 micron for example, and partially penetrates into the box. Source N 9. The "recess" - must be at least as deep as well 9, so that it has a side made of N + doped materials (well 9) and a side made of N doped material (portion 12 of the box 8).
Le recess est utilisé comme masque pour le dépôt de la métallisation Schottky de grille 5 : Ti-Pt-Au pulvérisés par des moyens directionnels, suivi d'une recharge électrolytique d'or. The recess is used as a mask for the deposition of the Schottky metallization of gate 5: Ti-Pt-Au sprayed by directional means, followed by an electrolytic recharge of gold.
Le transistor achevé est représenté en figure 5 : il est asymétrique en ce sens que la région d'accès de la source vers la grille est composée de GaAs dopé N+ (caisson 9), tandis que la région d'accès du drain vers la grille est composée de GaAs dopé N (portion 12). The completed transistor is shown in Figure 5: it is asymmetric in that the access region from the source to the gate is composed of N + doped GaAs (well 9), while the access region from the drain to the gate is composed of N-doped GaAs (portion 12).
Dans une variante au procédé, la plaquette de GaAs peut ne pas être encapsulée par une couche 7 de nitrure de silicium. In a variant of the method, the GaAs wafer may not be encapsulated by a layer 7 of silicon nitride.
Dans ce cas, les opérations de recuit sur substrat nu se font en atmosphère d'arsine, pour éviter la dégradation de GaAs.In this case, the annealing operations on a bare substrate are carried out in an arsine atmosphere, to avoid the degradation of GaAs.
Par rapport à un transistor de même dessin, mais à structure symétrique, le transistor asymétrique selon l'invention a une tension de claquage améliorée de 50 %, et une transconductance améliorée de 30 %. Compared to a transistor of the same design, but with a symmetrical structure, the asymmetric transistor according to the invention has an improved breakdown voltage of 50%, and an improved transconductance of 30%.
Le procédé décrit s'adapte de façon évidente pour l'homme de l'art à d'autres types de transistors dont la nature des matériaux, le nombre de couches semiconductrices, la fréquence de fonctionnement ou les dimensions seraient différentes de celles qui ont été citées pour exposer l'invention. The method described is obviously suitable for those skilled in the art to other types of transistors of which the nature of the materials, the number of semiconductor layers, the operating frequency or the dimensions would be different from those which have been used. cited to expose the invention.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8910829A FR2650915A1 (en) | 1989-08-11 | 1989-08-11 | Field-effect transistor and method of producing it |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8910829A FR2650915A1 (en) | 1989-08-11 | 1989-08-11 | Field-effect transistor and method of producing it |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2650915A1 true FR2650915A1 (en) | 1991-02-15 |
Family
ID=9384668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR8910829A Pending FR2650915A1 (en) | 1989-08-11 | 1989-08-11 | Field-effect transistor and method of producing it |
Country Status (1)
| Country | Link |
|---|---|
| FR (1) | FR2650915A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112269277A (en) * | 2020-10-09 | 2021-01-26 | 三明学院 | Electro-optical modulator based on stress silicon and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4191963A (en) * | 1978-11-21 | 1980-03-04 | Instituto Venezolano De Investigaciones Cientificas (Ivic) | Built-in notched channel MOS-FET triodes for high frequency application |
| EP0275905A2 (en) * | 1987-01-20 | 1988-07-27 | International Standard Electric Corporation | A self-aligned field effect transistor including method |
| JPS63198375A (en) * | 1987-02-13 | 1988-08-17 | Nec Corp | Mes-type fet device |
-
1989
- 1989-08-11 FR FR8910829A patent/FR2650915A1/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4191963A (en) * | 1978-11-21 | 1980-03-04 | Instituto Venezolano De Investigaciones Cientificas (Ivic) | Built-in notched channel MOS-FET triodes for high frequency application |
| EP0275905A2 (en) * | 1987-01-20 | 1988-07-27 | International Standard Electric Corporation | A self-aligned field effect transistor including method |
| JPS63198375A (en) * | 1987-02-13 | 1988-08-17 | Nec Corp | Mes-type fet device |
Non-Patent Citations (3)
| Title |
|---|
| 1987 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, Las Vegas, Nevada, 9-11 juin 1987, pages 161-163, IEEE, New York, US; K.G. WANG et al.: "State-of-the-art ion-implanted low-noise GaAs MESFET and monolithic amplifier" * |
| PATENT ABSTRACTS OF JAPAN, vol. 12, no. 481 (E-694)[3328], 15 décembre 1988; & JP-A-63 198 375 (NEC CORP.) 17-08-1988 * |
| SOLID-STATE ELECTRONICS, vol. 24, no. 5, mai 1981, pages 435-443, Port Washington, New York, US; S. TARASEWICZ et al.: "A high voltage UMOS transistor" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112269277A (en) * | 2020-10-09 | 2021-01-26 | 三明学院 | Electro-optical modulator based on stress silicon and preparation method thereof |
| CN112269277B (en) * | 2020-10-09 | 2024-03-22 | 厦门兴华鼎自动化技术有限公司 | Electro-optic modulator based on stress silicon and preparation method thereof |
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