JPS63193642A - Receiving circuit for serial data - Google Patents

Abstract

PURPOSE:To detect the speed of unknown serial data and to accurately convert the succeeding serial data into parallel data by comparing the pattern of parallel data with a reference pattern, determining a data speed and controlling timing. CONSTITUTION:When sample data consisting of 8 bits including one bit out of stop bits from serial data sd inputted at a reading speed corresponding to 8 times the maximum data speed of expected serial data are accumulated in a shift register 2 through a latch 1, a timing control part 4 is set up through a control register 6 so that parallel data are sent to a latch 3. When the data sd are inputted at the maximum speed, the control part 4 fetches the data into the register 2 by detecting a start/stop bit and sends the data to the latch 3. A data comparing part 8 reads the parallel data pd outputted from the latch 3 and compares the data pd with the internal reference pattern. Then, the comparing part 8 sets up the timing of the control part 4 through a register 6.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a serial data receiving circuit, and particularly to a serial data receiving circuit of an asynchronous type in which each serial data has a start bit and a stop bit. This invention relates to a circuit that detects speed.

[Conventional technology]

Conventionally, as shown in FIG. 4, a data rate detection circuit in this type of receiving circuit detects input asynchronous serial data sd at a rate sufficiently faster than the data rate, for example, 3.
Latch part 1 is sampled with a clock that is more than twice the speed.
1 and reading the output of this latch section 11, the waveform of the input serial data sd is known, and the speed of the serial data sd is detected from this. Note that 15 in FIG. 4 is a clock generation section, and 20 is a serial data speed detection section.

(Problems to be Solved by the Invention) The conventional serial data rate detection circuit described above has a drawback that it is necessary to separately provide a circuit for converting asynchronous serial data into parallel data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a serial data receiving circuit capable of detecting an unknown serial data rate and converting subsequent serial data into parallel data.

[Means for solving problems]

The receiving circuit of the present invention is a receiving circuit that receives and processes serial data in which a start bit is followed by 7 bits of data and has a stop bit after that, and sends out at least 7 bits of parallel data. is detected, the shift register stores the 7-bit data at a read speed eight times the expected maximum data rate of the serial data, converts the data into parallel data, and sends it out; data patterns and
The present invention is characterized by comprising a data comparison section that compares the data rate with a standard pattern for data rate detection registered in advance.

[Effect]

Therefore, the present invention determines the data rate by comparison with a standard pattern, detects the rate of unknown serial data, and accurately converts the subsequent serial data to parallel data without controlling the timing. Can be done.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment according to the present invention. As shown in FIG. 1, the latch unit 1 takes in asynchronous serial data sd using the high-speed sampling clock SC from the timing control unit 4, and transfers it to the shift register 2.
It is connected to send out to.

The shift register 2 is connected to read sampled serial data at a certain speed, convert it into parallel data pd, and send the output to the data latch unit 3. The output of the data latch section 3 is connected to be input to a data comparison section 8 via a data bus 7.

The timing control section 4 is connected to the latch section 1, the output terminal of the latch section 1, the shift register 2, and the data latch section 3, respectively, in order to control timing. Further, the timing control section 4 is connected to the data comparison section 8 via a control register 6 and a data bus 7 in order to convert control information between the timing control section 4 and the data comparison section 8 . It is connected to the control register 6.

In other words, the embodiment of FIG. 1 includes a latch section 1 for sampling and holding input serial data sd at high speed, and a latch section 1 for accumulating the sampled serial data at a certain speed and converting it into parallel data pd. shift register 2,
a data latch section 3 for holding and outputting the parallel data pd; a timing control section 4 for generating a sampling clock SC, controlling the shift register 2, and detecting an asynchronous start bit and a stop bit; ,
A clock generation section 5 that generates a reference clock, a data comparison section 8 that reads parallel data pd from the data latch section 3 and compares it with a registered standard pattern, a timing control section 4, and a data comparison section 8. It has a control register 6 for exchanging control information between the two.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. First, the latch section 1 samples input serial data sd using the high-speed sampling clock SC from the timing control section 4, and holds the sampled serial data.

When the timing control unit 4 monitors the output of the latch unit 1 and detects a start bit, it controls the shift register 2 so that the output of the latch unit 1 is taken into the shift register 2 at predetermined time intervals, which will be described later. do.

When the shift register 2 has finished loading a predetermined number of sampled serial data, the timing control unit 4
The output of each bit of shift register 2 is simultaneously
The data is sent to the data latch section 3 for output. The parallel data pd taken into the data latch unit 3 is sent to the data comparison unit 8 via the data bus 7.

The control register 6 is connected to the data comparison section 8 via the data bus 7, so that the timing control section 4 and the clock generation section 5 can be controlled from the data comparison section 8. Note that the predetermined number of bits is
The data comparison unit 8 is notified via the control register 6 of the fact that the stop bit has been taken in and sent to the data latch unit 3 and the polarity of the detected stop bit.

When the data speed of the serial data sd that is now input is known, the parallel data pd that has been converted and input to the data latch section 3 by the above-mentioned procedure is accurately parallel data p.
It is output as d.

On the other hand, if the data rate of the input serial data sd is unknown and is an integral multiple of a certain rate, the data rate of the serial data sd can be detected by the following procedure.

First, for example, input serial data sd is transferred to the shift register 2 as 8-bit data including 1 stop bit at a reading speed 8 times higher than the expected highest data rate of serial data. , the timing control section 4 is set via the control register 6 so that the parallel data pd is sent to the data latch section 3 when the sampled serial data is accumulated.

When the current input serial data sd is at the highest expected data rate, the start bit ST has the ``O'' polarity and the following O-th bit Bo has the ``1'' polarity, as shown in A in Figure 2. If we assume that
The timing control unit 4 detects the time point indicated by the arrow T in FIG. Each bit output of the shift register 2 is detected as a bit and sent to the data latch unit 3.
send to At the same time, the timing control section 4 notifies the data comparison section 8 through the control register 6 that the output parallel data pd has been sent to the data latch section 3 . At this time, the data latch unit 3 has the data 7 which is the time point b o ”-b 6.
Bit “OII” parallel data pd will be input.

Note that in this case, the stop bit P is
Not sent to.

If the input serial data sd has the highest data rate ″″″
If the data rate is slower than 172 in FIG. 2A, as in B in FIG. After sending the serial data to the data latch unit 3, the second T
From the point of arrow 2, the read serial data of 7 bits (times bo to be) is taken into shift register 2, and
At the time when the second stop bit P2 is detected, the second parallel data pd of 7 bits is sent to the data latch unit 3.

The data comparison section 8 reads parallel data pd output from the data latch section 3 via the data bus 7. In the data comparison section 8, bit patterns of parallel data pd corresponding to all expected data speeds of serial data are registered in advance, and these standard patterns and the parallel data pd outputted to the data latch section 3 are registered. By comparing, it is possible to know the data rate of the input serial data sd.

After the input data rate is known, the data comparison unit 8
By setting the timing control unit 4 through the control register 6 and changing the data rate to the data rate determined by the data comparison unit 8, the asynchronous serial data sd is input to IT at the known data rate. You can input
The data latch section 3 can output correctly converted parallel data pd.

Note that the data speed of the input serial data sd is an integral multiple of a certain speed, and the setting of the timing control unit 4 is such that the input serial data sd is transferred to the shift register 2 at a reading speed of 8 times the expected data speed. , set to store the 8 bits (time points bo to b6.P) including 1 bit of stop bit P in the shift register 2, and set to send each bit of parallel data pd to the data latch unit 3. , whether the input serial data sd has continuous "0" polarity as shown in Figure 2B, or has ii 1 ++ polarity in the middle as shown in Figure 2C. , depending on the polarity of the detected stop bit P, it is possible to distinguish only from the first output parallel data pd, and it is necessary to wait for the next parallel data pd.In addition, if the above settings are made, the result shown in FIG. 2B.

As shown in C, even if a long "0" polarity input continues, there is a "1" polarity part in the middle, and stop bits P and P2 of "1" polarity are detected there, so the second Diagram C
As shown in FIG. 2, the detection timing of the next start bit T2 can be ensured.

If the human-powered serial data sd exceeds the expected maximum data rate, the result will be as shown in FIG. In other words, the timing control unit 4 detects the time indicated by the arrow ■ as the start, and sends the contents bo-be of the shift register 2 to the data latch unit 3 at the time indicated by the arrow P, but at this time, the first bit B1 has already been Since input has started,
The detection of the start bit ST of the serial data sd will be delayed to the first bit B1.

On the other hand, in the case of FIG. 2C, the input serial data sd
is detected and input to the shift register 2 via the timing control unit 4 every 9 bits from the bit at time 1 to the bit at time P, so that -α' - 111' polarity becomes '1' polarity. Since it is detected as
The OI+ polarity bit (the bit at time T2) is always detected and will not lag.

〔Effect of the invention〕

As explained above, the present invention can determine the data rate of serial data by comparing it with a standard pattern and control the timing, so it can detect the data rate of unknown serial data and parallelize the detected serial data. There are effects that can be converted into data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
FIG. 3 and FIG. 3 are explanatory diagrams showing the same operation as above, and FIG. 4 is a block diagram showing a conventional example. 1... Latch section, 2... Shift register,
3... Data latch section, 4... Timing control section,
5... Clock generation section, 6... Control register, 7.
...Data bus, 8...Data comparison section, sd...
・Serial data, pd...parallel data, SC...
sampling clock. -, :,, Near 12 - Figure 3 Figure 4

Claims (1)

[Scope of Claims] A receiving circuit that receives and processes serial data in which a start bit is followed by 7 bits of data and has a stop bit after that, and sends out at least 7 bits of parallel data, comprising: a shift register that, when detected, stores the 7-bit data at a read speed eight times the expected maximum data rate of the serial data, and converts the data into parallel data and sends it out; 1. A serial data receiving circuit comprising: a data comparison section that compares the pattern of the above data with a standard pattern for data rate detection registered in advance.