JPH04178565A - Peak value detecting circuit - Google Patents

Abstract

PURPOSE:To perform real-time processing and detect a peak value precisely at a high speed by setting the input state of the next digital data when the data of the peak value are latched. CONSTITUTION:An analog signal is fed to a high-speed A/D converter 10 and digitized by the clock signal CK from a generating circuit 26 and fed to a latch circuit 12 and comparing circuits 18, 20, 22. When it is detected that the converted output data are changed to the preset threshold value VS or above, a leading edge detection signal ST is generated. When it is detected that the output data are changed to the preset threshold value VE or below, a trailing edge detection signal SE is generated. When the converted output data are larger than the data in the circuit 12, the converted output data are newly held, the held data are held by a latch circuit 14 and stored in a memory circuit 16. The latchable state is set in the circuit 12 synchronously with the generation timing of the signal ST, a latch action is performed by the circuit 14 synchronously with the generation timing of the signal SE, and a memory action is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak value detection circuit that converts the peak value of an analog signal into digital data and detects it.

[Prior Art] Conventionally, a peak value detection circuit having a configuration shown in FIG. 3 is known. In the figure, an analog peak hold circuit 2 detects the peak value of an analog signal S IN whose amplitude changes with the passage of time and holds it for a predetermined period of time. If the data is converted into digital data by a storage device such as a semiconductor memory,
6 are stored sequentially. Further, the timing signal generation circuit 8
A timing signal for controlling the operations of the analog peak hold circuit 2, A/D converter 4, and storage device 6 is generated.

Next, to explain the operation with reference to FIG. 4, at time t1 when the amplitude of the signal SIN exceeds a preset threshold level VTR, the timing signal generation circuit 8 internally changes the logic signal S1 from "L" to "H". At time t2 when the level is inverted and the amplitude of the signal S1 drops below the threshold level VTR, the logic signal S
2 is inverted from "L" to "H" level.

Furthermore, the logic signal S1 is inverted to the "H" level after a predetermined delay time has elapsed in synchronization with the time when the logic signal S1 is inverted to the "H" level, and the logic signal S2 is inverted to the "H" level and is inverted to the "H" level. After the delay time elapses, a synchronizing signal S4 is inverted to "L" level, and the A/D converter 4 is caused to perform the conversion process at the timing when the synchronizing signal S4 becomes "H" level, and the storage device 6 is Store data. When this storage is completed, the holding operation of the analog peak hold circuit 2 is reset to enable the next peak hold process.

Then, by performing such a series of processing on the analog signal, the peak value of the analog signal is detected as digital data.

In addition, as another control method, the timing signal generation circuit 8 outputs "L" after a predetermined delay time in synchronization with the signal S2.
A synchronizing signal S3 that is inverted from "H" level to "H" level is formed, and when this synchronizing signal S3 becomes "H" level, the A/D converter 4 starts the conversion operation, and the data is stored in the storage device 6. When this storage process is completed, the holding operation of the analog peak hold circuit 2 is reset.

Then, by performing such a series of processing on the analog signal, the peak value of the analog signal is detected as digital data.

[Problems to be Solved by the Invention] However, in such a conventional peak value detection circuit, when digital conversion is performed by an A/D converter in synchronization with the synchronization signal S4 in FIG. This attempts to process the peak value held by the peak hold circuit under the best conditions, but there is a problem in that the circuit configuration such as the timing signal generation circuit becomes complicated. In addition, since there is a delay time until the analog peak hold circuit is reset after the storage device stores digital data, dead time (time when input signals cannot be processed) is generated before moving to the next process. However, there was a problem in that the detection accuracy deteriorated.

On the other hand, when digital conversion is performed using an A/D converter in synchronization with the synchronization signal S shown in Fig. 4, a voltage drop in the analog beak holder occurs before the digital conversion starts, which reduces detection accuracy. Therefore, the drop in the voltage value of this analog peak holder becomes larger than when control is performed in synchronization with the synchronization signal S4.

Also, without using an analog peak hold circuit, the input analog signal is subdivided into extremely short predetermined cycles, and at the same time, it is directly converted into digital data using a high-speed A/D converter.
There is also a known method in which all the digital data is stored in a storage device, and finally, all the digital data is read out from the storage device by an arithmetic device such as a microcomputer, and the peak value is detected by determining the maximum value. However, it requires an extremely large capacity storage device, and
There was a problem that could not be processed in real time.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a peak value detection circuit that performs processing in real time and is fast and accurate.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a peak value detection circuit that converts the peak value of an analog signal into digital data and detects the peak value. An A/D converter that converts directly into digital data, and an A/D converter that converts directly into digital data.
a detection means that generates a rising detection signal when detecting when the output data of the D converter changes to a predetermined threshold value or more, and generates a falling detection signal when detecting when the output data changes to a predetermined threshold value or less; The first to latch the data
The latch means compares the held data held by the first latch means with the output data, and when it is detected that the output data is larger than the held data, the output data is newly held in the first latch means. a second latch means for further holding the data held in the first latch means, a storage means for storing the data held in the second latch means, and the detection means detects The first latch means is set to a latchable state in synchronization with the generation of the rising detection signal, and the second latch means is caused to perform a latch operation in synchronization with the generation of the falling detection signal, and and timing signal generation means for causing the storage means to perform a storage operation.

[Operation] According to the peak value detection circuit of the present invention having such a configuration, at the time when the peak value data is latched in the second latch circuit, the first latch circuit receives the data from the A/D converter 10. Since the state is set such that the next digital data can be input, there is no dead time as in the conventional case.

In addition, since all digital data is not stored in the storage means, it is possible to prevent the overall size of the circuit from increasing in size and price due to an increase in storage capacity, and furthermore, it is possible to realize peak value detection in real time. .

[Embodiment] Hereinafter, an embodiment of the peak value detection circuit according to the present invention will be described with reference to the drawings.

First, the configuration will be explained based on FIG. 1. The high-speed A/D converter 10 directly inputs the analog signal 5IN(1), and synchronizes it with the clock signal CK of a predetermined frequency supplied from the clock signal generation circuit 26. Digital data D (nT)
Convert and output. That is, the high-speed A/D converter 10 is
Conventionally, there is no method of sampling with a common sample-hold circuit and converting it into digital data during the holding period, but directly converting the analog signal 5IN(1) to digital data D(n
Convert to T).

Incidentally, for convenience of explanation, digital data output in time series for each period T of the clock signal CK is indicated by D (nT).

This digital data D (nT) is supplied to the first latch circuit 12, the first comparison circuit 18, the second comparison circuit 20, and the third comparison circuit 22.

The first comparison circuit 18 receives the input digital data D (
nT) and the digital data D held in the first latch circuit 12, D (nT)
> When the relationship D is detected, the first latch circuit 12
Strobe pulse signal S for holding (nT)
generate p. Therefore, the first latch circuit 12 is
Each time the strobe pulse signal Sp is supplied, the data D is changed to the maximum digital value and held.

As shown in FIG. 4, the second comparison circuit 20 compares the digital data D (nT) with a preset threshold value Vs, detects a time point t when D (nT)≧V+, and
A rising signal ST indicating that point is output to the timing signal generating circuit 2-4.

As shown in FIG. 4, the third comparison circuit 22 compares the digital data D (nT) with a preset threshold value V6, detects a time point t2 at which D (nT)≦V, and
A falling signal S1 indicating that point is output to the timing signal generation circuit 24.

The timing signal generation circuit 24 generates the clear signal CL at the same time as the signal SA is transferred from the second comparison circuit 20.
is supplied to the first latch circuit 12, and the first latch circuit 1
2 latch operation is enabled. That is, while the first latch circuit 12 is set to be capable of latch operation, the above-mentioned D
(nT) > D, the first comparator circuit 1
The first latch circuit 12 latches the digital data D (nT) in synchronization with the signal Sp of 8.

Further, the timing signal generation circuit 24 is connected to the third comparison circuit 2
At the same time as the signal S5 is transferred from the second latch circuit 2, a strobe signal S is generated to cause the second latch circuit 14 to latch the data D held by the first latch circuit 12. Further, an enable signal S synchronized with the strobe signal S.
By supplying the data D to the storage circuit 16, the data D latched by the second latch circuit 14 is stored in the storage circuit 16.

Note that the signal CL generated by the timing signal generation circuit 24,
S, and S. is formed in synchronization with the clock signal CK output from the clock signal generation circuit 26.

According to the peak value detection circuit having such a configuration, at the time when the peak value data D is latched in the second latch circuit 14, the first latch circuit 12 detects the next data from the A/D converter 10. Since the state is set such that digital data D (nT) can be input, there is no dead time as in the conventional case.

Furthermore, since not all digital data is stored in the storage circuit 16, it is possible to prevent the overall size of the device from increasing in size and price due to an increase in storage capacity, and furthermore, it is possible to realize peak value detection in real time. can.

Further, an at-one (add) which adds 1 to the digital data D input to the memory circuit 16 to generate address data
one) circuit and stores the digital data D in the memory area specified by the address data, there is no dead time, so a high-speed pulse-hide analyzer with no missing counts can be realized, and an excellent signal Can contribute to the development of processing equipment.

[Effects of the Invention] As explained above, according to the present invention, at the time when the peak value data is latched in the second latch circuit, the first latch circuit receives the next digital signal from the A/D converter 10. Since it is set in a state where data can be input, there is no dead time as in the conventional case, and detection accuracy can be improved.

In addition, since all digital data is not stored in the storage means, it is possible to prevent the overall size of the circuit from increasing in size and price due to an increase in storage capacity, and furthermore, it is possible to realize peak value detection in real time. .

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration of one embodiment of the peak value detection circuit of the present invention; Fig. 2 is an explanatory diagram for explaining the operation of the embodiment; Fig. 3 is an explanatory diagram of the configuration of a conventional example; FIG. 2 is an explanatory diagram for explaining the operation of a conventional example. Explanation of symbols; 10: A/D converter 12: First latch circuit 14: Second latch circuit 16: Memory circuit 18: First comparison circuit 20: Second comparison circuit 22: Third comparison circuit 24: Timing signal generation circuit 26: Clock signal generation circuit Patent applicant: Tokimec Co., Ltd.

Claims (1)

[Claims] (1) In a peak value detection circuit that converts the peak value of an analog signal into digital data and detects it, an A/
When it is detected that the output data of the D converter and the A/D converter changes to a predetermined threshold value (V_S) or more, a rising detection signal (S_T) is generated.
a detection means that generates a falling detection signal (S_E) when detecting when the output data changes to a predetermined threshold value (V_E) or less; a first latch means that latches the output data;
means for comparing the held data held by the latch means with the output data, and when detecting that the output data is larger than the held data, causing the first latch means to newly hold the output data; a second latch means for further holding the data held in the latch means; a storage means for storing the data held in the second latch means; and generation of a rising detection signal (S_T) detected by the detection means. The first latch means is set to a latchable state in synchronization with the time point, and the second latch means is caused to perform a latch operation in synchronization with the generation time of the falling detection signal (S_E), and the storage means A peak detection circuit comprising a timing signal generating means for causing a memory operation to be performed.