JP2003271413A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily obtain information for reproducing an operation inside a semiconductor integrated circuit on a simulation. <P>SOLUTION: An initial value holding means (initial value holding F/F128) for holding contents of an internal register is provided, the holding contents are parallel/serial converted, the converted data is outputted to the outside of the semiconductor integrated circuit. A PLL 125 is provided to multiply an input clock from the outside of the semiconductor integrated circuit. By using a clock generated in the PLL 125, the processing speed is made high. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for simulating internal operation.

[0002]

2. Description of the Related Art In the development of a conventional semiconductor integrated circuit, various inputs are given to the semiconductor integrated circuit by simulation, an output signal from the semiconductor integrated circuit is compared with an expected output value, and the expected operation is performed. After verifying that the actual device is manufactured. In this process, if the output does not meet the expected value, the simulation proceeds with the analysis while referring to the internal operation of the semiconductor integrated circuit.

However, when an unexpected operation occurs in a real device, it is not so easy to proceed in this way. This is because it is difficult to grasp the operation inside the semiconductor integrated circuit. As a technique related to this, there is Japanese Patent Laid-Open No. 2001-195278, "Large-scale integrated circuit". This is because the internal state analysis unit is mounted inside the semiconductor integrated circuit, and the detection circuit provided inside the internal state analysis unit performs state detection determination based on the internal state transition information stored in the memory, and the determination result Is output.

[0004]

In the above prior art, a dedicated internal state analysis unit must be mounted inside the semiconductor integrated circuit, and a simulator is used to analyze the cause efficiently. However, there was a problem that this could not be realized.

The present invention has been made to solve the above problems, and an object thereof is to make it possible to easily obtain information for reproducing the operation inside a semiconductor integrated circuit on a simulation.

[0006]

To achieve the above object, in a semiconductor integrated circuit according to the present invention, an initial value holding means for holding the contents of an internal register and a holding content of the initial value holding means are provided. A first conversion output unit for performing parallel / serial conversion and outputting the converted data to the outside of the semiconductor integrated circuit is provided.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, 101
Shows a circuit model inside the package of the semiconductor integrated circuit. 102 is a bidirectional terminal for inputting a bidirectional data signal, and 103 to 105 are input terminals for inputting an input data signal. Reference numeral 106 is a CLK (clock) input terminal. 107-A is an output buffer with OE control,
107-B is an input buffer, and 108-111 are input buffers.

Reference numeral 112 denotes an input F / F, and the signal input from the input terminal is sampled here at each falling edge of the CLK signal. Reference numeral 113 represents a combinational circuit portion as a model. In this semiconductor integrated circuit,
The logic circuits other than the F / F are combinational circuits. 114
Is an internal F / F, and 115 is a combinational circuit.
Reference numeral 116 denotes an output F / F, and this F / F output is output to the outside of the semiconductor integrated circuit via the output buffer. 11
Reference numerals 7 and 118 denote output buffers. 119 and 120 are output terminals. The above is the configuration of a general semiconductor integrated circuit.

Reference numeral 121 is a control input terminal for controlling the output of the internal F / F contents to the outside of the semiconductor integrated circuit, and the input buffer for this is the input buffer 122. 12
3 is 1 for the START signal input from the input terminal 121
F for creating signal (START_d1) delayed by CLK
/ F. Further, the F / F for creating a signal (START_d2) delayed by 1 CLK is F / F12.
It is 4. Reference numeral 125 is a PLL that generates a signal (X4CLK) having a frequency four times as high as the CLK signal. A counter 126 counts up while EN is at a high level. A selector 127 selects and outputs the output of the input F / F 112 according to the count output value of the counter 126.

Reference numeral 128 denotes an initial value holding F / F, which loads input data while the LD terminal is at the low level and holds the output value when the LD terminal becomes the high level. 12
A selector 9 selects and outputs the output value of the initial value holding F / F 128 according to the count output value of the counter 126. A selector 130 selects and outputs either the value selected by the selector 129 or the value selected by the selector 127. Reference numeral 131 is a selector, which outputs F
The output value of / F116 is selectively output according to the count output value of the counter 126. This output is X by F / F132
It is sampled every 4 CLK and is output from the output terminal 134 via the output buffer 133. 135 is F / F
That is, the output of the selector 130 is sampled for each X4CLK, and the output terminal 136 is sampled via the output buffer 136.
Output from 7.

FIG. 2 is a timing chart for explaining the operation of FIG. Here, CLK1 to CLK
It shows about 5 CLK up to 5. In addition, PLL125
Therefore, a clock of four times the frequency of this CLK (X4CL
Since K) is generated, 1 CLK will be described by dividing it into four P1 to P4.

In FIG. 2, "DIN" collectively indicates the 4-bit signals given to the input terminals 102 to 105 in FIG. 1, and K in CLK1.
1 and CLK2 are given as K2. “DOUT” collectively shows the contents of the output terminals 119 and 120 and the contents of the bidirectional terminal 102. “Input F / F output” indicates the output of the input F / F 112. “START” indicates a signal given to the input terminal 121. "START_d1" is the output signal of the F / F123, "S
TART_d2 ″ is the output signal of the F / F 124.

“Initial value holding F / F output” indicates the output value of the initial value holding F / F 128. "X4CLK" indicates a clock multiplied by 4 in the PLL. "TOUT2" and "TOUT1" are output terminals 1 respectively
34 and 137 are shown.

In FIG. 2, at CLK1, "ST
"ART" is at high level.
START_d1 becomes high level from CLK2 delayed by LK, and STAR_d1 from CLK3 delayed by 1 CLK.
T_d2 becomes high level. Since START_d1 is connected to the EN terminal of the counter 126, C of FIG.
As shown in [1: 0], the count-up operation is performed at the rising edge of X4CLK for detecting the high level of START_d1.

On the other hand, START_d2 is an initial value holding F
Since it is connected to the terminal of / F128, the output value is maintained during the rising edge of CLK which detects the high level of / F128. START_d1 is the S of the selector 130.
It is connected to EL. The selector 130 has an IN1 side when the SEL input is at a high level and an IN1 side when the SEL input is at a low level.
Select the 0 side. This result is 1X4 in F / F135
Since it is output to the output terminal of TOUT2137 with a delay of CLK, as shown in FIG. 2, the contents of the DIN input when START is set to the high level, the contents of the DIN input becomes START_d1 to the high level, and after the delay of 1X4CLK, X4C
It starts to be output as serial data for each LK.

Then, from the time when START_d2 becomes low level and it is delayed by 1X4CLK, the internal F at the next CLK which makes START high level every X4CLK.
/ F114 outputs and the contents start to be output as serial data. "TOUT1" outputs the output of the output F / F 116 as serial data every X4CLK.
Therefore, the contents of TOUT1 and TOUT2 are recorded outside the semiconductor integrated circuit at a clock that is four times CLK, and by appropriately simulating this information and the circuit information of the semiconductor integrated circuit on a computer, the semiconductor It is possible to grasp the internal operation of the integrated circuit.

[0017]

According to the invention of claim 1, there is provided an initial value holding means for holding the contents of the internal register, and the contents held by the initial value holding means are parallel / serial converted and output to the outside of the semiconductor integrated circuit. As a result, the value of the internal register at any point can be acquired from the outside. Therefore, the input signal given to the semiconductor integrated circuit is separately acquired from the arbitrary time point, and by combining these, the semiconductor integrated circuit can be obtained without acquiring all the input signals to the semiconductor integrated circuit after the power is turned on. It is possible to prepare all the information for reproducing the internal operation on the simulation.

According to the invention of claim 2, in addition to claim 1, a semiconductor integrated circuit has a PLL for multiplying an input clock from the outside, and a parallel / serial conversion is performed using this PLL output signal. Since the generated data is output to the outside of the semiconductor integrated circuit, it is not necessary to supply a high-speed clock to the semiconductor integrated circuit.

According to a third aspect of the present invention, in addition to the first aspect, there is provided means for performing parallel / serial conversion of data contents input into the semiconductor integrated circuit, and the serial / parallel converted data is output to the outside of the semiconductor integrated circuit. Therefore, the adverse effect of connecting a signal other than the original signal to the input terminal of the semiconductor integrated circuit does not occur.

According to the invention of claim 4, in addition to claim 1, there is provided means for parallel / serial converting the data contents output from the semiconductor integrated circuit, and the serial / parallel converted data is output to the outside of the semiconductor integrated circuit. Therefore, the adverse effect of connecting a signal other than the original signal to the output terminal of the semiconductor integrated circuit does not occur.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit according to the embodiment of the present invention.

[Explanation of symbols]

112 Input F / F 116 Output F / F 121 Control input terminal 122 input buffer 123, 124, 132 F / F 125 PLL 126 counter 127, 129, 130, 131 selectors 128 Initial value hold F / F 133 output buffer 134 output terminals 135 F / F 136 output buffer 137 output terminal

Claims (4)

[Claims] 1. In a semiconductor integrated circuit, initial value holding means for holding the contents of an internal register, parallel / serial conversion of the contents held by said initial value holding means, and the converted data is output to the outside of the semiconductor integrated circuit. A semiconductor integrated circuit comprising: first conversion output means. 2. A PLL for multiplying an input clock from the outside of the semiconductor integrated circuit is provided, and the first conversion output means uses the clock generated by the PLL,
2. The semiconductor integrated circuit according to claim 1, wherein parallel / serial conversion is performed and the converted data is output to the outside of the semiconductor integrated circuit. 3. A second conversion output unit for parallel / serial converting the data content input to the semiconductor integrated circuit and outputting the converted data to the outside of the semiconductor integrated circuit. The semiconductor integrated circuit described. 4. The third conversion output means for parallel / serial converting the data content output from the semiconductor integrated circuit and outputting the converted data to the outside of the semiconductor integrated circuit. Semiconductor integrated circuit.