JPS63193569A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS63193569A JPS63193569A JP2607687A JP2607687A JPS63193569A JP S63193569 A JPS63193569 A JP S63193569A JP 2607687 A JP2607687 A JP 2607687A JP 2607687 A JP2607687 A JP 2607687A JP S63193569 A JPS63193569 A JP S63193569A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- layer
- transistor
- polysilicon layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000010453 quartz Substances 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 7
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 34
- 239000010408 film Substances 0.000 abstract description 26
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 5
- 229910052787 antimony Inorganic materials 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は絶縁基板上に形成したＭ ＯＳ型トランジスタ
において、活性層となる半導体層の下に絶縁層を有した
導電体層を形成した薄膜トランジスタに関する６
〔従来技術〕
完全密着型イメージセンサ−用駆動回路、液晶ディスプ
レイの駆動回路、エレクトロルミネッセンス（ＥＬ）駆
動用回路等に使用される薄膜トランジスタ（ＴＰＴ）は
、従来、絶縁基板上に直接形成されるものであった。す
なわち、石英等の絶縁基板上にポリシリコン等の半導体
膜からなる活性層を形成し、この活性層上にゲート酸化
膜およびゲート電極を形成し、これらの上に層間絶縁膜
を形成した後、コンタクトホールを穿ち、金属電極を形
成して得られるものである。このような従来のＴＰＴで
はチャンネルとなる活性層が絶縁基板上に直接形成され
るために、活性層が浮いている状態となるため、ＴＰＴ
がＭＯ８型Ｆ’ＥＴである場合にスレッショルド電圧が
、シリコンウェハー上にＭＯ５型ＦＥＴを形成する場合
とは異なり、不安定になり、従って前述の如き駆動回路
における動作不安定を生ずるという問題点を有するもの
であった。Detailed Description of the Invention [Technical Field] The present invention relates to a thin film transistor formed on an insulating substrate, in which a conductive layer having an insulating layer is formed under a semiconductor layer serving as an active layer. Conventional technology Thin film transistors (TPTs) used in drive circuits for fully contact image sensors, drive circuits for liquid crystal displays, electroluminescence (EL) drive circuits, etc. have conventionally been formed directly on insulating substrates. there were. That is, after forming an active layer made of a semiconductor film such as polysilicon on an insulating substrate such as quartz, forming a gate oxide film and a gate electrode on this active layer, and forming an interlayer insulating film on these, It is obtained by drilling contact holes and forming metal electrodes. In such conventional TPT, the active layer that becomes the channel is formed directly on the insulating substrate, so the active layer is in a floating state.
When the F'ET is an MO8 type F'ET, the threshold voltage becomes unstable, unlike when an MO5 type FET is formed on a silicon wafer, which causes the problem of unstable operation in the drive circuit as described above. It was something that I had.
本発明は、ＭＯＳ型トランジスタを形成したＴＰＴにお
けるスレッショルド電圧を制御し、動作不安定を解消し
たＴＰＴを提供することを目的とするものである。An object of the present invention is to control the threshold voltage in a TPT in which a MOS transistor is formed, and to provide a TPT in which unstable operation is eliminated.
本発明は上記の如き課題を、ＴＰＴが形成されるべき絶
縁基板として１石英板と、その上のＰ、Ｂ、Ａｓ、Ｓｂ
等の不純物が高濃度に拡散さ九て低抵抗化されたポリシ
リコン層と、該層上の熱酸化法によって形成された絶縁
層とからなるものとすることによって達成するものであ
る。The present invention solves the above problems by using a quartz plate as an insulating substrate on which TPT is to be formed, and P, B, As, and Sb on the quartz plate.
This is achieved by forming a polysilicon layer in which resistance has been reduced by diffusing impurities at a high concentration, and an insulating layer formed by thermal oxidation on the polysilicon layer.
以下に本発明を図面を参照して説明する。The present invention will be explained below with reference to the drawings.
第１図は本発明に係るＴＰＴの一実施例を示すものであ
る。第１図において、石英板１上にはポリシリコン層２
が４０００〜６０００人の膜厚となるようにＬＰ−ＣＶ
Ｄ法により形成されている。FIG. 1 shows an embodiment of the TPT according to the present invention. In FIG. 1, a polysilicon layer 2 is placed on a quartz plate 1.
LP-CV so that the film thickness is 4,000 to 6,000 people.
It is formed by the D method.
このポリシリコンＮ２はＰＩ Ｂ、Ａｓ、ｓｂ等の不純
物が高濃度、例えばドーズ量として１０１９〜１０７″
１（、ｆｆ１） −’程度ドーピングされ１０−１〜１
０−３Ωロ程度に低抵抗化されている。このような低抵
抗化ポリシリコン層２上には熱酸化法によって形成され
たポリシリコン熱酸化膜からなる絶縁層３が２０００〜
３０００人の膜厚で形成されている。This polysilicon N2 has a high concentration of impurities such as PI B, As, sb, etc., for example, a dose of 1019 to 107''.
1(, ff1) -' doped to 10-1 to 1
The resistance has been reduced to about 0-3Ω. On such a low-resistance polysilicon layer 2, an insulating layer 3 made of a polysilicon thermal oxide film formed by a thermal oxidation method is formed with a thickness of 2000 to 2000.
It is formed with a film thickness of 3000 people.
上記のような石英板１、低抵抗化ポリシリコン層２およ
び絶縁層３が順次積層されたものを基板とし、この上に
、常法に従ってｎ−ａｈＭＯＳ型トランジスタあるいは
ｐ−ｃｈＭ。A substrate in which the quartz plate 1, low resistance polysilicon layer 2, and insulating layer 3 as described above are laminated in sequence is used as a substrate, and an n-ah MOS type transistor or a p-chM is formed on this substrate according to a conventional method.
Ｓ型トランジスタを形成する。これらトランジスタは第
１図に示されたように基板上に形成されたポリシリコン
活性Ｍ４、ゲート絶縁膜５、ゲート電極６、層間絶縁膜
７およびソース・ドレイン電極８によって構成される。Form an S-type transistor. These transistors are composed of a polysilicon active layer M4 formed on a substrate, a gate insulating film 5, a gate electrode 6, an interlayer insulating film 7, and source/drain electrodes 8, as shown in FIG.
以下に具体的な製造例を第２図に示した工程図に基づい
て説明する。A specific manufacturing example will be described below based on the process diagram shown in FIG. 2.
（イ）石英板１上に低抵抗化したポリシリコン層２を製
膜する。(a) A polysilicon layer 2 with reduced resistance is formed on the quartz plate 1.
ＬＰ−ＣＶＤ法
膜厚 ： ５０００人
ドーパント ：Ｐ、Ｂ・・・等
抵抗率 ： １０−１Ωロ
ドーズ量 ： １０” （ａｌ）−’（ロ）ポリシ
リコンを熱酸化し、熱酸化膜からなる絶縁Ｍ３を形成す
る。LP-CVD method Film thickness: 5000 Dopants: P, B...Equivalent resistivity: 10-1Ω Loading amount: 10''(al)-' (b) Polysilicon is thermally oxidized to form an insulation layer made of thermal oxide film. Form M3.
ｃｔｒｙ ｏｒ ｗｅｔ酸化
膜厚 ： ２０００人
（ハ）ポリシリコン（ｉｎｔｒｉｎｓｉｃ）を製膜し、
活性膜４を形成する。Ctry or wet oxide film thickness: 2000 people (c) Polysilicon (intrinsic) film is formed,
An active film 4 is formed.
ＬＰ−ＣＶＤ法 膜厚 ： ２０００人 次いでフォトリソ・パターニングする。LP-CVD method Film thickness: 2000 people Next, photolithography patterning is performed.
（ニ）ポリシリコンを熱酸化し、ゲート酸化膜５を形成
する。(d) Polysilicon is thermally oxidized to form gate oxide film 5.
ｄｒｙ ｏｒ ｗｅｔ酸化
膜厚 ：１０００人
ドープしたポリシリコンを製膜し、ゲート電極６を形成
する。Dry or wet oxide film thickness: A film of 1000 doped polysilicon is formed to form the gate electrode 6.
ＬＰ−ＣＶＤ法 膜厚 ： ２０００人 フォトリソ・パターニング（セルファライン）を行う。LP-CVD method Film thickness: 2000 people Perform photolithography patterning (Selfline).
次いで不純物を拡散し、ソースおよびドレインを形成す
る。Next, impurities are diffused to form a source and a drain.
（ホ）層間絶縁膜７をＣＶＤ法により形成する。(e) An interlayer insulating film 7 is formed by the CVD method.
ＬＴＯｏｒＨＴｏ法
膜厚 ： ５ｏｏｏ人
フォトリソ・パターニング、次いでシンターリングを施
す。LTO or HTo method film thickness: 500mm Photolithographic patterning, then sintering.
ここに第１図に示した如きＭＯＳ型トランジスタが得ら
れる。Here, a MOS type transistor as shown in FIG. 1 is obtained.
かくして得られるＴＰＴはチャネルとなる活性層の下に
バックゲートが形成されるため、スレッショルド電圧が
安定する。そしてバックゲートから活性層への不純物の
拡散はキャップ層としての絶縁層があるために起こらな
い。In the thus obtained TPT, the back gate is formed under the active layer serving as a channel, so that the threshold voltage is stabilized. Diffusion of impurities from the back gate to the active layer does not occur because of the presence of the insulating layer as a cap layer.
以上のような本発明によれば、絶縁基板から活性層まで
連続して形成でき、大面積化が可能であり、高濃度に不
純物を含んだバックゲートの存在によりスレッショルド
電圧を安定させ、歩留りを向上することができ、従って
各種の駆動回路の動作不安定を生ずることのないＴＰＴ
が得られるという効果を有する。According to the present invention as described above, the active layer can be formed continuously from the insulating substrate to the active layer, making it possible to increase the area, and the existence of the back gate containing a high concentration of impurities stabilizes the threshold voltage and improves the yield. TPT that can be improved and therefore does not cause unstable operation of various drive circuits.
This has the effect that the following can be obtained.
第１図は本発明に係るＴＰＴの一実施例を示す概略説明
図である。
第２図は第１図のＴＰＴを作製する場合の工程説明図で
ある。
１・・・石英板
２・・・低抵抗化ポリシリコン層
３・・・絶縁層 ４・・ポリシリコン活性層５
・・・ゲート絶縁膜 ６・・・ゲート電極７・・・層間
絶縁膜
８・・・ソース・ドレイン電極FIG. 1 is a schematic explanatory diagram showing an embodiment of the TPT according to the present invention. FIG. 2 is a process explanatory diagram for manufacturing the TPT shown in FIG. 1. 1... Quartz plate 2... Low resistance polysilicon layer 3... Insulating layer 4... Polysilicon active layer 5
...Gate insulating film 6...Gate electrode 7...Interlayer insulating film 8...Source/drain electrode
Claims (1)
トランジスタにおいて、基板が石英板上のＰ，Ｂ，Ａｓ
，Ｓｄ等の不純物が高濃度に拡散されて低抵抗化された
ポリシリコン層と、該層上の熱酸化法によって形成され
た絶縁層とからなることを特徴とする薄膜トランジスタ
。1. In a thin film transistor in which a MOS transistor is formed on an insulating substrate, the substrate is made of P, B, and As on a quartz plate.
A thin film transistor comprising a polysilicon layer in which impurities such as , Sd, etc. are diffused at a high concentration to reduce resistance, and an insulating layer formed by a thermal oxidation method on the polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2607687A JPS63193569A (en) | 1987-02-05 | 1987-02-05 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2607687A JPS63193569A (en) | 1987-02-05 | 1987-02-05 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63193569A true JPS63193569A (en) | 1988-08-10 |
Family
ID=12183557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2607687A Pending JPS63193569A (en) | 1987-02-05 | 1987-02-05 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63193569A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
-
1987
- 1987-02-05 JP JP2607687A patent/JPS63193569A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0519830B2 (en) | ||
| JPH05335573A (en) | Thin film semiconductor device | |
| JP2609619B2 (en) | Semiconductor device | |
| JP3287038B2 (en) | Liquid crystal display | |
| JPH10270578A (en) | Semiconductor device and manufacture thereof | |
| JPS63102264A (en) | Thin film semiconductor device | |
| JPH04279064A (en) | Display device | |
| JPS63193569A (en) | Thin film transistor | |
| JP2635542B2 (en) | Thin film transistor | |
| JP4076725B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS60225469A (en) | Mosfet on insulation substrate | |
| JPS63142851A (en) | Semiconductor device | |
| JPH0534837B2 (en) | ||
| JPH07159809A (en) | Liquid crystal display | |
| JPH04320378A (en) | Memory transistor | |
| JP2593641B2 (en) | Insulated gate field effect semiconductor device | |
| JPH0572555A (en) | Thin-film transistor | |
| JP2847745B2 (en) | Thin film transistor | |
| JPH1022506A (en) | Polysilicon thin film transistor and liq. crystal display | |
| JPS6159474A (en) | Thin film transistor | |
| JPS63205962A (en) | Mos type thin-film transistor | |
| JP2593640B2 (en) | Insulated gate field effect semiconductor device | |
| JPS63288067A (en) | Thin-film transistor | |
| JPH02102575A (en) | Semiconductor device | |
| JPH1154630A (en) | Semiconductor and fabrication thereof |