JPS63191980A - Semiconductor testing device - Google Patents

Abstract

PURPOSE:To measure a test execution time selectively with relatively simple constitution by generating a trigger signal under prescribed conditions of an application program for plural measurement modules and taking measurement of time according to it. CONSTITUTION:Start conditions for setting a desired time measurement section and stop condition data are loaded in a time measurement unit 4 from a CPU 3 before the application program is executed. Consequently, a trigger part 5 decides the prescribed conditions of the program executed by the CPU 3 and generates and applies the trigger signal TG to an AND gate 6. The gate 6 outputs a measurement clock CK according to the signal TG, and a counter part 7 counts it. Its time measurement result is read in the CPU 3 after the program execution and processed as required. Consequently, the execution times of the respective measurement modules are measured with the relatively simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor test device, and more particularly, to measurement of test execution time of a test-to-dye semiconductor device.

(Prior Art) As shown in FIG. 5, one type of semiconductor test equipment uses a calculation control unit 1 to control a plurality of measurement modules 21 to 2π according to an application program specific to a semiconductor device under test (hereinafter referred to as DIJT). Some devices are configured to control I.

By the way, in such semiconductor test equipment, the cost with respect to test time is important, so the DUT
There is a growing interest in specific test execution times, and there is an increasing demand for measurements of the test execution time for each DUT and the execution time of individual test routines.

However, conventional semiconductor test equipment does not have an effective means for measuring the execution time of such application programs.For example, if necessary, an in-circuit emulator and a time interval counter may be connected externally. A program signal line inside a semiconductor test device is monitored to measure a desired execution time.

(Problem to be solved by the invention) However, in this method of measuring the execution time of an application program by connecting a measurement device from outside, the internal state of the semiconductor test equipment that is being monitored is quite complicated. For this reason, accurate measurement of execution time is quite difficult not only for device users but also for device manufacturers.

The present invention has been made with attention to such problems, and its purpose is to realize a semiconductor test device that can selectively measure the execution time of any test based on an application program with a relatively simple configuration. There is a particular thing.

The present invention, which solves these problems, comprises: a calculation control section that controls a plurality of measurement modules according to a predetermined program according to a semiconductor device to be tested; A trigger unit that determines a predetermined condition of a program to be executed and generates a trigger signal, and a counter unit that measures time according to the trigger signal output from a part of this trigger and outputs the measurement result to the arithmetic control unit. It is characterized by having been established.

(Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as in FIG. 5 are given the same reference numerals. In FIG. 1, 3 is an arithmetic processing unit (hereinafter referred to as CPU) provided in the arithmetic control section 1, and 4 is a time measurement unit provided based on the present invention. Here, the time measurement unit 4 is placed under the control of the CPtJ3.

That is, the CPU 3 executes the application program and also controls the time measurement unit 4 in real time.

FIG. 2 is a block diagram showing the basic configuration of the time measurement unit 4. As shown in FIG. In FIG. 2, 5 is a trigger part;
A trigger signal TG is generated by determining a predetermined condition of an application program executed by the CPU 3 of the arithmetic control unit 1. This trigger signal TG is applied to one input terminal of the AND gate 6. A time measurement clock GK is applied to the other input terminal of the AND gate 6. A counter section 7 counts the measurement clock GK output from the AND gate 6 in accordance with the trigger signal TG output from the trigger section 4 to measure time. Note that this time measurement result is read into the CPU 3 after the application program is executed, and necessary arithmetic processing is performed. As such a counter section 7, a 16- to 24-bit binary counter, for example, is used depending on the measurement time.

FIG. 3 is a block diagram showing a specific example of FIG.
The same parts as in the figure are given the same reference numerals.

In FIG. 3, 8 is a register that stores the current program address CPA on the CPU bus, and its output is applied to one input terminal of comparator 9 and also to one input terminal of comparator 10. There is. Reference numeral 11 denotes a register that stores the start program address PA1, and its output is applied to the other input terminal of the comparator 9. 12 is a register that stores the stop program address P A 2, and its output is applied to the other input terminal of the comparator 10. 13 is a start event pulse Pa having a predetermined pulse width according to the output signal of the comparator 9.
The output pulse pa is applied to the down counter 14. 15 is comparator 1
This is a pulse generator that outputs a stop event pulse Pb of a predetermined pulse width in accordance with an output signal of 0, and the output pulse Pb is applied to the down counter 16. 1
A register 7 stores start event count data, and its output is preset to the down counter 14. 12 is a register that stores stop event count data, and its output is preset to the down counter 16. 19 is a set/reset type flip-flop, and a down counter 1 is connected to the set terminal S.
The output signal of the down counter 16 is applied to the reset terminal R. 20 is a clock generator that outputs a clock CK. 21 to 23 are 8-bit counters, and each of these counters 21 to 2
The count value of 3 is sent to the CPU 3 via registers 24 to 26.
is loaded into.

The operation of the #A position configured in this way will be explained using the timing chart of FIG. 4.

First, the start address register 11 of the trigger section 5.
Stop address register 12. The start event count data register 17 and the stop event count data register 18 are loaded with start condition data and stop condition data for setting a desired time measurement section in the counter section 7 before execution of the application program from the CPU 3. Since the trigger section 5 has the function of specifying the time measurement section in this way, the CPU 3
While the application program is being executed, it is only necessary to sequentially send the current program address CPA at the time of execution as shown in (a) to the address register 8, and the burden on the software is extremely light. The comparator 9 receives the program address C which is sequentially stored in the address register 8.
It compares PA and the program address P A + stored in the start address register 11 and outputs a match output to the pulse generator 13 . As a result, a start event pulse Pa as shown in (b) is output from the pulse generator 13 to the down counter 14.

When the down counter 14 counts a predetermined number of start event pulses Pa preset by the register 17, the start condition is satisfied as shown in (C), and the flip-flop 19 is set (f
The trigger signal TG rises as shown in >. On the other hand, the comparator 10 compares the program address CPA sequentially stored in the address register 8 with the program address P stored in the stop address register 12.
A2 is compared and a matching output is output to the pulse generator 15. As a result, the pulse generator 15 outputs a stop event pulse Pb as shown in (d) to the down counter 16. When the down counter 16 counts a predetermined number of stop event pulses Pb preset by the register 18, the stop condition is established as shown in (e), and the flip-flop 1
is reset and the trigger signal T is reset as shown in (f).
G will fall. As a result, the clock GK is applied to the counter section 7 through the AND gate 6 during the period when the trigger signal TG is rising, as shown in (l), and the desired test based on the application program including the loop program is performed. The execution time can be measured.The time data thus measured by the counter unit 7 will be collected by the CPU 3 after the application program is executed as described above.

This type of circuit can be configured relatively easily, and the number of circuit components increases only slightly when viewed from the overall device. The test execution time can be measured.

Further, processing for a part of the application program while the application program is being executed only requires sending the current program address, and the present invention does not cause the software to become complicated or the execution time to decrease.

In addition, since the trigger part makes decisions based on not only the start address and stop address but also the event count, it is possible to selectively measure the execution time of any test, even for application programs including complex loop programs. Can be done.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a semiconductor test device that can selectively measure the execution time of any test based on an application program with a relatively simple configuration, and has practical effects. is big.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the basic configuration of a time measurement unit, FIG. 3 is a block diagram showing a specific example of FIG. 2, and FIG. FIG. 3 is a timing chart for explaining the operation, and FIG. 5 is a conceptual diagram of the semiconductor test device. 1... Arithmetic control unit, 3... Arithmetic processing unit (CP
U), 4... Time measurement unit, 5... Trigger section, 6... AND gate, 7... Counter section. Agent Patent Attorney Shinsuke Kozawa Figure 1 Figure Z

Claims (1)

[Claims] A calculation control unit that controls a plurality of measurement modules according to a predetermined program according to a semiconductor device to be tested; and a trigger determined by determining a predetermined condition of the program executed by the calculation control unit. A semiconductor test device comprising: a trigger section that generates a signal; and a counter section that measures time according to the trigger signal output from the trigger section and outputs the measurement result to an arithmetic control section.