JPS63191254A - バツフア無効化方式 - Google Patents

バツフア無効化方式

Info

Publication number
JPS63191254A
JPS63191254A JP62023202A JP2320287A JPS63191254A JP S63191254 A JPS63191254 A JP S63191254A JP 62023202 A JP62023202 A JP 62023202A JP 2320287 A JP2320287 A JP 2320287A JP S63191254 A JPS63191254 A JP S63191254A
Authority
JP
Japan
Prior art keywords
buffer
tag
invalidation
address
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62023202A
Other languages
English (en)
Japanese (ja)
Other versions
JPH058458B2 (enExample
Inventor
Motoyoshi Hirose
元義 廣瀬
Yukihiko Kitano
北野　之彦
Tsuyoshi Motokurumada
強 本車田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62023202A priority Critical patent/JPS63191254A/ja
Publication of JPS63191254A publication Critical patent/JPS63191254A/ja
Publication of JPH058458B2 publication Critical patent/JPH058458B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP62023202A 1987-02-03 1987-02-03 バツフア無効化方式 Granted JPS63191254A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62023202A JPS63191254A (ja) 1987-02-03 1987-02-03 バツフア無効化方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62023202A JPS63191254A (ja) 1987-02-03 1987-02-03 バツフア無効化方式

Publications (2)

Publication Number Publication Date
JPS63191254A true JPS63191254A (ja) 1988-08-08
JPH058458B2 JPH058458B2 (enExample) 1993-02-02

Family

ID=12104082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62023202A Granted JPS63191254A (ja) 1987-02-03 1987-02-03 バツフア無効化方式

Country Status (1)

Country Link
JP (1) JPS63191254A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0512117A (ja) * 1991-07-04 1993-01-22 Toshiba Corp キヤツシユ一致化方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0512117A (ja) * 1991-07-04 1993-01-22 Toshiba Corp キヤツシユ一致化方式

Also Published As

Publication number Publication date
JPH058458B2 (enExample) 1993-02-02

Similar Documents

Publication Publication Date Title
US5133074A (en) Deadlock resolution with cache snooping
US5497480A (en) Broadcast demap for deallocating memory pages in a multiprocessor system
EP0303661B1 (en) Central processor unit for digital data processing system including write buffer management mechanism
JPH0461383B2 (enExample)
US4831581A (en) Central processor unit for digital data processing system including cache management mechanism
JPH0137773B2 (enExample)
JPH1031625A (ja) マルチ・プロセッサ・システムにおける改良されたコピーバック性能のためのライトバック・バッファ
US5263144A (en) Method and apparatus for sharing data between processors in a computer system
JP2695017B2 (ja) データ転送方式
US4658356A (en) Control system for updating a change bit
JPH04308953A (ja) 仮想アドレス計算機装置
JPH0410102B2 (enExample)
JPH0511337B2 (enExample)
JPS63191254A (ja) バツフア無効化方式
EP0153109A2 (en) Cache coherence system
JPH02110646A (ja) メモリの先行読出し装置
JP3226557B2 (ja) マルチプロセッサシステム
JPH0285960A (ja) 情報処理システム
JP3088293B2 (ja) キャッシュメモリの記憶一致制御装置及び記憶一致制御方法
EP0302926B1 (en) Control signal generation circuit for arithmetic and logic unit for digital processor
JPH0211931B2 (enExample)
JPH08272687A (ja) 入出力キャッシュメモリ
JP3217082B2 (ja) キャッシュ制御方式
JPS6345654A (ja) 情報処理装置の無効化処理方式
JPH05282207A (ja) キャッシュメモリ無効化制御方式