JPS63188188A - Display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a display control circuit in a character display device, and more particularly to a display control circuit equipped with a readable/writable memory as a character generator.

(Prior Art) The second factor is a block diagram showing an example of a conventional display control circuit. In Fig. 2, 20 to 22 are respectively 1 to 22.
Third buffer, 30 is character generator RAM
, 40 is the fourth buffer, 41 is the register, 42 is the fifth
50 is an OPU, 60 is a memory, and 80 is a bus arbitration circuit. Also, 31 is an address bus (lower),
32 is an address bus (upper), 33 is a data bus, 51
is an address bus, and s2 is a y-ta bus.

In the circuit shown in the second factor, when outputting a pattern from the character generator RAM 30 for display, the first
- an enable signal that turns the third buffers 720 to 22 into an output enabled state; and a fourth buffer 40. Register 41. and a disable signal for disabling fifth buffer 42 from outputting are output from bus arbitration circuit 80. Therefore, display rask information and code information are input to the address input of the character generator RAM 30 via the first and second buffers 20.21. At this time, a pattern appears on the data input/output terminal of the character generator RAM 30, and a display output is obtained via the third buffer 22.

On the other hand, when writing a pattern to the character generator RAM 30, execute the program using 0PU50, read the pattern from the memory 60, and write the pattern using 0PU50.
increases. Next, after setting the code information in the register 41, the 0PU50 outputs the rask information to the OPU address bus 51, outputs the previously fetched pattern to the CPU data bus 52, and requests writing to the bus arbitration circuit wr80. Outputs a ride request signal.

When the bus arbitration circuit 80 receives the ride request signal, it puts the 1 display buffer 22 into an output enabled state, turns off the enable signal, and outputs an enable signal that allows the write buffer register 41 to output. Therefore, the rask information is input to the address input of the character generator RAM 30 via the fourth buffer 40, and the register 4
Code information is input from 1.

Further, a pattern is input to the data input/output terminal via the fifth buffer 42, and the character generator R
Coverage to AM30 will be carried out.

When writing is completed, the bus arbitration circuit 80 outputs a ready signal to the 0PU 50, further outputs a display buffer output signal, and turns off the signal that allows the output of the write buffer register 41. Writing one pattern is performed through the series of steps described above, but if writing is performed during the display period rather than during the retrace period, the above series of steps is not actually performed in most cases.

During the storage operation, the third buffer 22 is prohibited from outputting, and the display output signal is not output normally during that period. Therefore, if writing is performed only during the flyback period, it will take a long time to write.

(Problems to be Solved by the Invention) The conventional display control circuit described above has the following first and second drawbacks. First, if a pattern is written to the character generator RAM while the pattern is being read from the character generator RAM for display, in order to give priority to pattern writing,
The disadvantage is that the display output during that period is no longer normal data, causing flickering on the display screen.

Second, since the pattern is written into the character generator RAM by a program, there is a drawback that the OPU is occupied for a long time.

An object of the present invention is to apply a retrace period signal to a DMA control circuit, continuously output a pattern from memory by DMA operation during the station line period, and then transfer the pattern to a character generator RAM.
It is an object of the present invention to provide a display control circuit configured to eliminate the above-mentioned drawbacks and quickly obtain a flicker-free screen by writing on the screen.

(Means for Solving the Problems) A display control circuit according to the present invention includes a memory, a character generator RAM, a DMA control circuit, and an OPU.

Memory is for storing arbitrary patterns.

The character generator L(, AM) is used to display a character by writing/reading a pattern.

The DMA control circuit provides a blanking period during which no display is performed using a blanking period signal, and performs control so that the DMA0 operation is performed in the center.

The OPU controls the memory and DMA control circuit, reads a pattern from the memory by DMA operation during the retrace period, and writes the pattern to the character generator RAM.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a display control circuit according to the present invention. In FIG. 1, elements similar to those in FIG. 2 are numbered similarly. Also, 70 is DM
AM control circuit 71 is an inverter.

In Figure 1, a character generator RA is used for display.
When reading a pattern from M30, the reading can be performed in the same manner as in the conventional method, and the i@1 to first to buffers 20 to 22 are always in an output enabled state during the display period.

When writing a pattern to the pot 51 character generator RAM 30, the 0PU 50 first sets code information in the register 41.

Next, the %0FU 50 sets in the DMA control circuit 70 the address of the memory 60 which is the data transfer source, the address of the character generator RAM 30 which corresponds to the data transfer destination (that is, rask information), and the number of data to be transferred.

In this state, when the retrace period signal on the signal line 72 is input to the DMA control circuit 70, the DMA control circuit 70
Hold 50. The hold request is a bus request signal, and the 0PU50's affirmative response to it is an acknowledge signal.

The DMA control circuit 70 thus obtained control of the bus.
enables the outputs of the fourth buffer 40, register 41, and fifth buffer 42, and prohibits the outputs of the first and second buffers 20 and 21. That is, it outputs an enable signal that permits output from the write register 41 and the second buffer 21, executes a DMA operation, and writes the pattern read from the memory 60 into the character generator RAM 30.

Since these series of operations for writing a pattern into the character generator RAM 30 are performed during the retrace period, the read operation of the character generator RAM 30 is not hindered, and writing by a program can be made faster.

(Effects of the Invention) As explained above, according to the present invention, the retrace period signal is
In addition to the MA control circuit, the following effects can be obtained by reading out a pattern from the DMA operation memory during the retrace period and writing the pattern to the character generator RAM.

First, read out a pattern from the character generator RAM for displaying one, and read the pattern from the character generator RAM.
Since there is no conflict when writing patterns to M, 1 display output is always output normally.

This has the effect that the display screen does not flicker, and the second
However, writing to the character generator RAM is not done by software using a program (DM
Since the A operation is performed, the time required for writing is shortened, and the overall processing speed of the OPU is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a display control circuit according to the present invention. FIG. 2 is a block diagram showing an example of a display control circuit according to the prior art. 20-22.40.42...buffer.

Claims (1)

[Claims] a memory for storing an arbitrary pattern; a character generator RAM for displaying the pattern as a character by writing/reading it; and a blanking period signal for providing a blanking period during which the display is not performed;
A DMA control circuit for controlling the execution of an MA operation, the memory, and the DMA control circuit to read the pattern from the memory by the DMA operation during the retrace period, and further read the pattern from the memory. A display control circuit comprising: a CPU for writing into the character generator RAM.