JPS63187495A - Memory device - Google Patents

Abstract

PURPOSE:To facilitate the information processing for plural meshes by applying mode selection so as to switch the at the normal mode and the access at the vertical mode. CONSTITUTION:In case of the access by the normal mode, while a row address is supplied by a RAS, four column address by supplied by, e.g., four CAS. In an equivalent memory device, D11-D41, D12-D42, D13-D49 and D14-D44 are accessed sequentially. In case of the access by the vertical mode, while the row address is supplied by the RAS, four column address are supplied by four CAS, for example. Then D11-D14, D21-D24, D31-D34 and D41-D44 are accessed sequentially. Thus, it is possible to select easily the normal mode and the vertical mode and the processing processing a data corresponding to plural meshes as a word is attained efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a memory device that stores image information having, for example, RGB and monochrome color signals, memory planes are stacked in sets (for example, four sets).

The normal mode writes and/or reads all at once to the memory planes existing in the stacking direction, and the normal mode writes and/or reads all at once to the memory planes existing in the stacking direction. It is possible to select a particle mode for writing and/or reading all column positions at once.

It is disclosed that it is possible to easily process information for a plurality of meshes each having a color signal.

[Industrial application field]

The present invention provides a memory device, particularly an image information storage memory device configured by stacking, for example, four sets of memory planes. The present invention relates to a memory device that can switch between accessing multiple meshes at once for one color.

(Prior Art) In a memory device that stores image information having RGB and monochrome color signals for each mesh, a memory plane 1-i of m rows and n columns has conventionally been arranged as shown in FIG. The memory planes are stacked in the form of memory planes 1-1 to 1-4.

Information regarding one mesh is shown in 9 diagrams DIl, Dz
++D21. It is stored as 4-bit information such as D41. With this configuration, each of the memory planes 1-1 to 1-4 can be accessed independently. In response to the application of the column address strobe (hereinafter abbreviated as CAS), the above DII+D z I+ D 311
It is possible to read/write the 4-bit information of D a + all at once.

[Problem that the invention seeks to solve]

Since data processing devices generally process four or more bits as one word, it is desirable to process information on a plurality of meshes as one word. In such a case, in the configuration shown in FIG.
□, D, 2-. When attempting to read/write data such as D, . . . , it is necessary to read/write each Dli.

That is, it is necessary to apply a plurality of RAS.

Then, taking the example of reading, the data that has been output multiple times is rDII+DI! +...
- Like (requires a lot of hardware to summarize into one word)

[Means for solving problems]

The present invention solves the above problems, and by selecting the mode, D! 1. Access in the form of DZI DZI D41 (access in normal mode) and D.

Access in the form of D1□, D1s+ D14...
access in particle mode).

FIG. 1 shows a basic configuration diagram of the present invention. In FIG. 1, reference numerals 1-1 to 1-4 indicate memory planes 2-11 to 2-14. 2-21 to 2-24. 2-31 to 2-34. and 2-41 to 2-44 represent unit memory planes, respectively. Further, 3-1, 3-2, 3-3, and 3-4 respectively constitute a memory unit according to the present invention. Furthermore, one memory plane 1-4 has four units in the case of two diagrams.
It is divided into memory planes 2-if to 2-14.

The individual unit memory planes '1-ij are configured so that they can be accessed independently from each other.

[Effect]

In the case of access using the above normal mode, R
While a row address is supplied by AS, four column addresses are supplied by one CAS, for example four times. and (i) the first CAS.
is applied.

In memory unit 3-1, 2 e.g. DII+ DZI+
When D 3110 a I is accessed and (ii) the second CAs is applied, in memory unit 3-2, DIz, Dzz, Dzz, D4Z are accessed, ... (1v) the fourth CAs is applied. When CAS is applied, in memory unit 3-4, Dla, D
za+Dsa+Dl4 is accessed. This means that in the equivalent memory device shown in FIG.
, or Dn++ I) 1! Or D4z, Dl2
This corresponds to the fact that Ishiri, . . . , D, through Dl4 are accessed in sequence. That is, it has substantially the same shape as the conventional case shown with reference to FIG.

Even in the case of access in the particle mode in the case of the present invention, while a row address is supplied by RAS, four column addresses are supplied by one CAS, for example, four times. . and 5
(i) When the first CAS is applied, the unit memory planes z-11 to 2-14 shown in FIG.
,D,,,D,3゜[)+a is accessed, (ii)
When the second CAS is applied, the unit shown in Figure 1.
On memory plane 2-21 to 2-24, D2□ D
2□+D2ff+Dt4 is accessed and...(iv
) When the fourth CAS is applied, D4d on the unit memory planes 2-41 to 2-44 shown in FIG.
, Da□+Da s +D44 are accessed. At this time, 7. In the equivalent memory device shown in FIG. 1, +D 1 H to DearD21 to Dt
This corresponds to J+ D31 to D24+ D41 to Dl4 being accessed in order.

[Embodiment] FIG. 2 shows the configuration of an embodiment of the present invention. Code “1” in the diagram
-ij is the unit memory plane, 3-j is the memory unit,
4 is a row address decoder, and 5-1j are column decoder mapping units.

5-ij is a register pointer section, 7 is an address buffer section, 8-1 and 8-2 are each an I10 buffer section,
9 is a multiplane bit operation section.

10 represents a data collection/distribution section, 11-j represents a bit operation unit, and 12 represents a bus. Also, MDj/Dj is mask data/write data, SDj is bit serial read data, BT is multiplane bit operation unit timing signal, BA is multiplane bit operation unit address, Aa to A are address information, SAS represents a serial access memory strobe.

An address buffer section (AB) 7 buffers address information, supplies one row address to a row address decoder (RAD) 4 in response to one RAS, and inputs one row address in response to one RAS. For example, four column addresses are supplied to the column decoder mapping section (ODA) 5-1j corresponding to four CAs, and access on the unit memory plane 2-il is performed for each column address supply. The position is determined.

Under normal mode, (i) corresponding to the first RAS, the column decoder mapping unit (CDA)
The same column address is supplied to 5-11, 5-21, 5-31 and 5-41.

(ii) Corresponding to the second RAS, column decoder mapping sections (ODA) 5-12, 5-22, and 5-
32 and 5-42 are provided with the same column address;
...and under particle mode,
(i) Corresponding to the first RAS, column decoder mapping sections (CDA) 5-11, 5-12, and 5-
13 and 5-14 are provided with the same column address,
(ii) Corresponding to the second RAS, column decoder mapping sections (CDA) 5-21, 5-22, and 5-
23 and 5-24 are provided with the same column address,
...I'm leaving. In addition, in response to the above access.

Accessed unit memory plane 2-il.

Corresponding to 2-42, 2-+3, 2-+4, register
Pointer part (RP) 6-+1.6-42°6-+3,6
-+4 is selected and successive data is accepted.

The write data is led to the column decoder/muffling unit (ODA) 5-ij via the bus 12, but at this time, the write data is transferred from the address buffer unit (AB) 7 to the multiplane bit operation unit address ( BA) is supplied to the multiplane bit operation unit (MI30) 9, and based on the focus operation unit (BOIJ) 11-j,
Any of the four column decoder mapping sections (CD
A) 4 unit memory planes 2- through 5-1j
4j is determined.

Continuous data during reading is processed by the column decoder.
Mapping section (CDA) 5-i j, multiplane
Bit operation unit (MBO)9. It is output via the I10 buffer units 8-1. On the other hand, read data is output to the display from the four units that have been accessed for reading.
Corresponding to memory plane 2-ij, it is received by four register pointer units (rl) 6-4j and output via I10 buffer unit 8-2.

In the above description, when accessing in the particle mode, the address buffer section (AB) 7 transfers the column address to the column decoder mapping section (CD
A) For example, column decoder mapping section (CDA) 5-11.5-21.
5-31. Either one of 5-41 is selected and that 1
The explanation was given assuming that the column address is supplied to the column address. However, the following form can also be adopted as other means.

That is, in the above example, the address buffer section (AB) 7 is connected to the column decoder mapping section (CDA) 5.
The same value is supplied to -11, 5-21, 5-31, and 5-41 all at once, and the bit operation unit (BOU)
Depending on the mask information prepared in the column decoder mapping unit (CDA) 11-1, it is possible to enable only one of the column decoder mapping units (CDA) 5-11 to 5-41. In this case, the above mask information is.

It is designated by the multiplane bit operation unit address BA.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to easily select between normal mode and particle mode. Therefore, it is possible to efficiently process data corresponding to a plurality of meshes as one word.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is an explanatory diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional case. 1-i is a memory plane, '1-4j is a unit memory plane, 3-j is a memory unit, 4 is a row address decoder, 5-ij is a column decoder mapping section, 6-
ij is a register pointer section. 9 represents a multiplane bit operation section.

Claims (1)

[Claims] A row is selected by a row address taken by a row address strobe (RAS) and a column is
K sets of memory planes (1-i) of m rows and n columns are stacked, the columns of which are selected by the column address taken in by the address strobe (CAS), and one row address strobe (CAS) is applied. One or more column address strobes (RAS) are applied while the column address strobe (RAS) is applied.
CAS) is configured to apply the above-mentioned one column
In response to the application of an address strobe (CAS), each of the rows is
Write the write data given to the respective positions specified by the address and the above column address and/or write the given write data to the respective positions specified by the above m rows x n columns of the memory plane (1-
i) as a unit memory plane with m rows and (n/k) columns (
The unit memory plane (2-ij
) are stacked in k sets of memory units (3-j) arranged in k or more in the column direction, and applied while the row address strobe (RAS) is applied once. One column address
The above m rows x (n/k) corresponding to the strobe (CAS)
Each of the individual unit memory planes (2-ij) constituting one memory unit (3-j) in which k sets of unit memory planes (2-ij) in a column are stacked is accessed all at once. mode, and for each of the k or more memory units (3-j) arranged in the column direction, any one unit memory selected forming the individual memory unit (3-j); A memory device characterized in that it is possible to select a mode in which each of the planes (2-ij) is accessed all at once.