JPS6318721A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain plural output signals with different frequency division ratios from one input signal and to reduce the power consumption by combining plural frequency division circuits to obtain output signals with different frequency division ratio and stopping the frequency division circuits whose operation is not required depending on the requested frequency division ratio by means of interruption of a bias voltage or the like. CONSTITUTION:In obtaining an output signal Va with a different frequency division ratio, a control signal Vc turns a changeover circuit 13 as shown in dotted lines and a current source of a frequency division circuit 12 is cut off. As soon as the circuit 12 is inactivated, the power consumption is reduced. That is, the control signal Vc acts like a switching control signal and a power supply interruption control signal, and a prescribed timing correlation is regarded as a simultaneous time. Then the output signal Va subjected to 1/M frequency division by a frequency division circuit 11 is fed to the circuit 13. Thus, the output signal Va is obtained as an output signal of the signal processing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing circuit suitable for use when obtaining output signals with different frequency division ratios from one input signal. It can be used in programmer pull counters, etc. to develop effective technology.

[Conventional technology]

Glyscalers are used in cellular radios, FM receivers, and the like. The prescaler and furthermore the programmable counter obtain an output signal of a frequency divided from an input signal of a predetermined frequency, and the frequency division ratio may be constant or variable. Also, if the division ratio is dog,
A plurality of frequency dividing circuits having different frequency dividing ratios may be provided and the frequency may be divided in stages to obtain a desired frequency dividing ratio.

An example of the above prescaler and programmable counter is described in "rFM Tuner Manual" (1st reprint issued on September 1, 1970, published by Radio Gijutsusha, p. 189). The outline is that the frequency signal extracted from the vCO is divided into 17M, and further divided into 1/N by a programmable counter. The frequency division ratio N is configured to be variable.

The inventors of the present invention have studied how to reduce the power consumption of a signal processing circuit suitable for the above-mentioned prescaler, programmable counter, and the like.

That is, the signal processing circuit shown in FIG. 5 has a frequency division ratio of 1/M.
The frequency dividing circuit 1 has a frequency division ratio of 1/N, a frequency dividing circuit 2 has a frequency division ratio of 1/N, and a switching circuit 3. When the input signal Vin of a predetermined frequency is supplied and the switching circuit 3 is switched as shown by the solid line by the control signal Vc, 17M-
The output vb frequency-divided to H is obtained as the output signal Vout. When the switching circuit 3 is switched as shown by the dotted line, the output Va divided by 1/M becomes the output signal Vo.
Obtained as ut.

However, according to the studies conducted by the present inventors, it has become clear that the above-mentioned signal processing circuit has the following problems.

[Problem that the invention seeks to solve]

In other words, since the frequency dividing circuit requires high-speed response, E
It is often composed of a CL circuit.

However, the ECL circuit has five drawbacks such as high power consumption.

Looking at the above signal processing circuit, when obtaining the output signal Vout frequency-divided to 17M, power consumption is reduced because the frequency divider circuit 2 that performs 1/N frequency division is not required, but it continues to be energized. increase It has been realized that if the power consumption of the frequency dividing circuit 2 can be stopped, the power consumption of electronic equipment to which the signal processing circuit is applied can be significantly reduced.

Particularly in electronic devices that use batteries as a power source, reduced power consumption is a great advantage as it allows for longer battery life.

An object of the present invention is to provide an ear signal processing circuit that can obtain an output signal whose frequency is divided by a desired frequency division ratio with respect to an input signal and at the same time reduce power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Failure to solve the problem]

A brief summary of typical inventions disclosed in this subject is as follows.

In other words, a plurality of signal processing systems using frequency dividing circuits with different frequency division ratios are combined. The above combinations should be combined so that the output signals obtained from the plurality of signal processing systems can be combined or individually derived. Furthermore, a switching circuit for selectively switching between the combined output signal and the individual output signals using a switching control signal, or a switching circuit for switching input signals to the plurality of signal processing systems is provided, and the switching circuit is The switching operation is performed by controlling the energization of the plurality of signal processing systems using a power cutoff control signal having a certain timing correlation with the switching control signal.

[Effect]

According to the above means, the switching circuit is switched by the switching control signal to obtain output signals with different frequency division ratios from the plurality of frequency dividing circuits, and when one of the plurality of signal processing systems is unnecessary, the above switching circuit is switched by the switching control signal. An object of the present invention is to obtain a signal processing circuit that can stop energization using a power cutoff control signal that has a certain timing correlation with a switching control signal, and that can obtain output signals with different frequency division ratios and at the same time obtain low power consumption signal processing circuits. Be able to achieve.

[Embodiment 1] Hereinafter, a first embodiment of a signal processing circuit to which the present invention is applied will be described with reference to FIGS. 1 and 2.

Note that FIG. 1 is a circuit diagram showing the basic concept of the signal processing circuit, and FIG. 2 is a circuit diagram showing a specific example.

The feature of this embodiment is that when multiple signal processing systems consisting of frequency dividing circuits with different frequency division ratios are combined in series, power consumption can be reduced by stopping power supply to unnecessary signal processing systems. This is because it is configured like this.

First, the basic circuit operation of the signal processing circuit will be explained with reference to FIG.

11 is a frequency dividing circuit whose frequency dividing ratio is set to 1/M;
2 is a frequency dividing circuit whose frequency dividing ratio is set to 1/N. The frequency dividing circuits 11 and 12 are connected in series, and one of the frequency dividing circuits 11 and 12 is connected in series.
The output signal Va frequency-divided to 7M is supplied to the next-stage frequency dividing circuit 12 and further to the switching circuit 13.

The switching circuit 13 is switched as shown by a solid line or a dotted line by a control signal VC. Although the switching circuit 13 is illustrated as a switch having a mechanical structure, it is actually constituted by an electronic switch.

An input signal V in of a predetermined frequency is supplied, and 17M·
When it is desired to obtain an output signal vb whose frequency is divided into
Power should be supplied to 2 as well.

The input signal Min is supplied to the frequency dividing circuit 11, and an output signal Va whose frequency is divided into 17M is obtained. Since the output signal Va is frequency-divided by the frequency dividing circuit 12 to ]/N, the frequency dividing circuit 1
The output signal vb of No. 2 is frequency-divided at a frequency division ratio of 1/N1·N.

Since the switching circuit 13 is switched as described above, the output signal vb is obtained from the signal processing circuit.

On the other hand, when obtaining output signals Va with different frequency division ratios, noteworthy circuit operations should be performed as described below.

That is, in this case, the switching circuit 13 is switched as shown by the dotted line by the control signal Vc, and at the same time, the current source of the frequency dividing circuit 12 is cut off.

The frequency dividing circuit 12 becomes inactive and at the same time, power consumption is reduced. That is, the control signal Vc serves as both a switching control signal and a power cutoff control signal, and a certain timing correlation can be seen as simultaneous.

Then, the output signal Va whose frequency has been divided by 1/M by the frequency dividing circuit 11 is supplied to the switching circuit 13. Therefore, the output signal Va is obtained as the output signal of the signal processing circuit.

Next, a specific example of the signal processing circuit will be described with reference to FIG.

14 is a bias circuit, and when the power supply Vcc is supplied, the transistor Q+TQt, the resistors R, +R1
Obtain the bias voltage Vx stabilized by the action of .

Transistors Q, ~Q1, and resistors R1~R1 supply constant current to the frequency divider circuit 11 -! The transistors Q, ~Qn, and the resistors R5~R1 are connected to the frequency dividing circuit 12.
It supplies a constant current to the

The resistors Ra, Rb, ) transistor Qa are used to control supply and interruption of constant current to the frequency dividing circuit 12.

That is, when the frequency dividing circuits 11 and 12 are simultaneously driven to obtain the output signal Va, no constant current is supplied from the constant current circuit C81. Transistor Qa is turned off and bias voltage Vx is applied to transistor Q.

~Q+ 1 each pace is supplied. In this case, the resistance R
Although there is a voltage drop due to a, the transistors Qs to Qu operate normally.

Then, the frequency dividing circuits 11 and 12 are connected to the above 1/M and 1/N.
The frequency division operation is performed according to the frequency division ratio of switching circuit 1.
3, the output signal vb can also be obtained.

On the other hand, when a constant current is supplied to the constant current circuit C8 and the transistor Qa, the transistor Qa operates in an on state, and the voltage level at point A becomes equal to that of the resistor Ra.

The voltage level is reduced to the voltage level divided by Rh.

Therefore, an operable bias voltage is not supplied to the transistors Q and Q11, and these are turned off and the frequency divider circuit 12 is also rendered inoperable.

However, the bias voltage Vx for transistors Q, ~Q,
is supplied, so the frequency divider circuit 11 performs a division operation. In addition to supplying a constant current to the transistor Qa with respect to -rb,
Since the switching circuit 13 is switched as shown by the dotted line, an output signal Va is obtained.

As a result of the circuit operation as described above, the following effects can be obtained in this embodiment.

(1) Frequency divider circuits with different frequency division ratios are connected in series, and the subsequent frequency divider circuit can be controlled to operate and deactivate by a control signal, and when the frequency divider circuits are connected in series and the subsequent stage is controlled by the control signal, Since the frequency dividing circuit is configured to selectively obtain the non-operating output signal, an effect can be obtained in that a plurality of output signals having different frequency division ratios can be obtained from the - input signal.

(2) According to (1) above, when the frequency divider circuit in the subsequent stage is made inactive, the power consumption by the frequency divider circuit can be reduced.

(3) Since the circuit configuration is simple, it is possible to easily integrate the circuit into a semiconductor integrated circuit.

(4) The branch circuit is selectively driven by transistor Q.

Since it is performed by driving, the control current only needs to be small.
This effect can be obtained.

[Embodiment 2] Next, a second embodiment of the present invention will be described with reference to FIG.

The difference between this embodiment and the first embodiment is that the frequency dividing circuit 11
．． The reason lies in that the switching circuit 13 is placed between 12 and 12.
The same parts as in the first embodiment are given the same reference numerals to avoid duplication of explanation.

When obtaining the output signal vb, the switching circuit 13 is switched as shown by the solid line, and the frequency dividing circuit 12 is also put into operation. The output signal Va of the frequency dividing circuit 11 is supplied to the frequency dividing circuit 12 via the switching circuit 13. Therefore, an output signal vb whose frequency is divided by 1/MN is obtained from the frequency dividing circuit 12.

On the other hand, when it is desired to obtain an output signal Va frequency-divided to 17M, the switching circuit 13 is switched as shown by the dotted line by the control signal Vc, and the frequency dividing circuit 12 is rendered inactive.

Therefore, the output signal Va of the frequency dividing circuit 11 is obtained via the switching circuit 13.

As a result of the circuit operation described above, the same effects as described above can be obtained in this embodiment as well.

[Embodiment 3] Next, a third embodiment of the present invention will be described with reference to FIG. 4.

The feature of this embodiment is that the frequency dividing circuits 11 and 12 are connected in parallel and are individually driven.

If it is desired to obtain an output signal Va whose frequency is divided by 1/M, the switching circuit 13 is switched as shown by the solid line using the control signal Vc, and at the same time, the frequency dividing circuit 12 is made inactive.

Since the frequency dividing circuit 11 is supplied with the control signal Vc whose phase has been inverted by the inverter 15, it becomes operable.

The input signal Vin is supplied to the frequency dividing circuit 11, and an output signal Va whose frequency is divided into 17M is obtained.

On the other hand, if it is desired to obtain the output signal vb whose frequency is divided by 1/N, the level of the control signal VC is converted. Switching circuit 13
is switched as shown by the dotted line, and at the same time the frequency dividing circuit 12 becomes operational. On the other hand, since the control signal Vc whose phase has been inverted by the inverter 15 is supplied to the frequency dividing circuit 11, it becomes inactive.

Therefore, in this case, the output signal V divided by 1/H
n is obtained.

As a result of the circuit operation as described above, this embodiment has the following effects.

(5) Multiple frequency divider circuits with different frequency division ratios are provided in parallel, input signals are individually supplied, and the drive of each frequency divider circuit can be controlled individually, so the frequency divider circuit can be selectively controlled. The effect is that it is possible to obtain output signals with different frequency division ratios by driving.

(6) Among the plurality of frequency divider circuits, the frequency divider circuits that do not need to operate can be made non-operational by cutting off the current, so it is possible to reduce power consumption.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and can be modified without departing from the gist of the invention. Needless to say. For example, the control signal VC in each of the above embodiments may be configured such that the control signal for the switching circuit and the control signal for selecting the drive of the frequency dividing circuit are separated, and the two are synchronized.

A larger number of frequency dividing circuits having different frequency dividing ratios may be provided.

The frequency dividing circuit may be selectively driven by supplying and cutting off power in addition to supplying and cutting off bias voltage.

The frequency division ratios of the frequency dividing circuits may be different as described above, but they may also be the same frequency division ratio (and can be freely set).

In the above explanation, the invention made by the present inventor was mainly applied to a frequency dividing circuit, which is the field of application that formed the background of the invention, but the present invention is not limited to this, and is applicable to various types of circuits that require a selection circuit. It can be used for electronic devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

By combining multiple frequency divider circuits to obtain output signals with different frequency division ratios, and by stopping the operation of frequency divider circuits that do not need to operate according to the frequency division ratio by cutting off the bias voltage A4, - It is possible to obtain a plurality of output signals with different frequency division ratios from an input signal, further reducing power consumption. This effect can be obtained.

[Brief explanation of drawings]

1 and 2 show a first embodiment of a signal processing circuit to which the present invention is applied. FIG. 1 is a circuit diagram explaining the basic concept of the signal processing circuit, and FIG. A circuit diagram showing a specific circuit configuration of the above signal processing circuit; FIG. 3 is a circuit diagram showing a second embodiment of the present invention; FIG. 4 is a circuit diagram of a slang processing circuit; FIG. 4 is a circuit diagram showing a third embodiment of the present invention. Circuit Diagram of Signal Processing Circuit FIG. 5 shows a circuit diagram of a signal processing circuit studied prior to the present invention. 11.12... Frequency dividing circuit, 13... Switching circuit,
14...Bias circuit, 15...Inverter, Q1
~Q++...Transistor, Va, Vb, Vn...
Output signal, Vin...input signal, Vc...control signal. Agent Patent Attorney Katsuo Ogawa Figure 1 C Figure 2 Figure 3 Figure 5 Figure 4 Figure 4 C

Claims (1)

[Claims] 1. A signal processing circuit that obtains a plurality of output signals for one input signal by combining a plurality of signal processing systems, the signal processing circuit obtaining a plurality of output signals for one input signal by combining a plurality of signal processing systems; While selectively driving the signal processing system to obtain a desired output signal,
A signal processing circuit characterized in that when any one of the plurality of signal processing systems is selected, the other signal processing system is rendered inactive. 2. The plurality of signal processing systems are frequency dividing circuits set to desired frequency division ratios, and by selectively driving the plurality of signal processing systems, the plurality of signal processing systems have different frequency division ratios for the one input signal. 2. The signal processing circuit according to claim 1, wherein the signal processing circuit obtains a plurality of output signals. 3. The signal processing circuit according to claim 1, wherein the frequency dividing circuit is constructed using an ECL circuit. 4. The signal processing circuit according to claim 1, wherein the operation of the signal processing system is stopped by cutting off a current source supplied to the signal processing system. 5. The plurality of signal processing systems are selectively driven by a switching control signal, and the current source is cut off by a power cutoff control signal, and the switching control signal and the power cutoff control signal have a certain timing correlation with each other. The signal processing circuit according to claim 1, characterized in that the signal processing circuit has: