JPH10276084A - Pll synthesizer integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize low power consumption and to decrease an area of the integrated circuit by stopping the operation of unrequired circuits among a plurality of PLL circuits. SOLUTION: The integrated circuit 1 is provided with input amplifiers 21, 22, 31, programmable counters 23, 32 and phase comparators 24, 33 for radio audio and non-voice data, and with a reference counter 41 in common for both the data. Moreover, switching transistors(TRs) 61, 62, 63 to control each input amplifier to be the operating state are connected to the circuit 1 and a control circuit 50 gives control data to the switching TRs 61-63 to activate only a required PLL and to inactivate undesired PLLs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a PLL synthesizer integrated circuit suitable for a system requiring a plurality of receiving circuits in an FM radio receiver.

[0002]

2. Description of the Related Art In FM radio, non-speech information such as character data is multiplex-broadcasted together with sound. Usually, non-speech information transmitted from the same broadcasting station as a radio sound broadcasting station is transmitted. It received information and displayed characters. Therefore, a single PLL synthesizer circuit for reception was sufficient.

However, as FM multiplex broadcasting stations increase,
There is an increasing demand for receiving non-speech information transmitted by another broadcasting station while listening to the radio sound of one broadcasting station. In order to respond to such a request, a P
As the LL synthesizer circuit, two systems for voice and non-voice are required. Generally, PLL synthesizer circuits are integrated, so that two PLL synthesizer integrated circuits have to be used to provide two systems in a radio receiver.

[0004]

The use of two PLL synthesizer integrated circuits makes it possible to receive broadcasts from different broadcasting stations for voice and non-voice, and can certainly meet the above demand. However, it is not always necessary to receive such separate broadcasting stations, and when listening to audio only, a non-audio system is not required, and when only non-audio data is used, an audio system is not required. Becomes However, since the conventional PLL synthesizer integrated circuit includes only one system of PLL circuit and is naturally developed so as to always operate, a special configuration such as a power supply control circuit or the like can be obtained by simply using two of them. Without it, it was impossible to bring only one of them into operation.

[0005] Further, since such an unnecessary PLL circuit operates, it is not preferable in terms of power consumption.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a PLL synthesizer integrated circuit, each of which includes an input amplifier for amplifying an input signal, a programmer counter for dividing an output signal of the input amplifier, and a reference for dividing a reference signal. A counter, and a phase comparator for comparing the phases of the output signals of the programmable counter and the reference counter, and a plurality of sets of PLL circuits capable of operating simultaneously; and a PLL circuit selected from the plurality of sets of PLL circuits. At least one
And a control circuit for controlling one of the circuit configurations to an operation stop state.

In the present invention, the plurality of sets of reference counters are shared by a single reference counter. Further, in the present invention, the sole reference counter is constituted by a plurality of frequency dividers, and the control circuit sets a frequency divider other than a frequency divider required by the selected PLL circuit to an operation stop state. Features.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numeral 1 denotes a two-system PLL for AM and FM radio audio and non-audio data which is FM multiplexed data.
This is a PLL synthesizer integrated circuit having circuits 2 and 3. The integrated circuit 1 includes an AM input amplifier 21 and an FM input amplifier 22 for radio sound, a programmable counter 23 for dividing the output of each amplifier, and a crystal oscillator 4.
A reference counter 41 for dividing the reference signal from
Programmable counter 23 and reference counter 4
1, a low-pass filter 5 is connected to the output of the phase comparator 24, and the VCO 6 for AM and the VCO 7 for FM are connected to the output of the low-pass filter 5 to form a first PLL. ing.

Further, for non-voice data, an input amplifier 31, a programmable counter 32 for dividing the output of the amplifier, and a phase comparator 33 for inputting output signals of the programmable counter 32 and the reference counter 41 are provided.
The low-pass filter 8 is connected to the output of the phase comparator 33, and the VCO 9 is connected to the output of the low-pass filter 8.
L is configured. The reference counter 41
Is also used for audio.

Further, a control circuit 50 for inputting control data from an external controller 10 and controlling each circuit in the integrated circuit 1 is provided.
Switching transistors 61, 62, 63 for stopping the operation are connected to 22, 31.
Therefore, when operating both the first and second PLLs, the frequency data corresponding to the broadcast station of the radio sound desired to be heard and the frequency data corresponding to the broadcast station transmitting the non-speech data desired to be received are defined as: These frequency data are transmitted from the controller 10 and set in the programmable counters 23 and 32 by the control circuit 50. Furthermore,
The control data of the L level is similarly transmitted from the controller 10 via the control circuit 50 to the switching transistor 6.
1 and 62 and the switching transistor 63 is supplied to turn off the switching transistor.
By this control, either one of the input amplifiers 21 and 22 and the input amplifier 31 are brought into an operating state, and both the first and second PLLs operate.

On the other hand, when the user wants to hear only the voice, the frequency data is set only in the programmable counter 23, the control data of the L level is supplied to one of the switching transistors 61 and 62, and the H level is supplied to the switching transistor 63. Supply control data. According to this control, one of the input amplifiers 21 and 22 is activated, and the input amplifier 31 is not activated. Therefore, only the first PLL operates, the second PLL stops, and the power consumption is only for one system PLL.

On the other hand, when it is desired to receive only non-voice data, the frequency data is set only in the programmable counter 32 and the switching transistors 61 and 62 are set.
, And L-level control data to the switching transistor 63. According to this control, the input amplifiers 21 and 22 are in a non-operation state, and the input amplifier 31 is in an operation state. Therefore, only the second PLL operates, the first PLL stops, and the power consumption is only for one system PLL.

As described above, only the PLL to be operated is selected based on the control data, and the PLL not to be operated is selected.
Can be stopped. By the way, in the present embodiment, the reference counter 41 is provided by two systems of PLs.
Since L is also used, the entire counter cannot be stopped. However, the reference counter 41 is composed of a plurality of frequency dividers, and realizes low power consumption by stopping unnecessary frequency dividers.

That is, the reference counter 41 corresponds to FIG.
As shown in the figure, the frequency division ratio is 1/8, 1/9, 1/2, 1 /
Six frequency dividers 411 to 416 of 10, 1/9 and 1/10
And 100K from the frequency dividers 412 and 413, respectively.
Hz, 50 KHz reference signal is output, and the frequency divider 41
5,416 output reference signals of 10 KHz and 9 KHz, respectively. Further, two multiplexers 417, 41
8 is provided, the multiplexer 417 selects and outputs one of the 100 KHz and 50 KHz reference signals, and the multiplexer 417 selects 100 KHz, 50 KHz, and 10 KHz.
A reference signal of either KHz or 9 KHz is selected and output.

The control circuit 50 includes a multiplexer 417,
Control data indicating which reference signal to select is supplied to 418, and reset control data is supplied to each of the frequency dividers 412 to 418, whereby unnecessary frequency dividers are stopped by this data. For example, when 100 KHz is used as the reference frequency for voice and the same 100 KHz is used as the reference frequency for non-voice data, the control circuit 50 sends reset data to the frequency dividers 413, 414, 415, and 416 to separate these data. The frequency divider is stopped, and the frequency divider 4
The reset data is not sent to 11, 412 and these are set to the operation state.

On the other hand, when only the AM radio sound is to be heard, the control circuit 50 sends reset data to the frequency dividers 412, 413 and 415 to stop them, and sets the remaining frequency dividers 411, 414 and 416 to the operating state. And As a result, a 9 KHz reference signal is output from the frequency divider 416, and the reference signal is output via the multiplexer 418.

As described above, only the necessary frequency divider operates and the unnecessary frequency divider stops, so that low power consumption is achieved. In the above-described embodiment, the input amplifier is set to the operation stop state. Alternatively, the programmable counter or the phase comparator may be set to the operation stop state.
Further, a combination thereof may be used.

[0018]

According to the present invention, unnecessary PLL circuits can be brought into an operation stop state without providing a special configuration such as a power supply control circuit, and therefore, low power consumption can be realized. Further, since the plurality of PLL circuits also serve as the reference counter, the area of the integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a specific configuration of a reference counter according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PLL synthesizer integrated circuit 2, 3 PLL circuit 5, 8 Low-pass filter 6, 7, 9 VCO 10 Controller 21, 22, 31 Input amplifier 23, 32 Programmable counter 24, 33 Phase comparator 41 Reference counter 50 Control circuit 61, 62 , 63 switching transistor

Claims (3)

[Claims] 1. An input amplifier for amplifying an input signal, a programmable counter for dividing an output signal of the input amplifier, a reference counter for dividing a reference signal, and phases of output signals of the programmable counter and the reference counter. A plurality of sets of PLL circuits having a phase comparator for comparing the same, and a control circuit controlling at least one circuit configuration in a selected PLL circuit among the plurality of sets of PLL circuits to an operation stop state; and A PLL synthesizer integrated circuit comprising: 2. The plurality of sets of reference counters,
2. The PLL synthesizer integrated circuit according to claim 1, wherein the PLL synthesizer is shared by a single reference counter. 3. The single reference counter is composed of a plurality of frequency dividers, and the control circuit selects a selected P.
3. The PLL synthesizer integrated circuit according to claim 2, wherein the frequency dividers other than the frequency divider required in the LL circuit are in an operation stop state.