JPS63185040A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63185040A
JPS63185040A JP1700187A JP1700187A JPS63185040A JP S63185040 A JPS63185040 A JP S63185040A JP 1700187 A JP1700187 A JP 1700187A JP 1700187 A JP1700187 A JP 1700187A JP S63185040 A JPS63185040 A JP S63185040A
Authority
JP
Japan
Prior art keywords
silicon
semiconductor substrate
type
transistor
embedded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1700187A
Other languages
Japanese (ja)
Inventor
Masahiro Yoneda
昌弘 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1700187A priority Critical patent/JPS63185040A/en
Publication of JPS63185040A publication Critical patent/JPS63185040A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To suppress the intrusion of impurities into a transistor channel region and to obtain an excellent element isolating characteristic, by embedding semiconductor layers having the same conductivity type as that of a semiconductor substrate in grooves, which are formed in the surface of a silicon semiconductor substrate, and electrically isolating elements. CONSTITUTION:P-type polycrystalline silicon films 8 are embedded in grooves 8 formed in the surface of a p<-> type semiconductor substrate. Thus elements are isolated. Not only the same element isolating characteristic as that of a conventional semiconductor device is obtained, but also intrusion of p<->type impurities into the channel region of a transistor can be eliminated. Therefore, the width of the gate of the transistor becomes the length determined by the element isolating region. Increase in threshold voltage value can be prevented even in the transistor, in which especially short gate width is required. Since polycrystalline silicon is embedded in the silicon grooves 2, an impurity forming step can be omitted, and the manufacturing process can be shortened. The p<->type polycrystalline silicon film 8 is formed on only the side wall part and the bottom wall part of each silicon groove 32. An insulating film 3 is embedded in the remaining part of each silicon groove 2, and thus the surface of the silicon semiconductor substrate can be flattened.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置に関し、特に微細なトレンチ型
分離を狭チャネル効果を生じさせることな(実現できる
ようにした半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which fine trench isolation can be realized without causing a narrow channel effect.

〔従来の技術〕[Conventional technology]

第2図(a)、 (b)はそれぞれ従来の半導体装置を
示す断面図、第2図(C)は第2図(alのl1c−1
1c領域を示す平面図である。この図において、■はp
−型シリコン半導体基板、2は前記シリコン半導体基板
1表面に形成された溝、3は前記溝2中に埋め込まれた
絶縁膜(例えばシリコン酸化膜)、4はシリコン基板表
面の前記溝2の開口部周辺(第2図(a)参照)、ある
いは:a2の周辺全域(第2図(b)参照)に形成され
たp゛型不純物領域、5はシリコン半導体基板1上に形
成されたゲート絶縁膜、6はゲート絶縁膜5上に形成さ
れゲート電極及び配線となる多結晶シリコン膜、7はシ
リコン半導体基板1表面に形成されソース、ドレイン領
域となるn+型不純物領域である。
2(a) and 2(b) are cross-sectional views showing conventional semiconductor devices, respectively, and FIG. 2(C) is 11c-1 of FIG. 2(al).
It is a top view which shows area 1c. In this figure, ■ is p
- type silicon semiconductor substrate, 2 is a groove formed on the surface of the silicon semiconductor substrate 1, 3 is an insulating film (for example, a silicon oxide film) embedded in the groove 2, and 4 is an opening of the groove 2 on the surface of the silicon substrate. 5 is a gate insulating region formed on the silicon semiconductor substrate 1. A polycrystalline silicon film 6 is formed on the gate insulating film 5 and serves as a gate electrode and wiring, and 7 is an n+ type impurity region formed on the surface of the silicon semiconductor substrate 1 and serves as a source and drain region.

このような半導体装置では、シリコン半導体基板表面に
形成されたp゛型不純物t=IJjI4の働きにより、
素子間の電気的な分離を良好に行なうとともに、さらに
ゲート電極6のチャネル方向即ち分#領域3に沿う方向
の電気的分離をも良好に行ない、これによりトランジス
タのソース、ドレイン間の電気的分離が可能となってい
た。
In such a semiconductor device, due to the action of the p-type impurity t=IJjI4 formed on the surface of the silicon semiconductor substrate,
In addition to providing good electrical isolation between elements, good electrical isolation is also provided in the channel direction of the gate electrode 6, that is, in the direction along the dividing region 3, thereby improving the electrical isolation between the source and drain of the transistor. was possible.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来の半導体装置では、素子間及びソース
、ドレイン間を電気的に分離するために、シリコン基板
表面にp゛不純物領域4を形成していたが、この不純物
領域4がトランジスタのゲート電極の下にも形成されて
いるため、トランジスタのゲート幅が実質上狭くなり、
トランジスタの闇値電圧が高くなるという問題点があっ
た。
In the conventional semiconductor device as described above, a p impurity region 4 is formed on the surface of the silicon substrate in order to electrically isolate between elements and between the source and drain. Since it is also formed under the electrode, the gate width of the transistor is effectively narrowed.
There was a problem in that the dark voltage of the transistor became high.

この発明は、上記のような問題点を解決するためになさ
れたもので、トランジスタのゲート幅を実質上狭くする
ことなく、良好な電気的分離特性を得ることができる半
導体装置を得ることを目的としている。
The present invention was made in order to solve the above-mentioned problems, and aims to provide a semiconductor device that can obtain good electrical isolation characteristics without substantially narrowing the gate width of a transistor. It is said that

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、シリコン半導体基板表面
に形成された溝に該半導体基板と同一の導電型の半導体
層を埋め込んで、素子間を電気的に分離したものである
In the semiconductor device according to the present invention, a semiconductor layer of the same conductivity type as the semiconductor substrate is embedded in a groove formed on the surface of a silicon semiconductor substrate to electrically isolate elements.

〔作用〕[Effect]

この発明においては、シリコン半導体基板表面に形成さ
れた溝に該半導体基板と同一の導電型の半導体層を埋め
込んで、素子間を電気的に分離するようにしたから、不
純物がトランジスタのチャネル領域へ食み出すのを抑え
ることができ、これによりチャネル幅の狭いトランジス
タを形成した場合でも、闇値電圧の上昇を防ぐことがで
きる。
In this invention, a semiconductor layer of the same conductivity type as that of the semiconductor substrate is buried in a groove formed on the surface of a silicon semiconductor substrate to electrically isolate the elements, so that impurities enter the channel region of the transistor. Protrusion can be suppressed, and thereby even when a transistor with a narrow channel width is formed, an increase in dark value voltage can be prevented.

〔実施例〕〔Example〕

以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)はこの発明の一実施例による半導体装置を
示す断面図、第1図(C)は第1図(a)のIc−IC
領域を示す平面図である。この図において、第2図と同
一符号は同一部分を示し、p−型シリコン基板1表面に
形成された溝(シリコン溝)2には、従来絶縁膜3が埋
め込まれていたが、この本装置では、シリコン半導体基
板1と同じ導電型つまりp型の多結晶シリコン膜(半導
体層)8が埋め込まれている。
FIG. 1(a) is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 1(C) is an Ic-IC of FIG. 1(a).
FIG. 3 is a plan view showing the area. In this figure, the same reference numerals as those in FIG. Here, a polycrystalline silicon film (semiconductor layer) 8 of the same conductivity type as the silicon semiconductor substrate 1, that is, p-type, is embedded.

次に作用効果について説明する。Next, the effects will be explained.

本実施例装置ではp−型半導体基板表面に形成された溝
2に、p型名結晶シリコン膜8を埋め込んで素子間を分
離したので、従来の半導体装置と同じ素子分離特性が得
られるだけでなく、トランジスタのチャネル領域へのp
型不純物の食み出しをなくすことができ、このため、ト
ランジスタのゲート幅は素子分離領域で決まる長さとな
り、特に短いゲート幅が要求されるトランジスタにおい
ても、闇値電圧が上昇するのを防ぐことができる。
In the device of this embodiment, a p-type crystalline silicon film 8 is buried in the groove 2 formed on the surface of the p-type semiconductor substrate to isolate the elements, so that the same element isolation characteristics as the conventional semiconductor device can be obtained. p to the channel region of the transistor.
It is possible to eliminate the protrusion of type impurities, and for this reason, the gate width of the transistor is set to the length determined by the element isolation region, which prevents the dark voltage from increasing even in transistors that require a particularly short gate width. be able to.

又、従来の半導体装置のように絶縁膜で埋め込むもので
は、不純物領域をシリコン溝周辺に形成しなければなら
なかったが、本装置ではシリコン溝2に多結晶シリコン
を埋め込むため、不純物形成工程を削除することができ
、製造工程を短縮できる。
In addition, in conventional semiconductor devices that are filled with an insulating film, an impurity region had to be formed around the silicon groove, but in this device, polycrystalline silicon is buried in the silicon groove 2, so the impurity formation process is not necessary. This can shorten the manufacturing process.

なお、上記実施例では、シリコン溝2を全てp型子結晶
シリコンで満たした場合を示したが、このp型子結晶シ
リコンはp−型シリコン半導体基板1と接する領域での
み効力を発揮するため、第1図(b)に示すようにシリ
コン溝2の側壁部及び底面部のみにp型名結晶シリコン
膜8を形成し、シリコン溝2の残りの部分には従来通り
絶縁膜3を埋め込みシリコン半導体基板表面を平坦にし
ておくようにしてもよい。
In the above embodiment, the silicon groove 2 is entirely filled with p-type child crystalline silicon, but this p-type child-crystalline silicon is effective only in the region in contact with the p-type silicon semiconductor substrate 1. As shown in FIG. 1(b), a p-type crystalline silicon film 8 is formed only on the sidewalls and bottom of the silicon groove 2, and the remaining part of the silicon groove 2 is filled with an insulating film 3 as before. The surface of the semiconductor substrate may be kept flat.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明にかかる半導体装置によれば、
シリコン半導体基板表面に形成された溝に、該半導体基
板と同一の導電型の半導体層を埋め込んで、素子間を電
気的に分離したので、シリコン溝を素子分離に利用した
ときに生じる不純物のトランジスタのチャネル領域への
食み出しを抑えることができ、かつ良好な素子分離特性
が得られるという効果がある。
As described above, according to the semiconductor device according to the present invention,
A semiconductor layer of the same conductivity type as that of the semiconductor substrate is embedded in a groove formed on the surface of a silicon semiconductor substrate to electrically isolate the elements. Therefore, impurity transistors generated when the silicon groove is used for element isolation are eliminated. This has the effect of suppressing the protrusion into the channel region and providing good element isolation characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例による半導体装置を説明する
ための図、第2図は従来の半導体装置を説明するための
図である。 図において、1はp−型シリコン半導体基板、2は半導
体基板表面に形成された溝、3.5はシリコン酸化膜、
6.8は多結晶シリコン膜、7はn゛不純物領域である
。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional semiconductor device. In the figure, 1 is a p-type silicon semiconductor substrate, 2 is a groove formed on the surface of the semiconductor substrate, 3.5 is a silicon oxide film,
6.8 is a polycrystalline silicon film, and 7 is an n impurity region. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板表面に形成され素子間を分離するため
の溝を有する半導体装置において、 上記溝内に上記半導体基板と同一の導電型を有する半導
体層を埋め込んで、素子間を電気的に分離したことを特
徴とする半導体装置。
(1) In a semiconductor device having a groove formed on the surface of a semiconductor substrate for isolating elements, a semiconductor layer having the same conductivity type as the semiconductor substrate is embedded in the groove to electrically isolate the elements. A semiconductor device characterized by:
(2)上記半導体層は、上記溝の内壁面に沿って形成さ
れた半導体膜であり、上記溝は該半導体膜とその上に充
填された絶縁膜とで満たされていることを特徴とする特
許請求の範囲第1項記載の半導体装置。
(2) The semiconductor layer is a semiconductor film formed along the inner wall surface of the trench, and the trench is filled with the semiconductor film and an insulating film filled thereon. A semiconductor device according to claim 1.
JP1700187A 1987-01-27 1987-01-27 Semiconductor device Pending JPS63185040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1700187A JPS63185040A (en) 1987-01-27 1987-01-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1700187A JPS63185040A (en) 1987-01-27 1987-01-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63185040A true JPS63185040A (en) 1988-07-30

Family

ID=11931770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1700187A Pending JPS63185040A (en) 1987-01-27 1987-01-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63185040A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02295153A (en) * 1989-05-09 1990-12-06 Mitsubishi Electric Corp Semiconductor device
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02295153A (en) * 1989-05-09 1990-12-06 Mitsubishi Electric Corp Semiconductor device
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit
US5436488A (en) * 1993-09-30 1995-07-25 Motorola Inc. Trench isolator structure in an integrated circuit

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