JPH02295153A - Semiconductor device - Google Patents

Abstract

PURPOSE:To alleviate a stress generated at the time of heat treatment and to prevent a crystal defect from generating by forming a thermal stress alleviating film between a semiconductor substrate and an isolating insulating film. CONSTITUTION:A groove 2 having a desired depth is formed on a region to be isolated of a p-type silicon substrate 1 by photolithography and anisotropic etching. Then, a polycrystalline silicon film 6 is formed as a film for alleviating a thermal stress between the substrate 1 and a silicon oxide film 4 to be buried therefrom by a chemical vapor growing method. After the thin polycrystalline silicon film except those formed at the bottom and sidewall of the groove 2 of the silicon 6 is removed, the film 4 is thickly deposited, and etched back to complete a groove buried isolation. This film 6 alleviates a stress generated due to the difference of thermal expansion coefficients of the substrate 1 and the film 4 in a later heat treating step thereby to prevent the crystal defect of the substrate.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a structure in which a groove is formed in a semiconductor substrate and an insulating film is buried in the groove to electrically isolate between elements or wells. This article relates to semiconductor devices. [Prior Art] A conventional semiconductor device of this type will be explained with reference to FIG. The isolation shown here is achieved by chemical vapor deposition (.CV) in a trench formed in a silicon substrate.
D method) is used to embed a silicon oxide film.
It is called the BOX method (Buried OXide method). Furthermore, the example shown in FIG. 3 shows the isolation of an n-channel MOS transistor element that is not formed on a p-type silicon substrate. That is, on the p-type silicon substrate 1,
A groove (trench) of desired depth is formed in the region where isolation is to be formed by photolithography and anisotropic etching.
After forming the trench 2, a channel cutting layer is formed over the bottom and sidewalls of the trench 2 so that the n+ layer 1O and the n+ layer 1l of adjacent n-channel MOS transistor elements do not form a channel under the isolation region. A p-type impurity layer 3 is formed by implanting boron ions. Thereafter, a silicon oxide film 4 is deposited thickly including the inside of the trench 2 by chemical vapor deposition (CVD), and then this silicon oxide film 4 is planarized by an etch-back method to fill the trench. Complete M5. [Problems to be Solved by the Invention] Conventional semiconductor devices, particularly semiconductor devices manufactured by the BOX method, have a structure in which a silicon oxide film 4 is directly embedded in a trench 2 formed in a silicon substrate 1 by a CVD method. Therefore, during the heat treatment after separation formation, stress is generated due to the difference in thermal expansion coefficient between the silicon substrate 1 and the silicon oxide film 4, which induces crystal defects in the silicon substrate 1 and causes abnormal leakage current in the semiconductor device. There was a problem in that it caused This invention was made to solve the above problems, and it does not cause crystal defects in the semiconductor substrate.
The purpose of this invention is to provide a semiconductor device with a trench-buried isolation structure in which no abnormal leakage current occurs in the device. [Means for Solving the Problems] A semiconductor device according to the present invention has a trench-embedded isolation structure in which an isolation insulating film is embedded in a trench formed on a semiconductor substrate, wherein the semiconductor substrate and the isolation A thermally stressed Mfli film is formed between the insulation film and the insulation film. [Function] The thermal stress buffer film of the present invention alleviates the stress caused by the difference in thermal expansion coefficient between the semiconductor substrate and the isolation insulating film in the subsequent heat treatment process, prevents the occurrence of crystal defects in the semiconductor substrate, and protects the semiconductor substrate. Prevent abnormal leakage current from being induced in the device. [Embodiment] FIG. 1 shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention. , a polycrystalline silicon film is formed as a film to buffer the stress generated by heat treatment. Note that, like the conventional example, this example also uses an n-channel MO formed on a p-type silicon substrate.
The separation of S-type transistor elements will be explained. That is, in a region of a p-type silicon substrate 1 where isolation is to be formed, a trench 2 of a desired depth is formed by photolithography and anisotropic etching. Next, a polycrystalline silicon film 6 is formed by chemical vapor deposition (CVD) as a film for buffering thermal stress between the silicon substrate 1 and the silicon oxide film 4 to be buried. , the groove of the polycrystalline silicon film 6 (
After removing the polycrystalline silicon thin film other than that formed on the bottom and sidewalls of trench 2, a thick silicon oxide film 4 is deposited. Thereafter, this silicon oxide film 4 is planarized by the etch-nochinoku-soki method to complete trench-filling isolation. Note that the p-type impurity layer 3 for channel cut is formed by injecting boron ions into the bottom and sidewalls of the trench 2 within the polycrystalline silicon I [6 or across both the polycrystalline silicon film 6 and the silicon substrate 1]. It is formed by injecting. Furthermore, in order to perfect the insulation isolation of the semiconductor device shown in FIG. 1, thermal stress #lI! Consider forming an insulating film in the vicinity of the surface of the polycrystalline silicon film 6 for protection. Here, the surface portion of the semiconductor device shown in FIG. 1 is wet oxidized. At this time, the polycrystalline silicon film 6 formed for thermal stress buffering has a higher oxidation rate than the silicon substrate l! ．． This is about 5 to 3 times faster, so even if the oxide film formed on the surface is later removed, the silicon oxide film 7 remains near the surface of the polycrystalline silicon film 6 (see FIG. 2). In the above example, a polycrystalline silicon film was formed as a thermal stress buffer film, but an amorphous silicon film may also be formed.Also, in the above example, an n-channel MOS type Although the isolation of transistor elements has been described, it can also be applied to isolation between other elements or well isolation. [Effects of the Invention] As described above, according to the present invention, in the trench-embedded isolation structure, the isolation insulator buried with the semiconductor substrate Since a thermal stress buffer film is provided between the film and the film, the stress generated during heat treatment can be alleviated, resulting in highly reliable semiconductor devices that do not create crystal defects in the semiconductor substrate and do not allow leakage current to flow. There are benefits to be gained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a semiconductor device according to another embodiment of the invention, and FIG. 3 is a sectional view showing a conventional semiconductor device. be. In the figure, 1 is a p-type silicon substrate, 2 is a trench,
3 is a p-type impurity layer, 4 is a CVD silicon oxide film, 6 is a polycrystalline silicon film, and 7 is a silicon oxide film.

Claims (1)

[Claims] In a semiconductor device in which an isolation insulating film is embedded in a groove formed in a semiconductor substrate, a thermal stress buffer film is formed between the semiconductor substrate and the isolation insulating film for buffering stress caused by heat treatment. A semiconductor device characterized by: