JPS63184844A - Data processing system - Google Patents

Abstract

PURPOSE:To select two methods as a debugging means by designating the parallel execution control mode or the non-parallel execution control mode independently. CONSTITUTION:If the parallel execution control mode, namely, '0' is set to a static mode control indication set register 4-1 by an instruction 1, the non- parallel execution control mode, namely, '1' is set to a dynamic mode control indication set register 4-2 by an instruction 2 and the output of an OR gate 5 goes to '1', and instructions 3 and 4 are subjected to non-parallel execution control. When the instruction 3 is set to an adder executing instruction register 14-1 at a timing '0', an operation executing part 11 starts to add the 0th elements read out from vector registers 12 at a timing '1' and successively adds vector elements hereafter and adds the last elements at a timing 128 and informs resource operation information 9 that vector registers 12 and an adder 13-1 used by the instruction 3 are available. Static mode control indication set is designated to the register 4-2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system that executes a plurality of arithmetic operations in parallel in time.

[Conventional technology]

The advantage of a data processing system that performs parallel execution of arithmetic processing is that processing time can be shortened by effectively utilizing resources. However, even if the same program is executed, the parts that are executed in parallel each time are different, so if there is an error in the program, the error location in the program may be reported differently each time the program is executed. The disadvantage is that it is difficult to debug. Therefore, conventionally, as described in Japanese Patent Publication No. 61-22818, there is a parallel execution control mode in which multiple instructions are executed temporally in parallel, and a non-parallel execution control mode in which execution of the next instruction is started after waiting for the execution of the preceding instruction. A mode control instruction setting register is provided for specifying which mode is selected by the program, and when debugging, the mode control instruction setting register is configured based on the result written in advance by the program in the mode control instruction setting register. The method used was to specify the mode and control non-parallel execution.

[Problem that the invention seeks to solve]

In the conventional technology described above, it was possible to provide the user with only one of the following two methods as a debugging means.

One is to embed an instruction specifying non-parallel execution in the mode control instruction setting register in the part of the program that you want to debug, and embed an instruction specifying parallel execution in the mode control instruction setting register in other parts. This is a method of controlling the execution of parts of a program in a non-parallel manner. This method has the advantage of shortening the program processing time, but the disadvantage is that it requires detailed instructions to be inserted in advance at the parts of the program where non-parallel execution control is desired, and it takes a lot of effort to modify the program. There is. Particularly if the program uses a high-level language, it is necessary to recompile the program each time the program is modified, further increasing the effort required for modification.

The other method is to control non-parallel execution of the entire program to be executed by specifying non-parallel execution in the above mode control instruction setting register via a program such as O8 without modifying the program itself. It is. This method has the advantage that it does not take much effort to modify the program, but has the disadvantage that the program processing time increases.

Both methods have advantages and disadvantages, but with the above conventional technology,
It has not been possible to provide both of the above debugging methods to the user and allow the user to select one of them. This is because some programs contain a mixture of parts for which parallel execution control is instructed and parts for which non-parallel execution control is instructed.

If the user wants to control non-parallel execution of the entire program without modifying the program, even if the user specifies this in the mode control instruction setting register through a program such as O8, the parallel execution embedded in the program to be executed will not be possible. This is because the contents of the mode control instruction setting register are rewritten in the portion for which control is instructed, and parallel execution is controlled.

An object of the present invention is to provide both of the above methods as debugging means, and to enable the user to select the method he or she wishes to use.

[Means for solving problems]

The above purpose is to provide two parts as the mode control instruction setting register that can each independently specify a parallel execution control mode or a non-parallel execution control mode, and to set at least one of the two parts of the mode control instruction setting register to a non-parallel execution control mode. When the execution control mode is specified, non-parallel execution control is performed, and when the parallel execution control mode is specified in both of the two parts of the mode control instruction setting register, parallel execution control is performed. This is achieved by

[Effect]

Set one of the two parts of the above mode and control instruction setting register to the static mode control instruction setting register (or register)
, the other is called the dynamic mode control instruction setting register (or D register) for debugging.

Either of the above methods can be used as shown below.

When using a method to dynamically control non-parallel execution of partial parts of a program, instruct the static mode control instruction setting register to specify the parallel execution control mode using a program such as O8, and then Insert an instruction to specify in the behavioral mode control instruction setting register in the part you want to control execution, compile again if necessary, and run the program. Only the parts for which the mode is specified are dynamically controlled for non-parallel execution.

On the other hand, when using a method to statically control non-parallel execution of the entire program, two parts are provided as the mode control instruction setting register, so in a program such as O8, the static mode control instruction setting register is used to control non-parallel execution. If you run the program by instructing to specify the mode, even if there is a part of the program that specifies the parallel execution control mode in the above dynamic mode control instruction setting register, the non-parallel execution control mode will be specified. Even if there are some parts of the program, the entire program is statically controlled for non-parallel execution.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

. FIG. 1 shows the configuration of a vector processor that is an embodiment of the present invention.

In Figure 1, 1 is the memory where the program is stored, 2 is the instruction fetch unit, 3 is the decoder, 4 is the mode control instruction setting register, and 4-1 of these indicates the non-parallel execution control mode when its value is 1. A static mode control instruction setting register (S register) that indicates the parallel execution control mode when its value is O.

4-2 is a dynamic mode control instruction setting register (D register) that displays non-parallel execution control mode when its value is 1, and displays parallel execution control mode when its value is 0; 5 is an OR gate; 6 7 is a control unit for the upper arithmetic execution start determining unit; 8 is an instruction register; 9 is a control unit for the upper arithmetic execution start determining unit; 10 is the execution instruction information that reflects the presence or absence of an instruction being executed in the arithmetic execution unit, and 11 is the arithmetic execution information. 12-4.12-2, . . . are vector registers, 13-1.13-2.・・・・・・
are arithmetic units, 14-1 and 14-2, respectively.・・・・・・
. each represents an executing instruction register corresponding to the above-mentioned arithmetic unit.

When executing a program, the instruction fetch unit 2 reads an instruction from the memory 1, the decoder 3 decodes the read instruction, and the decoded instruction is stored in the mode control instruction setting register 4 as a parallel execution control mode or a non-parallel execution control mode. If the instruction specifies an execution control mode, a value of 0 or 1 indicating the specified mode is set in the mode control instruction setting register 4, and if the decoded instruction is an operation instruction, the decoded instruction is used as the instruction. Set in register 8.

The OR gate 5 is connected to the static mode control instruction setting register 4-
If the non-parallel execution control mode, that is, 1 is specified in at least one of the static mode control instruction setting register 4-2 and the static mode control instruction setting register 4-2, 1 indicating the non-parallel execution control mode is output. -1 to both dynamic mode control instruction setting registers 4-2 for parallel execution control mode, that is, 0.
If , it outputs 0 indicating the parallel execution control mode, and sends it to the calculation execution start determining section 6.

In the calculation execution start determining unit 6, the control unit 7 controls the OR gate 5.
, the contents of the instruction register 8 set by the decoder 3, the resource operation information 9, and the currently executing instruction information 10, the contents of the instruction register 8 are transferred to the operation execution unit 11.
It is determined whether or not to send it to the execution instruction register 14 inside.

When the arithmetic execution unit 11 has an instruction set in the executing instruction register from the arithmetic execution start determining unit 6.

Arithmetic processing is executed according to the instructions of the set instruction.

Specifically, for example, data is read from the vector register 12 specified by the set instruction, and an operation is executed by the arithmetic unit 13 specified by the set instruction.
Processing such as writing the operation result into the vector register 12 specified by the set instruction is performed.

The arithmetic execution unit 11 reports from time to time to the resource operation information 9 which of the vector registers 12 and arithmetic units 13 can be used by other instructions, and determines whether or not there is an instruction being executed by the arithmetic execution unit 11. is reported to the currently executing instruction information 10. The control unit 7 refers to the resource operation information 9 and the currently executing instruction information 10 obtained as described above, and registers the instruction register 8.
It is determined whether or not the contents of are to be sent to the executing instruction register 14 in the arithmetic execution unit 11.

Specifically, when the control unit 7 receives 0 from the OR gate 5, that is, when the parallel execution control mode is specified,
It refers to the resource operation information 9, waits until the vector register 12 and the arithmetic unit 13 used by the instruction in the instruction register 8 become available, and then transfers the contents of the instruction register 8 to the arithmetic unit 13 used by that instruction. It is sent to the corresponding executing instruction register 14. Therefore, the calculation execution unit 11
In this case, the arithmetic processing of multiple instructions is executed temporally in parallel.

On the other hand, when the control unit 7 receives 1 from the OR gate 5, that is, when the non-parallel execution control mode is specified, the control unit 7 refers to the resource operation information 9 and registers a vector register to be used by the instruction in the instruction register 8. 12 and the arithmetic unit 13 become available, and then refer to the executing instruction information 10 and wait until there are no more instructions being executed in the arithmetic execution unit 11. It is sent to the executing instruction register 14 corresponding to the arithmetic unit 13 to be used. Therefore, in the arithmetic execution unit 11, the execution of the arithmetic processing of a certain instruction is started after the execution of the previous instruction is completed.

In the embodiment of the above configuration, a method for controlling non-parallel execution only of the part of the program that is desired to be controlled for non-parallel execution, and a method for statically controlling non-parallel execution of the entire program are shown in FIGS. 2, 3 and 4. This will be explained using figures.

Fig. 2 shows an example of the given program, Fig. 3 shows a timing chart when program 15-1 shown in Fig. 2 is executed, and Fig. 4 shows a timing chart when program 15-2 shown in Fig. 2 is executed. The timing chart is shown below.

In FIG. 2, instructions ■ and ■ instruct the static mode control instruction setting register 4-1 or dynamic mode control instruction setting register 4-2 to specify parallel execution control mode or non-parallel execution control mode, respectively. , instruction ■, ■ is a vector addition instruction, instruction ■.

■ is a vector multiplication instruction.

By using the program 15-1 shown in FIG. 2, it is possible to dynamically control the non-parallel execution of only the portion of the program that is desired to be controlled for non-parallel execution. The vector length of the vector operation is 128, and the operation unit 13-1 is an adder, and the operation unit 13
FIG. 3 will be explained below using -2 as a multiplier.

The instruction ■ specifies the parallel execution control mode, that is, O, in the static mode control instruction setting register 4-1, and the instruction ■ specifies the non-parallel execution control mode, that is, 1, in the dynamic mode control instruction setting register 4-2. The output of gate 5 is 1
Therefore, instructions ■ and ■ are executed in a non-parallel manner. When the instruction ■ is set in the adder execution instruction register 14-1 at timing O, the arithmetic execution unit 11 starts adding the O-th element read from the vector register 12 at timing 1, and then sequentially adds the vector elements. Perform the addition of .

At timing 128, the final element is added, and the resource operation information 9 reports that the vector register 12 and adder 13-1 used in the instruction ① are now available, and the execution instruction information 10 indicates the operation. It is reported that there are no more instructions being executed by the execution unit 11. Based on the resource operation information 9 and the currently executing instruction information 10, the control unit 7 transfers the instruction ■ to the multiplier executing instruction register 10- at timing 130.
2, and vector multiplication is performed at timings 131-258.

Since the parallel execution control mode, that is, O, is specified in the static mode control instruction setting register 4-2 by the instruction ■, and O is specified in both the mode control instruction setting registers 7, the output of the OR gate 5 becomes 0, and the instructions ■ and ■ is controlled in parallel. At timing 401, adder execution instruction register 14-
When the instruction ■ is set to 1, the calculation execution unit 11 starts vector addition at timing 402, and the force control unit 7 refers to the resource operation information 9 and sets the vector register 12 and calculation unit 13 used in the instruction ■. can be used, the instruction ■ is set in the multiplier execution instruction register 14-2 at the same timing, and the operation execution unit 11 uses the timing 403.
Vector multiplication starts at timing 529, vector addition ends at timing 530, and vector multiplication ends at timing 530.

The program 15-2 shown in FIG. 2 allows static non-parallel execution control of the entire program. The program 15-2 differs from the program 15-1 only in that the non-parallel execution control mode is specified in the static mode control instruction setting register in the instruction (2).

The instruction ■ specifies the non-parallel execution control mode, that is, 1, in the static mode instruction setting register 4-1, and the instruction ■ specifies the non-parallel execution control mode, that is, 1, in the dynamic mode instruction setting register 4-2, so the OR gate is activated. The output of 5 becomes 1, and the instructions ■ and ■ are controlled for non-parallel execution. When the instruction ■ is set in the adder execution instruction register 10-1 at timing O, the arithmetic execution unit 11 performs vector addition at timings 1 to 128, and the control unit 7 waits for the end of the vector addition before issuing the instruction ■. It is set in the multiplier execution instruction register 14-2 at timing 130, and vector multiplication is performed at timings 131-258.

The parallel execution control mode, that is, 0, is specified in the dynamic mode instruction setting register 4-2 by instruction (2).

Since the static mode control instruction setting register 4-1 is specified, the output of the OR gate 5 becomes 1, and the instructions (2) and (2) are controlled to be executed in a non-parallel manner. When the instruction ■ is set in the adder execution instruction register 14-1 at timing 401, the arithmetic execution unit 11 performs vector addition at timings 402 to 529, and the control unit 7 waits for the end of the vector addition before issuing the instruction ■. At timing 531, the multiplier execution instruction register 14
-2, and vector multiplication is performed at timings 532-659.

As mentioned above, 2 is set as the mode control instruction setting register 7.
Therefore, if a program instructs the static mode control instruction setting register 4-1 to specify the non-parallel execution control mode and executes the program, the dynamic mode control instruction setting register 4-1 in the program can be executed. 2, even if there is a part that specifies parallel execution control mode or a part that specifies non-parallel execution control, the entire program is statically controlled for non-parallel execution.

〔Effect of the invention〕

According to the present invention, when debugging a program by controlling non-parallel execution in a data processing system that performs parallel execution of arithmetic processing, the non-parallel execution is dynamically controlled only for the part of the program that is desired to be controlled. There are two methods: one is to shorten the processing time, and the other is to statically control non-parallel execution of the entire program to be executed, thereby saving the effort of modifying the program.
This has the effect of providing an environment in which the user can select one of two methods.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an example of a given program, and FIGS. 3 and 4 are timing charts when the program shown in FIG. 2 is given. 1...Memory, 2...Instruction fetch unit, 3...Decoder. 4... Mode control instruction setting register, 5... OR gate, 6... Arithmetic execution start determining unit, 7... Control unit,
8... Instruction register, 9... Resource operation information, 1
0... Executing instruction information, 11... Arithmetic execution unit, 12
...Vector register, 13...Arithmetic unit, 1
4...Executing instruction register, 7-・7 Agent Patent attorney Katsuo Ogawa J

Claims (1)

[Claims] 1. Equipped with multiple arithmetic units, configured so that the arithmetic units can perform arithmetic processing in parallel in time, and operands can be input to the arithmetic units when executing multiple instructions. A parallel execution control mode in which the multiple instructions are executed in parallel in time by waiting for the execution of the instruction, and a non-parallel execution control mode in which the instructions are executed by waiting for the preceding instruction among the multiple instructions to be executed. a calculation start determining unit having means capable of operating in the mode of Accordingly, in a data processing system in which the arithmetic execution start section performs execution control, two parts are provided as the mode control instruction setting registers, each of which can independently specify the parallel execution control mode or the non-parallel execution control mode, and The calculation start determining section is set to 2 of the mode control instruction setting register.
When the above-mentioned non-parallel execution control mode is specified in at least one of the two parts, non-parallel execution control is performed, and when the parallel execution control mode is specified in both of the two parts of the mode control instruction setting register, A data processing system characterized by having means for controlling parallel execution.