JPS63182737A - High-speed arithmetic system for specific data pattern - Google Patents

Abstract

PURPOSE:To extremely increase the arithmetic processing speed by making one of two arithmetic units perform a normal arithmetic processing and the other arithmetic unit perform a high-speed arithmetic processing accordant with a specific data pattern and selecting the results of these arithmetic operations. CONSTITUTION:A 1st arithmetic unit 3 obtains a desired arithmetic result when the desired input operand data is not equal to a specific data pattern. A 2nd arithmetic unit 4 obtains a desired arithmetic result when said input operand data is equal to a specific data pattern. An arithmetic control device 5 functions to ensure the synchronizing and parallel operations of both device 3 and 4. The device 5 validates the arithmetic result of the device 3 when the operand data is not equal to the specific data pattern, then to validate the arithmetic result of the device 4 when the operand data is equal to the specific data pattern. In such a way, the arithmetic processing speed can be extremely increased with the specific data pattern without deteriorating the arithmetic performance that is caused with no specific data pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic acceleration system having a plurality of arithmetic units.

BACKGROUND OF THE INVENTION In recent years, in the field of large-scale information processing devices, functions have been decentralized, for example, by separately providing arithmetic circuits for addition and subtraction and arithmetic circuits for multiplication and division, resulting in an optimized configuration for six arithmetic circuits. by doing.

There is a trend toward shortening machine cycles.

Problems to be Solved by the Invention However, with this method, for example, when performing multiplication, arithmetic circuits for addition and subtraction are not used at all, resulting in waste.

On the other hand, in many cases of multiplication used in address indexing, etc., the multiplier can be expressed as a number (n is a positive integer) or has a very small value, and these multiplications require a shift circuit rather than a multiplication circuit. In many cases, results can be obtained more quickly by using an adder circuit or a combination of an adder circuit and a shift circuit.7 The present invention was made to solve the above-mentioned problems inherent in the conventional technology. Therefore, it is an object of the present invention to provide a new system for accelerating calculations that can extremely speed up calculations for special data patterns without causing performance deterioration when the data patterns are not special. .

Means for Solving the Problems In order to achieve the above object, the system for accelerating arithmetic operations based on a specific pattern according to the present invention is provided with a system for accelerating arithmetic operations based on a specific pattern according to the present invention. a first arithmetic device which obtains a desired arithmetic result when the operand data is input and which obtains a desired arithmetic result when the operand data is a specific data pattern; and an arithmetic control device that controls the arithmetic devices to operate synchronously and in parallel, and the arithmetic control device controls the arithmetic result of the first arithmetic device when the operand data is not a specific data pattern. is set to be valid, and when it is a specific data pattern, control is performed so that the calculation result of the second calculation device is valid.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 1 is a block diagram showing the arithmetic unit shown in FIG. 7 in more detail.

In FIG. 1, a general-purpose register group l consists of a plurality of general-purpose registers each holding operand data. Memory memory is the main storage device.

For example, the calculation device 3 performs 3 kobits in 1 machine cycle)X
This is a multiplication circuit that performs Q-bit multiplication, and 32-bit x 32-bit multiplication can be performed in one machine cycle. As shown in Figure 2, the arithmetic circuit has an adder axis that can perform addition/subtraction of 3-bits and 3-bits in xti machine cycles, and a shift operation in the range of Q to 3 cobits left and right that can be performed in 1 machine cycle. It consists of a 3-bit shift circuit 3 and a pattern check circuit 11 which checks the pattern of %J-bit data to see if it is -1 (n is an integer from 0 to 31). The input data for the pattern check circuit is a+ xQ.
When it is n, the arithmetic and control unit informs that fact! The K ``n'' value is input to the shift circuit 3 as a shift amount. The arithmetic control device 3 controls the arithmetic devices J and D to always operate synchronously and in parallel, and controls the adder 4 (-) for addition and subtraction, the shift circuit II3 for shift operation, and the operation for 1 multiplication. It controls the use of each of the multiplication circuits in the device 3. Also, during multiplication, a check instruction is given to the pattern check circuit 'III, and if there is no notification from the pattern check circuit, the result obtained by the arithmetic device 3 is is written to the general-purpose register, and when the notification is received, the result obtained by the arithmetic unit 3 is written to the general-purpose register, and execution in the arithmetic unit 3 is terminated.

Next, the present invention will be explained in more detail using specific examples.

Now, let us take as an example the case where A is held in one of the general-purpose registers and 9B is held in the memory, and ``@AxB'' is performed and written to the general-purpose register.A.

B is expressed in 76 decimal A-/Jj? ? BDF B-θooootoo (=2) shall be.

First, in the first cycle, the arithmetic control unit j instructs the arithmetic unit 3 and da to read A from the general-purpose register group l and read B from the memo IJ and l, and in response to this, each operation The device takes in and holds A and B internally.In the C arithmetic unit 3, A is in register 1O, and register 4!
/ respectively hold B).

Next, in the first cycle, there is an arithmetic and control unit! Instructs the arithmetic bag fJ to start multiplication, also instructs the pattern check circuit in the arithmetic unit q to check, and also instructs the shift circuit to write O'' to the lower double bytes of the contents of the register.
It instructs the register aS to shift the t bytes of data marked with by the number of shifts supplied from the pattern check circuit to the left, and also instructs the register aS to receive the output of the shift circuit 3.

Since the content held in the pattern check circuit is 72, it notifies the arithmetic control unit 3 that the arithmetic operation can be performed in the arithmetic unit DA, and also sends a message to the shift circuit DA 3 as the number of bits to be shifted. Give II. The shift circuit <4J selects the register QO from these instruction contents.
The data held in K is shifted to the left by j bits and '37deBDF7Q' is output, which is taken into register IIS and held. In the 2nd co-cycle, the arithmetic unit DA can perform calculations. The arithmetic control unit f5, which received the notification,
At @j psi, execution of the arithmetic control unit 3 is stopped, and the data of the lower byte of the result held in the register lI& is stored. BDF00'' is written to the general-purpose register, and the register is also written to instruct the shift circuit lIj to write S byte data with 0'' appended to the upper byte of the contents of the register to the left in the same way as in the 8g cocycle. 4'j are respectively instructed to receive the output of the shift circuit 3. In response to this, the shift circuit 11. y is "0000"
00/, 3''' is output, and this is taken into Regimushi Tada 3.Finally, the upper double byte data of the result held in register R in the second cycle is ``oooooooi,
y" is written to the general-purpose register and the process ends.

If this multiplication is executed on the arithmetic unit 3, A,
It can be seen that a total of 70 cycles are required, including a cycle for fetching B, a cycle for multiplication, and a cycle for storing the result, and the present invention can speed up the process by 6 cycles.

As described in detail, according to the present invention, attention is paid to the fact that operations can be extremely simplified when the input operand is a special data pattern, and one arithmetic unit is made to perform normal operations, The other arithmetic unit performs high-speed processing suitable for special data patterns, and by selecting these as the arithmetic result, it is possible to perform very high-speed arithmetic operations on special data patterns without incurring performance deterioration when the data pattern is not a special data pattern. It is possible to convert

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
FIG. 1 is a block diagram showing the arithmetic unit shown in FIG. 1 in more detail. l...General-purpose/register group, co...memory, 3 and da...arithmetic unit, 5...arithmetic control unit, rabbit, nail, and q...register, IIJ...adder, IIJ
... shift) Do path, w... pattern check circuit

Claims (1)

[Scope of Claims] In an information processing device having a plurality of arithmetic units and an arithmetic control unit for controlling these units to operate synchronously and in parallel, when executing some predetermined operations, a first arithmetic unit that receives operand data and obtains a desired calculation result when the operand data is not a certain data pattern; and when the operand data is input and the operand data is the specific data pattern. and a second arithmetic unit that obtains a desired arithmetic result, and the arithmetic control unit includes:
When executing the several operations, if the operand data is not a specific data pattern, the result of the operation in the first arithmetic unit is valid, and if it is a specific data pattern, the operation result in the second arithmetic unit is validated. A system for accelerating calculations in a specific data pattern, characterized by controlling the results to be valid.