JPS6015770A - Vector data processor - Google Patents

Abstract

PURPOSE:To ensure the use of a vector register with high efficiency under a simple control by providing individually plural vector registers which can perform both writing and reading at a time via a vector data processor and write/ read address registers. CONSTITUTION:An OP code designates the multiplication to perform the instructions which designate vector registers VR0, VR1 and VR2 through an arithmetic result store operand part, the 1st operand part and the 2nd operand part respectively. Then the OP code designates the addition to deliver the instructions which designate VR3, VR0 and VR4 through the arithmetic result store operand part, the 1st operand part, the 2nd operand part respectively. Thus the accesses of the VR0 overlap each other. However the former instruction is equal to a writing action carried out by the control of a writing address register 11, and the latter instruction is equal to a reading action done by the control of a reading address register 21. Thus a simultaneous access is possible with both instructions. As a result, the latter instructions are started before the execution is through with the former instructions.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vector data processing bag that allows efficient use of vector registers.

Prior Art Taking a look at FIG. 1, the conventional vector data processing device has a main memory MM and a vector register vR.

Vector address register AR, and performance 1. Equipped with IHm. In vector data processing.

Vector data is loaded/stored between main memory MM and vector register VI(,), and element data strings are exchanged between vector register VW and arithmetic unit Al. Vector address register AR is an address register that indicates the storage location of element data in the vector register VIt.

Usually, several vector registers are provided, and each vector register holds a plurality of element data strings 5, for example, from the first element data to the 64th element data. For example, if eight vector registers are provided, vector register vl
l(There are 8 +.

There are eight vector address registers AR corresponding to each vector register VR.

When the vector register access request source accesses the i-th vector register VRi, the i-th vector address register ARi indicates the first element data to the 64th element data. However, since there is only one vector address register ARil in the vector register VRi, this access source on the open side cannot access the i-th vector register.

That is, with vector data processing decoration, for example, the main memory M
When loading vector data from M to the vector register VR and using this loaded data as input data to the arithmetic unit AL, the calculation is started after all vector data has been loaded, increasing speed. The disadvantage is that it cannot be achieved.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a vector data processing device that allows efficient use of vector registers.

The device of the present invention is a vector data processing device that includes a plurality of vector registers holding a plurality of elements and performs operations by sequentially accessing the elements in each vector register.

Multiple vector registers that can be written and read simultaneously, a write address register and T
The present invention is characterized in that a read address register is separately provided for each of the plurality of vector registers.

Examples of the invention Next, the present invention will be described and explained in detail with reference to the drawings.

Referring to FIG. 2, one embodiment of the present invention.

Push register 1-8, which holds data written to the vector register; 17'-include address register 11-18; successive address register 2128. Read data selection circuit 31-
39, read registers 41-49 that hold vector data read from vector registers, first arithmetic unit 51
．． Second arithmetic unit 52. Third computing unit 53, fourth computing!
'+54.61 to 68 digit write data selection circuit 61-
67, vector register VR.

The first to fourth arithmetic units correspond to, for example, a multiplier, an adder, a divider, and a logical arithmetic unit, respectively.

Write register 1 is connected to vector register VRa, and write register 2 is connected to vector register VR. Similarly, write register 3゜4.5, 6.7
and 8 are vector registers Vbird, VR,,V, respectively.
~, I am addicted to Tori, V Tori, and VR. Vector registers V, R, -V) can be written and read independently and simultaneously, and write address registers 11-18 and read address registers 21-
28, respectively. Vector register VR
The read data from o is each read data selection circuit 3l.
−=39. Although not shown in the drawing, the vector registers VR, -VR7 are also connected to the read data selection circuits 31-39 in the same way as the vector register VFL.

The escape registers 41-48 are the m output data selection circuits 31-
This register temporarily stores the read data selected at 38. The read registers 41 and 42 are connected to the first arithmetic unit,
Continuation registers 43 and 44 are connected to the second arithmetic unit, read registers 45 and 46 are connected to the third arithmetic unit, and read registers 47 and 48 are connected to the fourth arithmetic unit, respectively. The read register 49 is a register for temporarily storing the read data selected by the read data selection circuit 39 and storing it in the main memory. The calculation result of the first calculation unit 51 is supplied to write data selection circuits 61-68. Although not shown in the drawing, the second computing unit 52 and the third computing unit 5
3. Load data from the fourth arithmetic unit 54 and the main memory is also transferred to the write data selection circuit 61 in the same way as the first arithmetic unit 51.
−68 is given.

Referring to FIG. 3, a vector instruction consists of an operation code UP, an operation result storage operand section It l, a first operand section I (2), and a second operand section I (3). The vector instruction is specified in the first operand section. The contents of the specified vector register and the contents of the vector register specified by the second operand section are operated as specified by the UP code, and the operation result is written to the vector register specified by the operation result storage operand section. This is an instruction.

Next, the operation of one embodiment of the present invention will be explained in detail.

Referring to FIG. 4, the instruction ■, that is, the OP code specifies multiplication, and the operation result storage operand section stores VRo as
The operand part is VR, and the second operand part is VH.
Assume that the execution of the instructions specifying 2 has started. Vector register VRoO write address register 1
1. Vector register VR.

Read address register 22. Vector register V1'
112 subsequent address registers 231-j: each initialized to point to an ml element in the vector register. The first element of vector register vR1 specified by read address register 22 is:

The data is stored in the successive output register 41 via the read data selection circuit 31. At the same time, the first element of the vector register R7 specified by the read address register 23 is stored in the successive register 42 via the read data selection circuit 32, and the contents of the address registers 22 and 23 are changed to +1. and specifies the first step of the next element. The contents of read data registers 41 and 42 are input to first arithmetic unit 51, respectively. First computing unit 5
] outputs the operation result in 7 clocks, then 7
After the BLACK and ACK, the operation result is stored in the write register via the write data selection circuit 61. Further, at a second clock, 1 is set in the first element of the vector register Vf (.) specified by the write address register 31, and the contents of the write address register 11 are incremented by +1.

In the instruction ■ following the instruction ■ shown in FIG. 4, the Of' code specifies addition, the operation result storage operand part is VR3, and the first operand part is VIL. , the second operand part is l
, , i are the instructions specified respectively.

If the execution of instruction (2) has not finished, the vector register VR. This will result in duplicate access. However, the access to vector register VRo by instruction ■ is a vector data write operation under the control of write address register II, and the instruction to read vector data in vector register vR・0 by the first operand of instruction ■ continues. This is under the control of the address register 21. Therefore, simultaneous access is possible, and as shown in Figure 5, the instruction (2) is started without waiting for the completion of execution of the instruction (2).

That is, referring to FIG. 2 and FIG. 6, vector register VE, write address register 14 of vector register Vl(, read address register 25 of vector register VI), and read address register 21( of
l″t are initialized to point to the first element in the vector register, respectively.The first element data successively output from the vector register Va, and the write address register already pointing to the first element during a write operation, are initialized to point to the first element in the vector register. The first element data read from the readable vector register VRo is stored in read registers 43 and 44 via read data selection circuits 33 and 34, respectively, and is also stored in read address registers 21 and 44, respectively. The contents of 25 are incremented by 1. This relationship is shown in the 6th column.
This is timing a in the figure. Read registers 43 and 44
The first element data of 1 is inputted to the second arithmetic unit 52, and if the addition result is outputted in 5 clocks, the 1st element data is inputted to the second arithmetic unit 52.
It is input to the write register 4. Furthermore, at the next clock, the contents of the write register 4 are written to the first element data storage location pointed to by the write address register 14, and the contents of the scheduled address register 14 are incremented by 1.

In the present invention, while vector register v1 is also executing a write operation of 1, a read operation of the same vector register can be performed by a subsequent instruction;
)l・! Read j% and write operation e! to the same vector register by a subsequent instruction during the operation. It is clear that there could also be four lines.

Effects of the Invention The present invention has the advantage that by configuring the vector register so that writing and reading can be performed simultaneously, the vector register can be used efficiently for simple control.

[Brief explanation of drawings]

Figure 1 shows the general outline of the vector data processing equipment, Figure 2
3 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing the format of a vector instruction, FIG. 4 is a diagram showing the appearance of instructions, FIG. is a diagram showing element data processing. 1 to 6, 1-8--Write register, 11-18...Write address register, 21
-28...Read address register, 31-39...
...Read data selection circuit, 41-49...
Read register. 51...First arithmetic unit, 52...Second arithmetic unit. 53...Third arithmetic unit, 54...Fourth arithmetic unit, 61-68...Write data selection circuit,
Vl (・, -VI-L, ...... vector register. Z l Figure L3 Flash 4 Figure 4 order■ MtJly VFo, VKyy VA'2 Zenkin■ ρρI) I VkJ, Vlel, VF'd Mei 5
Figure L 6 Leap Time Procedure Amendment (Voluntary) 59.10. - zl Month, Day 1, Showa 1980, Incident Indication 1982 Patent Application No. 122681
No. 2, Name of the invention Vector data processing device 3, Relationship to the amended person case Applicant 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative Tadahiro Sekimoto 4, Agent ( (Contact information: Patent Department, NEC Corporation) 5. Column 6 of the detailed description of the invention in the specification to be amended and column 6 of the detailed description of the invention in the specification of the contents of the amendment will be corrected as follows. 1. The statement "1 Example" on page 4, line 13 has been corrected to "1 example."
I will correct it. Agent Patent Attorney Uchihara −. '・+'1-2 A

Claims (1)

[Scope of Claim] A vector data processing device that performs operations by sequentially accessing elements stored in each of a plurality of vector registers each holding a plurality of elements. Multiple vector registers that can be written and read simultaneously. A vector data processing device comprising: a plurality of convolution address registers corresponding to each of the plurality of vector registers; and a plurality of read address registers corresponding to each of the plurality of vector registers.