JPS63181473A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPS63181473A JPS63181473A JP1378687A JP1378687A JPS63181473A JP S63181473 A JPS63181473 A JP S63181473A JP 1378687 A JP1378687 A JP 1378687A JP 1378687 A JP1378687 A JP 1378687A JP S63181473 A JPS63181473 A JP S63181473A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- active layer
- silicon carbide
- film transistor
- xcx
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 22
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 25
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims abstract description 12
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 229910052799 carbon Inorganic materials 0.000 abstract description 4
- 239000000969 carrier Substances 0.000 abstract description 3
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 abstract description 2
- 230000005669 field effect Effects 0.000 abstract description 2
- 229910000077 silane Inorganic materials 0.000 abstract description 2
- 229910006992 Si1-xCx Inorganic materials 0.000 abstract 4
- 238000010030 laminating Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000005755 formation reaction Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 235000002020 sage Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
この発明は例えば薄膜トランジスタをスイッチ素子とし
て用いるアクティブ液晶表示素子に用いられる薄膜トラ
ンジスタに関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a thin film transistor used, for example, in an active liquid crystal display device using a thin film transistor as a switching element.
「従来の技術」
従来のこの種の薄膜トランジスタは、例えば第６図に示
すように、ガラスのような透明基板１１上に、互に分離
されてドレイン電極１）及びソース電極１３が形成され
、こｎ７らｒレイン電極１）及びソース電極１３間にわ
たって例えば水素化アモルファスシリコンａ−８ｉ：Ｈ
の活性層１４ カ基板１１上に形成され、その活性層１
４上に窒化シリコンＳ ｉＮｘなどのゲート絶縁膜１５
が形成され、そのゲート絶縁膜１５上にゲート電極１６
が形成さしていた。``Prior Art'' In a conventional thin film transistor of this type, for example, as shown in FIG. 6, a drain electrode 1) and a source electrode 13 are formed on a transparent substrate 11 such as glass and separated from each other. For example, hydrogenated amorphous silicon a-8i:H is applied between the n7 and r rain electrodes 1) and the source electrodes 13.
The active layer 14 is formed on the substrate 11, and the active layer 14 is formed on the substrate 11.
4, a gate insulating film 15 such as silicon nitride SiNx is formed.
is formed, and a gate electrode 16 is formed on the gate insulating film 15.
was forming.
このように従来においτは活性層１４としてａ−３ｉ
： Ｈを用いているため電界移動度が小さいため電流駆
動能力が低い。このため例えばアクテイブ液晶表示素子
における画素電極に対するスイッチ素子として用いた場
合にその動作速度を十分速くすることができず、またア
クティブ液晶表示素子の周辺駆動回路を、薄膜トランジ
スタを用いて実現することは困難であった。In this way, conventionally τ is a-3i as the active layer 14.
: Since H is used, the electric field mobility is small, so the current driving ability is low. For this reason, for example, when used as a switch element for a pixel electrode in an active liquid crystal display element, the operating speed cannot be made sufficiently high, and it is difficult to realize a peripheral drive circuit for an active liquid crystal display element using thin film transistors. Met.
この発明の目的は電界効果移動度の大きい薄膜トランジ
スタを提供することにある。An object of the invention is to provide a thin film transistor with high field effect mobility.
「問題点を解決するための手段」
この発明によれば薄膜トランジスタの活性層はへテロ接
合超格子構造とされる。つまシ、この第１発明によれば
水素化炭化アモルファスシリコンａ −Ｓ＋ １−ｘＣ
ｘ ：Ｈ（ｘ（０，５）の井戸層と、水素化炭化アモル
ファスシリコンａ −Ｓｉ １−ｘＣｘ： Ｈ（ｘ）０
．５ ）のバリヤ層とが交互に多層積層されて構成され
る。"Means for Solving the Problems" According to the present invention, the active layer of a thin film transistor has a heterojunction superlattice structure. According to the first invention, hydrogenated amorphous silicon a -S+ 1-xC
x :H(x(0,5) well layer and hydrogenated amorphous silicon carbide a-Si 1-xCx: H(x)0
．． 5) and the barrier layer are alternately laminated in multiple layers.
この第２発明によれば、水素化アモルファスシリコンａ
−８ｉ：Ｈの井戸層と、水素化炭化アモルファスシリコ
ンａ −Ｓ １１−１ Ｃｚ ： Ｈのバリヤ層トカ多
層積層されてなる。According to this second invention, hydrogenated amorphous silicon a
-8i:H well layer and hydrogenated amorphous silicon carbide a-S11-1Cz:H barrier layer are laminated in multiple layers.
このようにこの発明による薄膜トランジスタは活性層か
へテロ接合超格子構造となっているため、量子効果によ
る疑似二次元キャリヤの電気伝導による移動度が増大し
、大きな電流駆動能力が得られる。As described above, since the thin film transistor according to the present invention has a heterojunction superlattice structure in the active layer, the mobility due to electric conduction of pseudo two-dimensional carriers due to quantum effects increases, and a large current driving ability is obtained.
「実施例」
第１図はこの発明をトップゲート形スタガ構造に適用し
た薄膜トランジスタの一例を示し、第６図と対応する部
分には同一符号を付けである。Embodiment FIG. 1 shows an example of a thin film transistor in which the present invention is applied to a top gate staggered structure, and parts corresponding to those in FIG. 6 are given the same reference numerals.
この第１発明によれば活性層２１として水素化炭化７
％ ／ｌ／ ７．７ ス’／す：Ｉ ｙ ａ −Ｓｉ
１−ｘＣＸ（ｘ（０，５）を井戸層とし、水素化炭化ア
モルファスシリコンａ −Ｓ ｓ １−ｘＣｘ （ｘ）
０．５ ）をバリヤ層とし、これらを交互に多層積層し
て構成する。前記井戸層の厚さは例えば２５Ｘ、前記バ
リヤ層の厚さは例えば５０Ｘとし、その積層を例えば１
５周期とし、全体の厚さを１１７５又とする。According to this first invention, as the active layer 21, the hydrocarbonized 7
% /l/ 7.7 S'/S: I y a -Si
1-xCX (x (0,5) is a well layer, hydrogenated amorphous silicon carbide a - S s 1-xCx (x)
0.5) as a barrier layer, and these are alternately laminated in multiple layers. The thickness of the well layer is, for example, 25X, the thickness of the barrier layer is, for example, 50X, and the laminated layer is, for example, 1.
There are 5 periods, and the total thickness is 1175.
この活性層２１の形成はシランガスＳｉＨ４とアセチレ
ンガスＣ２Ｈ２とのグロー放電法によシ形成することが
できる。その場合井戸層とバリヤ層との各層の形成ごと
に放電を停止し、反応容器内のガスを・セージ後、原料
ガスを交換して再び放電を行う方法と、放電を停止せず
に各層の形成はガスの切替えのみで行う方法とが考えら
れる。The active layer 21 can be formed by a glow discharge method using silane gas SiH4 and acetylene gas C2H2. In this case, two methods are available: one method is to stop the discharge after each layer (well layer and barrier layer) is formed, and after sage the gas in the reaction vessel, replace the raw material gas and start the discharge again. One possible method is to perform the formation by simply switching the gas.
第１図の例ではゲート絶縁膜２２として炭化アモルファ
スシリコンａ−８ｉ４−ｘＣｘ（ｘ ＞ ０．５ ）を
用いた場合である。このデート絶縁膜２２を用いると、
活性層２１の形成に引き続き、連続的にゲート絶縁膜２
２の形成を行うことができる。In the example shown in FIG. 1, amorphous silicon carbide a-8i4-xCx (x>0.5) is used as the gate insulating film 22. When this date insulating film 22 is used,
Following the formation of the active layer 21, the gate insulating film 2 is continuously formed.
2 formations can be performed.
このように炭化アモルファスシリコンａ−８１１−ｘＣ
ｘのカーボン量Ｘを０．５以上にすると第２図の曲線２
３に示すように導電率が著しく低下し、絶縁層として用
いることができる。In this way, amorphous silicon carbide a-811-xC
When the carbon content X of x is 0.5 or more, curve 2 in Figure 2
As shown in Figure 3, the electrical conductivity is significantly reduced and it can be used as an insulating layer.
第３図はこの発明を＆）ムゲート形スタが構造に適用し
た例を示す。すなわち、基板１１上にデート電極１６が
形成され、そのゲート電極１６上にゲート絶縁膜２２が
形成され、更にその上に活性層２１が形成され、その活
性層２１の両側部上にドレイン電極１）及びソース電極
１３が形成される。FIG. 3 shows an example in which the present invention is applied to a &) Mgate type star structure. That is, a date electrode 16 is formed on the substrate 11, a gate insulating film 22 is formed on the gate electrode 16, an active layer 21 is formed on the gate electrode 16, and a drain electrode 1 is formed on both sides of the active layer 21. ) and source electrode 13 are formed.
第４図はこの発明をコーデラナ構造に適用した薄膜トラ
ンジスタの一例を示す。すなわち基板１１上に活性層２
１が形成され、その活性層２１上にドレイン電極１）と
ソース電極１３とが互に分離されて形成され、これらド
レイン電極１）及びソース電極１３間にわたってゲート
絶縁膜２２が活性層２１上に形成され、ゲート絶縁膜２
２上にゲート電極１６が形成される。FIG. 4 shows an example of a thin film transistor in which the present invention is applied to a Cordelana structure. That is, the active layer 2 is formed on the substrate 11.
A drain electrode 1) and a source electrode 13 are formed on the active layer 21, separated from each other, and a gate insulating film 22 is formed on the active layer 21 between the drain electrode 1) and the source electrode 13. The gate insulating film 2 is formed.
A gate electrode 16 is formed on 2.
上述においては活性層２１の井戸層及びバリヤ層として
共に水素化炭化アモルファスシリコンａ−８ｉ１−ｘＣ
ｘ：Ｈを用いたが、第２発明によれば活性層２１の井戸
層は水素化アモルファスシリコンａ−８ｔ：Ｈで、バリ
ヤ層は水素化炭化アモルファスシリコンａ−８ｔ １−
ｘＣｘ ：Ｈでそれぞれ構成される。この場合も例えば
井戸層の厚さは２５Ｘ１バリヤ層の厚さは５０Ｘとし、
１５周期の多層構造とし、全厚さを１１７５Ｘとされる
。この活性層の形成は先の第１発明の場合と同様に、例
えばＳ ｉＨ４ガスとＣ２Ｈ２ガスのグロー放電法によ
り行うことができる。In the above description, both the well layer and the barrier layer of the active layer 21 are made of hydrogenated amorphous silicon carbide a-8i1-xC.
According to the second invention, the well layer of the active layer 21 is made of hydrogenated amorphous silicon a-8t:H, and the barrier layer is made of hydrogenated amorphous silicon carbide a-8t1-.
xCx :H. In this case, for example, the thickness of the well layer is 25X, the thickness of the barrier layer is 50X,
It has a multilayer structure with 15 periods and a total thickness of 1175X. This active layer can be formed by, for example, the glow discharge method using SiH4 gas and C2H2 gas, as in the case of the first invention.
「発明の効果」
以上述べたようにこの発明によれば、活性層２１がへテ
ロ接合超格子構造となっているため、量子効果による類
似二次元キャリヤの電気伝導による移動度が増大し、大
きな電流駆動能力が得られる。"Effects of the Invention" As described above, according to the present invention, since the active layer 21 has a heterojunction superlattice structure, the mobility due to electrical conduction of similar two-dimensional carriers due to quantum effects increases, and Current drive capability is obtained.
従って例えばアクティブ液晶表示素子の画素電極に対す
るスイッチ素子としてこの発明の薄膜トランジスタを適
用すると、画素電極に対する充放電を急速に行うことが
できる。また大きな電流駆動能力をもつため、アクティ
ブ液晶表示素子の周辺駆動回路の能動素子としても十分
利用することができ、従って液晶表示素子の基板に画素
電極、そのスイッチ素子としての薄膜トランジスタを形
成すると共にその周辺、駆動回路も同一基板に、この発
明の薄膜トランジスタを用いて同時に形成することがで
きる。Therefore, for example, when the thin film transistor of the present invention is applied as a switching element for a pixel electrode of an active liquid crystal display element, charging and discharging of the pixel electrode can be performed rapidly. In addition, since it has a large current driving capability, it can be fully used as an active element in the peripheral drive circuit of an active liquid crystal display element. Peripheral and drive circuits can also be formed simultaneously on the same substrate using the thin film transistor of the present invention.
まだ水素化炭化アモルファスシリコンａ −Ｓ ｔ １
−Ａ：Ｈはカーピン量Ｘを増加すると第３図の曲線２４
に示すように光導電率が低下する。また第５図に示すよ
うにカーボン量Ｘを増加すると光学的エネルギーギャッ
プが大となる。つまりａ −Ｓ ｉ １− ｘＣｘ ：
Ｈはカーピン量Ｘを増加すると光導電効果が小さくな
る。従って、第１発明によればバリヤ層のＸを０５以」
二としているため、基板１１全通して外部から活性層２
１に光が入射されてもこれに影響されることなく、薄膜
トランジスタと１〜で良好に動作するものが得らｆｌる
。Still hydrogenated amorphous silicon a-S t 1
-A:H increases with the curve 24 in Figure 3 as the carpin amount X increases.
The photoconductivity decreases as shown in . Further, as shown in FIG. 5, when the amount of carbon X is increased, the optical energy gap becomes larger. That is, a −S i 1− xCx:
When H increases the carpin amount X, the photoconductive effect becomes smaller. Therefore, according to the first invention, X of the barrier layer is 05 or more.
2, the active layer 2 is exposed from the outside through the entire substrate 11.
Even if light is incident on the thin film transistor 1, it is not affected by the incident light and can operate well with the thin film transistor 1.
第１図はこの発明による薄膜トランジスタの一例を示す
断面図、第２図は炭化アモルファスシリコンのカーピン
量に対する導電率特性例を示す図、第３図及び第４図は
それぞれこの発明の薄膜トランジスタの他の例を示す断
面図、第５図は炭化アモルファスシリコンのカーピン量
に対する光学的エネルギーギャノｆ特性例を示す図、第
６図は従来の薄膜トランジスタを示す断面図である。
特許出願人 星電器製造株式会社
代 理 人 草 野 憫才 ２ 図
Ｃ２１−１）／（ＳｉＨ４＋Ｃ２Ｈ２）才 ３７
；１ｆ７４ 図FIG. 1 is a cross-sectional view showing an example of a thin film transistor according to the present invention, FIG. 2 is a diagram showing an example of conductivity characteristics with respect to carpin content of amorphous silicon carbide, and FIGS. FIG. 5 is a cross-sectional view showing an example of the optical energy Gano f characteristic with respect to the carpin amount of amorphous silicon carbide, and FIG. 6 is a cross-sectional view showing a conventional thin film transistor. Patent applicant: Hoshi Denki Manufacturing Co., Ltd. Agent: Keisai Kusano 2 Figure C21-1)/(SiH4+C2H2) 37;1f74 Figure
Claims (2)
層が配され、その活性層上に上記ドレイン電極及びソー
ス電極間にゲート絶縁膜を介してゲート電極が設けられ
た薄膜トランジスタにおいて、上記活性層は水素化炭化
アモルファスシリコンａ−Ｓｉ＿１＿−＿ｘＣ＿ｘ：Ｈ
（ｘ＜０．５）の井戸層と、水素化炭化アモルファスシ
リコンａ−Ｓｉ＿１＿−＿ｘＣ＿ｘ：Ｈ（ｘ＞０．５）
のバリヤ層とが交互に多層積層されてなることを特徴と
する薄膜トランジスタ。(1) In a thin film transistor in which an active layer is disposed between a drain electrode and a source electrode, and a gate electrode is provided on the active layer with a gate insulating film interposed between the drain electrode and the source electrode, the active layer is Hydrogenated amorphous silicon carbide a-Si_1_-_xC_x:H
(x<0.5) well layer and hydrogenated amorphous silicon carbide a-Si_1_-_xC_x:H(x>0.5)
A thin film transistor characterized in that a multilayer barrier layer is laminated alternately.
層が配され、その活性層上に上記ドレイン電極及びソー
ス電極間にゲート絶縁膜を介してゲート電極が設けられ
た薄膜トランジスタにおいて、上記活性層は水素化アモ
ルファスシリコンａ−Ｓｉ：Ｈの井戸層と、水素化炭化
アモルファスシリコンａ−Ｓｉ＿１＿−＿ｘＣ＿ｘ：Ｈ
のバリヤ層とが交互に多層積層されてなることを特徴と
する薄膜トランジスタ。(2) In a thin film transistor in which an active layer is disposed between a drain electrode and a source electrode, and a gate electrode is provided on the active layer with a gate insulating film interposed between the drain electrode and the source electrode, the active layer is Well layer of hydrogenated amorphous silicon a-Si:H and hydrogenated amorphous silicon carbide a-Si_1_-_xC_x:H
A thin film transistor characterized in that a multilayer barrier layer is laminated alternately.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1378687A JPS63181473A (en) | 1987-01-23 | 1987-01-23 | Thin-film transistor |
| US07/145,949 US4849797A (en) | 1987-01-23 | 1988-01-20 | Thin film transistor |
| DE88100845T DE3881066T2 (en) | 1987-01-23 | 1988-01-21 | Thin film transistor. |
| AT88100845T ATE89686T1 (en) | 1987-01-23 | 1988-01-21 | THIN FILM TRANSISTOR. |
| EP88100845A EP0276002B1 (en) | 1987-01-23 | 1988-01-21 | Thin film transistor |
| EP19910121805 EP0484987A3 (en) | 1987-01-23 | 1988-01-21 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1378687A JPS63181473A (en) | 1987-01-23 | 1987-01-23 | Thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63181473A true JPS63181473A (en) | 1988-07-26 |
Family
ID=11842932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1378687A Pending JPS63181473A (en) | 1987-01-23 | 1987-01-23 | Thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63181473A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6731531B1 (en) | 1997-07-29 | 2004-05-04 | Micron Technology, Inc. | Carburized silicon gate insulators for integrated circuits |
| US6835638B1 (en) | 1997-07-29 | 2004-12-28 | Micron Technology, Inc. | Silicon carbide gate transistor and fabrication process |
| WO2006127225A2 (en) * | 2005-05-25 | 2006-11-30 | Mears Technologies, Inc. | Semiconductor device comprising a superlattice dielectric interface layer |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60124973A (en) * | 1983-12-12 | 1985-07-04 | Semiconductor Energy Lab Co Ltd | Insulated gate type semiconductor device |
| JPS61125082A (en) * | 1984-11-21 | 1986-06-12 | Hitachi Maxell Ltd | Thin film transistor |
| JPS6242566A (en) * | 1985-08-20 | 1987-02-24 | Fujitsu Ltd | Thin film transistor |
| JPS6288367A (en) * | 1985-10-11 | 1987-04-22 | ゼネラル エレクトリツク カンパニー | Transistor |
| JPS62299083A (en) * | 1986-06-18 | 1987-12-26 | Fujitsu Ltd | Thin-film transistor |
-
1987
- 1987-01-23 JP JP1378687A patent/JPS63181473A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60124973A (en) * | 1983-12-12 | 1985-07-04 | Semiconductor Energy Lab Co Ltd | Insulated gate type semiconductor device |
| JPS61125082A (en) * | 1984-11-21 | 1986-06-12 | Hitachi Maxell Ltd | Thin film transistor |
| JPS6242566A (en) * | 1985-08-20 | 1987-02-24 | Fujitsu Ltd | Thin film transistor |
| JPS6288367A (en) * | 1985-10-11 | 1987-04-22 | ゼネラル エレクトリツク カンパニー | Transistor |
| JPS62299083A (en) * | 1986-06-18 | 1987-12-26 | Fujitsu Ltd | Thin-film transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6731531B1 (en) | 1997-07-29 | 2004-05-04 | Micron Technology, Inc. | Carburized silicon gate insulators for integrated circuits |
| US6835638B1 (en) | 1997-07-29 | 2004-12-28 | Micron Technology, Inc. | Silicon carbide gate transistor and fabrication process |
| WO2006127225A2 (en) * | 2005-05-25 | 2006-11-30 | Mears Technologies, Inc. | Semiconductor device comprising a superlattice dielectric interface layer |
| WO2006127225A3 (en) * | 2005-05-25 | 2007-02-22 | Rj Mears Llc | Semiconductor device comprising a superlattice dielectric interface layer |
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