JPS63181016U - - Google Patents
Info
- Publication number
- JPS63181016U JPS63181016U JP7264287U JP7264287U JPS63181016U JP S63181016 U JPS63181016 U JP S63181016U JP 7264287 U JP7264287 U JP 7264287U JP 7264287 U JP7264287 U JP 7264287U JP S63181016 U JPS63181016 U JP S63181016U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- bias power
- current mirror
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第1図は本考案の一実施例の回路図、第2図は
第1図の変形例の回路図、第3図は本考案の他の
実施例の回路図、第4図は従来例の回路図である
。
1…可変電圧源、2a…NPNトランジスタ、
3b,6b,7b…PNPトランジスタ、4,9
…抵抗。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a modification of Fig. 1, Fig. 3 is a circuit diagram of another embodiment of the invention, and Fig. 4 is a circuit diagram of a conventional example. It is a circuit diagram. 1... Variable voltage source, 2a... NPN transistor,
3b, 6b, 7b...PNP transistor, 4, 9
…resistance.
Claims (1)
続し、該第1のトランジスタのエミツタに定電流
源及び第2のトランジスタのベースを夫々接続し
、該第1のトランジスタのコレクタにバイアス電
源を接続し、該第2のトランジスタのエミツタに
抵抗を介してバイアス電源を接続したトランジス
タ回路において、 1入力複数出力のカレントミラー回路の入力端
を該第2のトランジスタのコレクタに接続し、該
カレントミラー回路の第1の出力端を該第1のト
ランジスタのエミツタに接続し、該カレントミラ
ー回路の他の複数の出力端を夫々負荷を介して前
記バイアス電源に接続してなるトランジスタ回路
。[Claims for Utility Model Registration] An input voltage source is connected to the base of the first transistor, a constant current source and the base of the second transistor are connected to the emitter of the first transistor, and In a transistor circuit in which a bias power source is connected to the collector of the second transistor, and a bias power source is connected to the emitter of the second transistor via a resistor, the input terminal of a current mirror circuit with one input and multiple outputs is connected to the collector of the second transistor. a first output terminal of the current mirror circuit is connected to the emitter of the first transistor, and a plurality of other output terminals of the current mirror circuit are connected to the bias power supply through respective loads. transistor circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7264287U JPS63181016U (en) | 1987-05-15 | 1987-05-15 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7264287U JPS63181016U (en) | 1987-05-15 | 1987-05-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63181016U true JPS63181016U (en) | 1988-11-22 |
Family
ID=30916273
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7264287U Pending JPS63181016U (en) | 1987-05-15 | 1987-05-15 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63181016U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5592006A (en) * | 1978-12-27 | 1980-07-12 | Pioneer Electronic Corp | Amplifier |
-
1987
- 1987-05-15 JP JP7264287U patent/JPS63181016U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5592006A (en) * | 1978-12-27 | 1980-07-12 | Pioneer Electronic Corp | Amplifier |