JPS63180992U - - Google Patents
Info
- Publication number
- JPS63180992U JPS63180992U JP7136687U JP7136687U JPS63180992U JP S63180992 U JPS63180992 U JP S63180992U JP 7136687 U JP7136687 U JP 7136687U JP 7136687 U JP7136687 U JP 7136687U JP S63180992 U JPS63180992 U JP S63180992U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- case material
- fixed
- circuit boards
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims description 5
- 238000010396 two-hybrid screening Methods 0.000 claims 2
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
第1図は本考案の実施例を示す断面図、第2図
は本実施例のケース材を示す平面図、第3図は他
の実施例を示す断面図、第4図乃至第6図は従来
を示す断面図である。
1,2は混成集積回路基板、3はケース材、4
は回路素子、5は外部リード、6はケース材の側
体部、7は基板ストツパー。
Fig. 1 is a sectional view showing an embodiment of the present invention, Fig. 2 is a plan view showing the case material of this embodiment, Fig. 3 is a sectional view showing another embodiment, and Figs. 4 to 6 are It is a sectional view showing the conventional art. 1 and 2 are hybrid integrated circuit boards, 3 is a case material, and 4
5 is a circuit element, 5 is an external lead, 6 is a side body part of the case material, and 7 is a board stopper.
Claims (1)
された二枚の混成集積回路基板と、前記二枚の混
成集積回路基板を離間して固着するケース材とか
ら成る混成集積回路において、前記ケース材の終
端辺のエツヂ部を前記混成集積回路基板の基板表
面より内側に配置したことを特徴とする混成集積
回路。 In the hybrid integrated circuit comprising two hybrid integrated circuit boards having a circuit element and an external lead fixed to the peripheral edge of one side, and a case material to which the two hybrid integrated circuit boards are fixed in a spaced manner, A hybrid integrated circuit characterized in that an edge portion on a terminal side of the case material is disposed inside a substrate surface of the hybrid integrated circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7136687U JPS63180992U (en) | 1987-05-13 | 1987-05-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7136687U JPS63180992U (en) | 1987-05-13 | 1987-05-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63180992U true JPS63180992U (en) | 1988-11-22 |
Family
ID=30913854
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7136687U Pending JPS63180992U (en) | 1987-05-13 | 1987-05-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63180992U (en) |
-
1987
- 1987-05-13 JP JP7136687U patent/JPS63180992U/ja active Pending
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