JPS63180279A - Memory circuit - Google Patents

Abstract

PURPOSE:To reduce the capacity of a memory by thinning out an input data string at the rate of one sample at every (n) samples at the time of writing and interpolating the thinned-out sample at the time of reading. CONSTITUTION:For writing a luminance signal Yd in the memory 1, an address signal and a write signal are supplied from a write control circuit 2 to the memory 1. If four in the data string of the Yd is set to one group, for example, fourth data in respective groups are not addressed, and the write signal comes to an inhibit level, whereby the thinned-out signal Yd is written. At the time of reading, a read control circuit 3 reads the thinned-out signal data string. A interpolating circuit 4 generates interpolating data from precedent and subsequent data of thinned-out data, and the thinned-out signal Yd is fetched through a delay circuit 5 and a switch 6. Thus, the capacity of the memory can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to memory circuits.

[Summary of the invention]

In a memory circuit, when writing, this invention thins out a human data string at a rate of 1 sample every n samples and writes it into the memory, and when reading, by interpolating the thinned out samples, the capacity of the memory is reduced ( n
-1)/n times.

[Conventional technology]

For example, in a home VTR, one way to achieve still playback on a clear screen without noise or blurring is to use field memory.

[Problem that the invention seeks to solve]

By the way, as shown in FIG. 6, when the band of the signal Y is IN, the sampling frequency fs is fs≧2fw, but if the number of bits per sample is n, then
The bit rate rb is f)≧2fwn(bPs).

Therefore, when storing a 1 second signal in memory,
The memory capacity M becomes minimum at M-2fHnT when fS=2fN, but if the sampling frequency fs is brought closer to the frequency 21n in order to reduce the capacity M, the following problem occurs.

It is necessary to make the cutoff characteristic of the low-pass filter before the i^/D conversion steep, and the phase characteristic deteriorates.

The same goes for the low-pass filter after it D/^ conversion.

ii Frequency characteristics deteriorate due to ^10 conversion and D/^ conversion converter Percha effect, and high frequency compensation is required.

This invention attempts to solve these problems.

[Means for solving problems]

Therefore, in the present invention, when writing, the human input signal is sampled at a sampling frequency sufficiently higher than its Nyquist frequency, and is thinned out at a rate of 1 sample for each predetermined number of samples and written to the memory, and when reading, The thinned out data is interpolated from the data before and after it.

[Effect]

Apparently, the memory capacity is about the same as when sampling at a frequency close to the Nyquist frequency.

〔Example〕

In FIG. 1, Yd indicates a digital luminance signal, which means that, as shown in FIG. 2A, for example, the original analog luminance signal has a sampling frequency fs (=4fn) that is four times its Nyquist frequency fN. A signal archive in which one sample is sampled and converted into an 8-bit parallel digital signal Yd is shown in A in the same figure.
(i=0.1.2°3...) indicates data for each sample of the signal Yd.

At the time of writing, this signal Yd is supplied to the field memory (1). This memo January 1) has a predetermined capacity and, in this example, is a so-called dual-port memory in which writing and reading of data can be freely performed almost independently.

In the write control circuit (2), FIG.

As shown in C, a write address signal -80R and a write signal WE are formed in synchronization with each data Yi of the signal Yd, and these signals -ADR and WE are supplied to the memory +1). In this case, the address indicated by the signal -ADR is originally incremented by one address for each data Yi of the signal Yd, but for example, the address indicated by the signal Yd is incremented by one address.
J - YJ÷3 When (j-0, 4, 8, . . . ) is one set, the address of the fourth data Yj+3 in each set is the same as the address of the third data YJ+2. In addition, the write signal WE also goes to the 6L" level (write permission level) for each data Yl of the signal Yd, but during the period of data YJ+3 when the address signal -ADR is not incremented, the write signal WE goes to the "H" level (write prohibition level). ) will be left as is.

Therefore, when the signal Yd is written to the memory (1), this signal Yd is thinned out at a ratio of 1 data Y for every 4 data Yj - YJ ÷ 3, +3, and the signal resulting from the thinning is The addresses Yd ("Yj"'Yj+2) will be written consecutively in the memo January 1). In the case of FIG. 2, each data Y3 in the signal Yd
, Yv, Yll, . . . are thinned out, and the remaining data is sequentially written one address at a time starting from address O in memory (1).

On the other hand, during reading, the read control circuit (3) receives the read address signal R as shown at H in the figure.
ADR and read signal RD are formed, and these signals R
ADR, RD will be supplied in Memo January 1).

In this case, the address indicated by the signal RADR is the signal -AD
Similar to R, it is incremented at the rate of thinning out one data for every four data of signal Yd, and the signal RD is also at the "L" level read permission level during the period corresponding to the data that has not been thinned out. ), and during the period corresponding to the thinned out data, the level is set to "H"level<Vt overflow inhibition level).

Therefore, as shown in FIG. F, from the memory 11, when four data are set as one set, a signal Yd is read out, which is the same data YJ+2 for the third and fourth data, for example.

Then, this read signal Yd is sent to the interpolation circuit (4).
As shown in FIG.
c is formed and supplied to the switch circuit (6), and at the same time, the signal Yd is supplied to the delay circuit (5), and as shown in F and G of the figure, the thinned data Y in the signal Yd is
, H43 and the position of the interpolated data Yc, the signal Yd is delayed and supplied to the switch circuit (6).

Then, the switch circuit (6) is switched between the data Yc period and the remaining period, and from the switch circuit (6), as shown in H in the same figure, the thinned out data is output as a digital luminance interpolated with the data Yc. A signal Yd is taken out.

Thus, according to the present invention, the luminance signal Yd is stored in the memory (
L) and read it when necessary, but in this case, in particular, according to the present invention, there is no problem since the human input signal is sampled at a sampling frequency sufficiently higher than its Nyquist frequency when writing. Point (i
) to (iii) can all be solved. At this time, the data to memory (1) was thinned out and written at a rate of 1 sample for every n number of samples, and when reading, the thinned out data was interpolated from the data before and after it. ) can be made (n-1)/n times smaller than the original capacity, and in the case of the above numerical example, ' s = 3 / 4fH and the capacity of Memo January 1) can be reduced to It can be done in 3/4.

FIG. 3 shows an example of the interpolation circuit (4). That is, for example, six delay circuits (41) to (46) are connected in series, and the delay time of each of these delay circuits (41) to (46) is determined by the signal Yd read from the memo January 1). This signal Yd is supplied to the delay circuit (41).

Therefore, from the delay circuits (41) to (46), six consecutive samples of data Yi~'/i w of the signal Yd are output.
Y H+s will be obtained at the same time, but the data Y
1+z and Yi+→ are supplied to an adder circuit (71), and average data (Yi+2+Yi+4)/2 is taken out.
Similarly, each average data is taken out from the addition circuits (72) and (73), and these average data are supplied to the addition circuit (74), and the average data of data Yi to YH46 is taken out as interpolated data Yc. It will be done.

Then, this data Yc is supplied to the switch circuit (6), and data Y1+3 is supplied from the delay circuit (43).
is the signal Yd from the delay circuit (5) and the switch circuit (
6). Therefore, the signal Yd interpolated by the data Yc is taken out from the switch circuit (6).

In the example shown in FIG. 4, color difference signals are also processed at the same time. That is, at the time of writing, the digital luminance signal Yd is supplied to the switch circuit (8), and
A digital color difference signal Cd is supplied. In this case, the signal Y
d is a signal sampled and digitized at a frequency four times the color subcarrier frequency fc as shown in FIG. This is a signal that is alternately sampled at 2fc and digitized.

Then, from the switch circuit (8), the signal Yd is thinned out at a ratio of one for four data, and the signal Cd
Signal 1. A signal Sd having Q alternately is taken out, this signal Sd is supplied to the memo January 1), and all of the signal Sd is sequentially written to each address of the memo January 1) without being thinned out.

When reading, the signal S from the memory (1) is
d are read out in order as shown in C of the same figure, and this read signal Sd is supplied to the interpolation circuit (4) and the delay circuit (5), and the switch circuit (6) is outputted as shown in the same figure. , a digital luminance signal Yd interpolated by interpolation data Yc from the delay circuit (4) is extracted.

Further, the signal Yd read from the memo 1) is supplied to the latch (9), and as shown in FIG. The original digital color difference signal Cd latched for each Q
is taken out.

Therefore, in this case, 1 of the digital luminance signal Yd
With the memory (1) having a capacity equivalent to one field, the digital color difference signal Cd can also be processed at the same time.

〔Effect of the invention〕

According to this invention, it is possible to write the luminance signal Yd in the memo 1) and read it out when necessary. In this case, in particular, according to this invention, when writing, the input signal is Since sampling is performed at a sufficiently high sampling frequency, problems (i) to (ii)
i) can all be solved.

At this time, the data for memory (11) was thinned out and written at a rate of 1 sample for every n samples, and when reading, the thinned out data was interpolated from the data before and after it, so I wrote it in a memo (January 1). The capacity of can be made (n-1)/n times smaller than the original capacity, and in the case of the above numerical example, apparently fs = 3 / 4
fH, and the capacity of memory (1) can be reduced to 3/4.

[Brief explanation of the drawing]

1 and 4 are system diagrams of an example of the present invention, and FIGS. 2, 3, 5, and 6 are diagrams for explaining the same. (1) is a memory, and (4) is an interpolation circuit.

Claims (1)

[Scope of Claims] In a memory circuit in which a data string is accessed, at the time of writing, the data of the data string is n samples (n>2
) is thinned out at a rate of 1 sample per sample and written to memory, and when reading, the data string that has been thinned out is read from the memory, and the thinned out data is interpolated from the data before and after it. memory circuit