GB2221117A

GB2221117A - Recursive noise reduction filter for still video signals

Info

Publication number: GB2221117A
Application number: GB8913736A
Authority: GB
Inventors: Kenji Shimoda
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1988-07-15
Filing date: 1989-06-15
Publication date: 1990-01-24
Also published as: DE3921008C2; JPH0226478A; DE3921008A1; GB8913736D0; KR900002625A

Description

4 2221117 "RECURSIVE NOISE REDUCTION CIRCUIT11 This invention relates to a

noise reduction circuit, and more particularly, to a recursive noise reduction circuit in which one field of still video signal is stored and recursively added to reduce a noise signal.

Conventionally, a noise reduction circuit for reducing a noise component contained in a video signal is used in a magnetic recording/reproducing apparatus for recording and reproducing a video signal. The noise reduction circuit is used to reduce the noise signal contained in the video signal, e.g. still image signal input to the magnetic recording/reproducing apparatus, for example, and it uses a memory for storing at least one frame of still image to recursively process the still image. Such a recursive noise reduction circuit is disclosed in, for example, documents "TELEVISION JOURNAL", 1979, Vol. 33, No. 4 "NOISE REDUCER"; "TELEVISION TECHNOLOGY.' 1987, JAN. "NEC NOISE WIPER VC-D7HF"; and "TELEVISION JOURNAL", ITEJ Vol. 11, No. 13 "IMPROVEMENT OF IMAGE BY APPLICATION OF DIGITAL MEMORY".

For examplei the noise reduction circuit for recursively adding a still image for each field is constructed as follows. That is, the still image of current field supplied via the input terminal is multiplied by (1-K) (K is a fixed value and O<K<1) by

1 a multiplier circuit and then supplied to an adding circuit. The output of the adding circuit is written into a field memory. The field memory is accessed by means of a timing generation circuit for generating various timing signals in synchronism with the still image signal supplied to the input terminal. The added output of the adding circuit which has been obtained for the immediately preceding field is read out from the field memory. The readout added output is multiplied by K by means of a coefficient multiplier and then supplied to the adding circuit again.

The above operation is repeatedly effected each time a still image signal of new field is supplied to the input terminal so that the image signal having the noise component reduced can be derived from the output terminal.

Further, another type of recursive noise reduction circuit having two adding circuits has been used. In this type of noise reduction circuit, a still image of current field supplied from the input terminal is supplied to first and second adding circuits and a timing generation circuit, and the output of the first adding circuit is supplied to the output terminal and at the same time written into a field memory. The field memory is accessed by means of the timing generation circuit, and the added output of the first adding cir cuit obtained in the immediately preceding field is read

3 - out from the field memory and supplied to the second adding circuit. The output of the second adding circuit is multiplied by K (O<K<1) by means of a multiplier circuit and then supplied to the first adding circuit. The output of the first adding circuit is obtained as an added output of a signal equal to (1-K) times the still image signal of current field and a signal equal to K times the added output of the immediately preceding field.

In the conventional recursive noise reduction circuit described above, a still image signal appearing at the output terminal at the end of the recursive adding operation is derived. In this case, SIn and Son respectively denote an input still image signal and an output still image signal of the n-th field in a case where n=0 for the current field.

so. = (1-K) + (1-K) (1-K) At this time, image signal SI is equation is obtained:

SI-n = SI-(n+l) = SI... (2) As a result, equation (1) can be rewritten as follows:

sio + U-K). K SI-1 K2 # SI-2 +...

(1-K). K(n-1) SI-(n-1) (SIo + K - SI-1 + K2. SI-2 + K(n-1) ' SI-(n-1))... (1) the field correlation of input still "V' and therefore the followina 1 Soo = U-K) n (lim E K(k-1)). S, n± k=l 1 (1-K) T__K. SI = SI .. (3) The noise component can be expressed as follows:

N002 = (1-K)2. NIO 2 + (1-K)2. K2. NI_12 + + (1-K)2. K(n-1).-N12_ (n-1) = (1-K)2. (NIO 2 + K2. N-12 +...

+ K(n-1). N12_ (n-1)...(4) where NI-n and NO-n denote an input noise signal and an output noise signal obtained before n fields in a case where n=0 for the current field.

In this case, input noise signal NI normally has no field correlation. However, if the amplitude level is kept constant with time, then the following equation can be obtained since the power thereof is constant:

NI-n2 = NI-(n+l)2 = N12... (5) By combining equations (4) and (5), the following equation can be obtained.

n N002 = (1-K)2. lim E K2(k-1) - N12 n± k=l (1-K)2. 1 1 K2. N12... (6) From equation (6)r the following equation is derived.

NOO U-K)2. N12 -K7. NI 1-K2 = /P+K .. (7) - As described above, it is clearly understood by comparing equations (3) and (7) that output still image signal SO is set at the same level as input still image signal SI while the-level of output noise signal NO is suppressed to (1-K)/(1+K) times the level of input noise signal NI. In this case, the noise reduction effect can be improved more as the value of K is set closer to "1".

However, as is clearly seen from equation (4), with the noise reduction circuit of the above construction, the final addition coefficient for input noise signal NI in each field becomes different, and the added amount becomes larger in a field closer to the current field. Therefore, when the number of added fields is small (in a case where the noise signal is reduced by using 5 or 10 fields, for example), a significant noise reduction effect cannot be attained.

In order to solve the above problem, it is considered that a noise reduction circuit using a field memory for the still image signal of each field is used instead of the recursive noise reduction circuit.

That is, a still image signal input from the input terminal is supplied to the timing generation circuit and a plurality of field memories. The field memories corresponding in number (n) to fields to be added together are used to store the still image signals of n fields. When the field memories are accessed by the timing generation circuit, the still image signals stored in the field memories are multiplied by l/n corresponding to the number of the field memories by means of a coefficient multiplier, and then supplied to an adding circuit. An output still image signal from the adding circuit is supplied from the output terminal. output still image signal SO and output noise signal NO represented by equations (8) and (9) are supplied to the output terminal.

SO0 =.1 - SIo +.1. SI-1 + +.1 SI- (n-1) n n n = SI 1. n. SI i .. (8) NOO = 1 7. NI02 + 1 7. NI-12 + + - 1 7 N12_ (n-1) /n n n L- NI,fn .. (9) As described above, when the noise reduction circuit different from the recursive noise reduction circuit is used, the final adding coefficient for input noise signal NI in each field can be set equal as is clearly understood from equation (9). Therefore, input noise signal NI of each field contributes to noise reduction by the same amount. As a result, even when the number n of added fields is small, a sufficiently large noise reduction effect can be attained.

However, in this case, n field memories for the n adding fields are necessary and therefore the size of the noise reduction circuit becomes large.

Thus, a recursive noise reduction circuit which is small in size and can attain a significant noise reduction effect even in a case of the small number of adding fields has been long required.

An object of this invention is to provide a recursive noise reduction circuit which can attain a significant noise reduction effect even in a case of the small number of adding fields and in which it is not necessary to provide field memories corresponding in number to added fields in order to attain a sufficiently large noise reduction effect.

According to an aspect of the present invention, there is provided a recursive noise reduction circuit for storing a still image video signal of at least one field and recursively adding the same to reduce the noise component of the still image video signal, comprising an A/D converter for converting the input still image video signal into a digital signal, currentcoefficient means for multiplying the digital signal converted by the A/D converter by l/t (t denotes the reception order of the still image video signal), recursive adding means for sequentially and recursively 8 adding a still image video signal of an immediately preceding field to the input still image video signal to remove the noise component contained in the input still image video signal from the digital signal multiplied by 1/k by the current-coefficient means, field memory means for storing the output of at least one field of the recursive adding means, precedingcoefficient means for multiplying preceding data of the still image video signal of the immediately preceding field read out from the field memory means by (L-1)/L and then supplies the multiplication result to the recursive adding means, timing generation means for accessing the field memory means at a preset timing in synchronism with the still image video signal and supplying a is preset control signal for selecting the preceding data of the preceding-coefficient means to the precedingcoefficient means, and a D/A converter for converting the digital signal having the noise component removed and supplied from the recursive adding means into an analog signal.

According to another aspect of the present invention, there is provided a recursive noise reduction circuit for storing a still image video si.gnal of at least one field and recursively adding the same to reduce the noise component of the still image video signal, comprising an A/D converter for converting the input still image video signal into a digital signal, current-coefficient means for multiplying current data of the input still image video signal output from the A/D converter by (1-KL) (t denotes the reception order of the still image video signal), recursive adding means for sequentially recursive-adding a still image video signal of an immediately preceding field to the input still image video signal to remove the noise component contained in the input still image video signal from output of the current-coefficient means, field memory means for storing the output of-at least one field of the recursive adding means, preceding-coefficient means for multiplying preceding data of the still image video signal of the immediately preceding field read out from the field memory means by Kt and then supplies the multiplication result to the recursive adding means, timing generation means for accessing the field memory means at a preset timing in synchronism with the still image video signal and supplying a preset control signal for selecting the preceding data and the current data of the preceding-coefficient means and the currentcoefficient means to the preceding-coefficient means and the current-coefficient means, and a D/A converter for converting the digital signal having the noise component removed and supplied from the recursive adding means into an analog signal.

According to still another aspect of the present invention, there is provided a noise reduction circuit for storing a still image video signal of at least one frame and recursively adding the same to reduce the noise component of the still image video signal, comprising an A/D converter for converting the input still image video signal into a digital signal, current-coefficient means for multiplying the digital signal converted by the A/D converter by l/t (t denotes the reception order of the still image video signal), recursive adding means for sequentially and recursively adding a still image video signal of an immediately preceding frame to the input still image video signal to remove the noise component contained in the input still image video signal from the digital signal multiplied l/L by means of the current-coefficient means, frame memory means for storing the output of at least one frame of the recursive adding means, preceding-coefficient means for multiplying preceding data of the still image video signal of the immediately preceding frame read out from the frame memory means by (t-l)/L and then supplies the multiplication result to the recursive adding means, timing generation means for accessing the frame memory means at a preset timing in synchronism with the still image video signal and supplying a preset control signal for selecting the preceding data of the preceding-coefficient means to the preceding-coefficient means, and a. D/A converter for converting the digital signal having the noise component removed and supplied from the recursive adding means into an analog signal.

According to further aspect of the present invention, there is provided a noise reduction circuit for storing a still image video signal of at least one frame and recursively adding the same to reduce the noise component of the still image video signal, comprising an A/D converter for converting the input still image video signal into a digital signal, currentcoefficient means for multiplying current data of the input still image video signal output from the A/D converter by (1-KL) (ú denotes the reception order of the still image video signal), recursive adding means for is sequentially and recursively adding a still image video signal of an immediately preceding frame to the input still image video signal to remove the noise component contained in the input still image video signal from output of the current-coefficient, frame memory means for storing the output of at least one frame of the recursive adding means, preceding-coefficient means for multiplying preceding data of the still image video signal of the immediately preceding frame read out from the frame memory means by Kt and then supplies the multiplication result to the recursive adding means, timing generation means for accessing the frame memory means at a preset timing in synchronism with the still image video signal and supplying a preset control signal for selecting the preceding data and the current data of the preceding-coefficient means and the current-coefficient means to the preceding- coefficient means and the current-coefficient means, and a D/A converter for converting the digital signa.1 having the noise component removed and supplied from the recursive adding means into an analog signal.

The aforementioned aspects and other features of the present invention are explained in the following description, taken in conjunction with the accompanying drawings wherein:

Fig. 1 is a block diagram showing the construction of a first embodiment of a noise reduction circuit according to the present invention; Fig. 2 is a block diagram showing an example of a timing generation circuit of Fig. 1; Fig. 3 is a block diagram showing a second embodi- ment of the present invention; Fig. 4 is a block diagram showing a third embodiment of the present invention; and Fig. 5 is a block diagram showing a fourth embodi ment of the present invention.

There will now be described an embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 is a block diagram showing the construc tion of one embodiment of the present invention and shows a noise reduction circuit applied to a magnetic recording/reproducing apparatus, for example. In Fig. 1, 12 denotes an input terminal to which a still image video signal previously selected from a video signal is sequentially supplied. The still image video signal supplied to the input terminal is con verted into a digital signal by means of A/D converter (analog-digital converter) 14 and then supplied to and multiplied by (1-K1), (1-K2), (1-Kn) by means of coefficient circuits 161, 162r 16n. The outputs of coefficient circuits 161, 162P ---,.16n are sequentially selected at a field frequency by means of switch 18 and then supplied to adding circuit 20. The output of adding circuit 20 is supplied to D/A converter (digital- analog converter) 22 and at the same time written into field memory 24. The output of field memory 24 is supplied to and multiplied by K1, K2, Kn by means of coefficient circuits 261, 262, ---, 26n for the number (n) of added fields. The outputs of coefficient circuits 261p 262# ---, 26n are selected at the field frequency by means of switch 28 and then supplied to adding circuit 20 to be added to the selected output of switch 18.

Further, the still image video signal supplied to input terminal 12 is supplied to timing generation circuit 30 via A/D converter 14. Timing generation circuit 30 generate a control signal for controlling the selecting operation of switches 18 and 28 and various timing signals such as a signal for accessing field memory 24 in synchronism with the still image video signal. That is, when a still image video signal of L-th field is supplied by the control of timing generation circuit 30, for example, L-th coefficient circuit 16Z is selected by means of switch 18. After this, an added output of (L-l)th field is read out from field memory 24 and L-th coefficient circuit 26L is selected.

On the other hand, the still image video signal output from adding circuit 20 and having the noise component reduced is converted into an analog signal in D/A converter 22, and then supplied to the main body of a magnetic recording/reproducing apparatus (not shown) from output terminal 32.

Fig. 2 is a block diagram showing an example of timing generating circuit 30.

The still image video signal input from input terminal 12 via A/D converter 14 is supplied to coefficient circuits 161, 162, ---, 16n and to vertical/horizontal sync separation circuit 34 of timing generating circuit 30. Each time a vertical sync signal and a horizontal sync signal are supplied to memory control circuit 36, switching selection signals for each field are supplied - 15 to switches 18 and 28. That is, the switching positions of switches 18 and 28 are sequentially changed at the field frequency so that the outputs of coefficient cir cuits 161, 162r ---, 16n and coefficient circuits 261, 262' ---, 26n can be selected and sequentially supplied to adding circuit 20.

The horizontal sync signal is supplied to and phase-locked by means of phase locked loop circuit 38, and then a clock signal whose phase is locked with the horizontal sync signal is supplied to memory control circuit 36.

Memory control circuit 36 controls field memory 24 by supplying a memory readout signal and a memory write in signal to field memory 24 at a preset timing. The memory readout signal is, for example, a chip select signal for selecting one of a plurality of memories, a read strobe signal-for controlling data transfer from the memory cell array to the output register, or a read address signal for specifying the reception of a readout address of the memory. The memory write-in signal is, for example, the chip select signal, a write strobe signal for controlling data transfer from the input register to the write latch, a write enable signal for controlling the write-in of data from the write latch into the memory cell array, or a write address signal for specifying the reception of the write address of the memory.

Now, the operation of the noise reduction circui with the above construction is explained.

First, assume that coefficients K1f K2, ---. and Kn for coefficient circuits 161, 162, ---, and 16n and coefficient circuits 261, 262, ---, and 26n are set as follows:

1 - K1 = 1/2 1 - K2 = 1/3 1 - Kn = l/n Therefore, coefficients (1-K1), (1-K2), ---, and (1-K-n)-Of coefficient circuits 161, 162, ---, and 16n are respectively set at 1/2, 1/3, ---, and l/n.

Further, coefficients Kly K21 ---. and Kn Of coefficient circuits 261, 262, ---, and 26n are respectively set at 1/2, 2/3, ---, and (n-1)/n--.

In this way, in this embodiment, the still image video signal of t-th field is multiplied by l/L where z is the reception order of a field. The readout output of field memory 24 is multiplied by As a result, output still image signal SO supplied to output terminal 32 and output noise signal NO contained in signal SO which are obtained when the operation of recursively adding input still image signals SI of n fields is completed can be expressed as follows:

SOO =.1 - SI + n-1. { 1. S,_, n 0 n n-1 + n-2 ( 1 1 n-1 -n---7 SI-2 + + -n--7 SI- (n-1 1 SI n n n 0 + 'I SI-1 + + 'L SI- (n-1) = SI N2 NI 2 + (n-1)2 Oo ny 0 n2 .. (10) 0 1 1 NI-12 (n-1)2 - + ( n-2)2. { 1 NI-22 + n-T (n-2)2 + (n 1 2)2 - N12_ (n-l)}] =.1 N12 n NOO = 1 NI v n .. (11) As is clearly understood from equation (10), input image signal SI of each field is eventually subjected to an addition with an addition coefficient of l/n. As a result, the level of output image signal SO at the time of completion of recursive addition for n fields becomes the same as that of input image signal SI. Therefore, input image signal SI can be supplied from D/A converter

22 to output terminal 32 without any restriction.

Also, as is clearly understood from equation (11), input image noise signal NI of each field is eventually subjected to an addition with the same addition coef ficient. As a result# output noise signal NO obtained by attenuating input noise signal NI by 1/,/-n can be supplied to output terminal 32 at the time of completion of recursive addition for n fields.

As described above, according to the above embodiment, the addition coefficients of the input still image signal and the readout output of field memory 24 are changed for each field. More specifically, an input still image signal of L-th field is multiplied by l/t, and the readout output of field memory 24 is multiplied by U-1)A.

With the above construction, the same addition coefficient is set for input noise signal NI of each field, and input noise signal NI of each field can contribute to noise reduction at the same rate at the final stage. Therefore, a sufficiently large noise reduction effect can be attained even when the number of addition fields is small.

Further, the above recursive circuit uses only one field memory 24, and therefore the circuit size can be kept small unlike the circuit using field memories for n addition fields.

Fig. 3 is a block diagram showing the construction of a second embodiment of the present invention. In Fig. 3, portions which have the same construction and operated in the same manner as those of Fig. 1 are denoted by the same reference numerals and the explana tion therefor is omitted.

In Fig. 3, an input still image signal input from input terminal 12 via A/D converter 14 is supplied to adding circuits 40 and 42 and to timing generation circuit 30. The output of adding circuit 40 is supplied from D/A converter 22 to output terminal 32 and at the same time written into field memory 24. The output of field memory 24 is supplied to adding circuit 42 which in turn processes the output of field memory 24 together with input still image signal SI. That is, adding cir cuit 42 subtracts the readout output of field memory 24 from input still image signal SI. The subtraction result is supplied to coefficient variable type coef ficient circuit 44 and is multiplied by U-1)/L.

Further, the output multiplied by (L-1)/L by means of coefficient circuit 44 is subtracted from the input still image signal in adding circuit 40. In this case, preset control signals are supplied from timing generation circuit 30 to field memory 24 and coefficient circuit 44 and coefficient (L-1)/L of coefficient cir cuit 44 is changed according to the preset control signals.

As in the first embodiment, an input still image signal whose level is multiplied by l/t and the readout output which is read out from field memory 24 and whose level is multiplied by (L-1)/L are obtained on the output side of adding circuit 40 in the second embodiment. Thus, with the noise reduction circuit of the above construction, the same effect as that of the first embodiment can be attained.

Further, in the second embodiment, since coefficient variable type coefficient circuit 44 is used, the circuit size can be reduced in comparison with the first embodiment in which a plurality of coefficient fixed type coefficient circuits are used.

As described above, in the first and second embodi- ments, a noise reduction circuit in which an input still image signal is recursively added at a field frequency is explained. However, the noise reduction circuit is not limited to these examples, and it can be applied to a circuit in which the input still image signal is recursively added for each frame, for example.

Now, other embodiments are explained with reference to Figs. 4 and 5. In this case, portions which are constructed and operated in the same manner as those in the first and second embodiments are denoted by the same reference numerals and the explanation thereof is omitted.

Fig. 4 is a block diagram showing the construction of a noise reduction circuit according to a third embodiment and is similar to that of the first embodiment shown in Fig. 1 except that the field memory is replaced by a frame memory. That is, a still image video signal supplied from input terminal 12 via A/D converter 14 is supplied to n coefficient circuits 161, 162, ---, and 16n and respectively multiplied by (1-K1), (1-K2)r --- 1 and (1-Kn), and at the same time supplied to timing generation circuit 30. The outputs of coefficient circuits 161, 162r ---, and 16n are selected by means of switch 18 according to control signals from timing generation circuit 30, and then supplied to adding circuit 20. The output of adding circuit 20 is supplied to output terminal 32 via D/A converter 2'2 and at the same time written into frame memory 46. Frame memory 46 is accessed in response to various timing signals generated from timing generation circuit 30 and the output thereof is supplied to coefficient circuits 261, 262, -# and 26. of addition frame number (n) and multiplied by K1, K2, and Kn, respectively. The outputs of coef ficient circuits 261, 262, ---, and 26n are selected by means of switch 28 according to a preset control signal from timing generation circuit 30, and then added to the selected output of switch 18 by means of adding circuit 20. In this way, a still image signal having noise component reduced is derived from adding circuit 20 via D/A converter 22 and output terminal 32.

Like the first embodiment, with the noise reduction circuit of the above construction according to the third embodiment, the addition coefficients of the input still image signal and the readout output of frame memory 46 are changed for each frame. That is, the input still image signal of t-th frame is multiplied by l/t and the output of frame memory 46 is multiplied by (L-1)/t so as to effect the noise reduction.

Fig. 5 is a block diagram showing a noise reduction circuit of a fourth embodiment which is similar to that of the second embodiment shown in Fig. 3 except that the field memory is replaced by a frame memory. That is, in

Fig. 5, an input still image signal supplied from input terminal 12 via A/D converter 14 is supplied to adding circuits 40 and 42 and to timing generation circuit 30.

The output of adding circuit 40 is supplied from D/A converter 22 to output terminal 32 and at the same time written into frame memory 46. The output of frame memory 46 is supplied to adding circuit 42 and processed together with input still image signal SI by means of adding circuit 42. That is, adding circuit 42 subtracts the readout output of frame memory 46 from input still image signal SI. The subtraction result is coefficient variable type coefficient circuit 44 and multiplied by Further, the output multiplied by U-1)/L by means of coefficient circuit 44 is subtracted from the input still image signal in adding circuit 40. In this case, preset control signals are supplied from timing generation circuit 30 to frame memory 46 and coefficient circuit 44 and coefficient (L-1)/ú of coefficient cir cuit 44 can be changed according to the preset control 23 signals.

Like the third embodiment, the input still image signal whose level ismultiplied by l/t and the readout output of frame memory 46 whose level is multiplied by (L-1)/L can be derived on the output side of adding circuit 40 in the above fourth embodiment. Thus, with the noise reduction circuit of the above construction, the same effect as those of the first to third embodiments can be attained.

Further, since coefficient variable type coefficient circuit 44 is used in the fourth embodiment. the circuit size can be reduced in comparison with the circuit in the third embodiment in which a plurality of coefficient fixed type coefficient circuits are used.

In the above embodiments, this invention is applied to a magnetic recording/reproducing apparatus. However, this invention is not limited to the above embodiments, and can be applied to a VTR camera, for example.

Further, a still image signal is supplied to input terminal 12 in the above embodiments. Howevert it is also possible to input a dynamic image signal in the following manner.

For example. in a case where the coefficient fixed type coefficient circuit is used as in the first embodiment, switches 18 and 28 are set to the preset switching positions by means of timing generation circuit 30. As a result, the same coefficient circuits are always selected from coefficient circuits 161, 162, ---, and 16n and coefficient circuits 261, 262, ---, and 26n. In this way, even when a dynamic image signal is supplied from input terminal 12, the noise reduction effect can be obtained in the same manner as in the case of a still image signal.

- 25

Claims

Claims:

1. A recursive noise reduction circuit for storing a still image video signal of at least one field and recursively adding the same to reduce the noise com- ponent of the still image video signal, comprising:

an A/D converter for converting the input still image video signal into a digital signal; current-coefficient means for multiplying the digital signal converted by said A/D converter by l/t (t denotes the reception order of the still image video signal); recursive adding means for sequentially and recursively adding a still image video signal of an immediately preceding field to the input still image video signal to remove the noise component contained in the input still image video signal from the digital signal multiplied by 1/ú by said current-coefficient means; field memory means for storing the output of at least one field of the recursive adding means; preceding-coefficient means for multiplying preceding data of the still image video signal of the immediately preceding field read out from said field memory means by (L-I)/I and then supplies the multipli cation result to said recursive adding means; timing generation means for accessing said field memory means at a preset timing in synchronism with the still image video signal and supplying a preset 26 control signal for selecting the preceding data of said precedingcoefficient means to said precedingcoefficient means; and a D/A converter for converting the digital signal having the noise component removed and supplied from said recursive adding means into an analog signal.

2. A recursive noise reduction circuit for storing a still image video signal of at least one field and recursively adding the same to reduce the noise com- ponent of the still image video signal, comprising:

an A/D converter for converting the input still image video signal into a digital signal; current-coefficient means for multiplying current data of the input still image video signal output from said A/D converter by (1-Kú) (ú denotes the reception order of the still image video signal); recursive adding means for sequentially recursiveadding a still image video signal of an immediately preceding field to the input still image video signal to remove the noise component contained in the input still image video signal from output of said currentcoefficient means; field memory means for storing the output of at least one field of the recursive adding means; preceding-coefficient means for multiplying preceding data of the still image video signal of the immediately preceding field read out from said field memory means by Kt and then supplies the multiplication result to said recursive adding means; timing generation means for accessing said field memory means at a preset timing in synchronism with the still image video signal and supplying a preset control signal for selecting the preceding data and the current data of said preceding- coefficient means and said current-coefficient means to said preceding- coefficient means and said current-coefficient means; and a D/A converter for converting the digital signal having the noise component removed and supplied from said recursive adding means into an analog signal.

3. A circuit according to claim 2, wherein each of said current-coefficient means and said preceding is coefficient means includes at least two coefficient circuit means, and said timing generation means gen erates a control signal for selecting said coefficient circuit means which multiplies the preceding data and current data in said preceding coefficient means and said current-coefficient means by a preset value.

4. A circuit according to claim 3, wherein said current-coefficient means and said preceding-coefficient means respectively include first and second switching means for selecting a desired one of coefficients from said at least two coefficient circuit means according to the control signal generated from said timing generation means.

1

5. A circuit according to claim 2, wherein said (i-KL) is Vt, and said Kt is (L-WL.

6. A circuit according to claim 4, wherein said timing generation means includes sync separation means for separating the input still image video signal into a vertical sync signal and a horizontal sync signal and supplying a preset control signal to said first and second switching means at a field frequency; and memory control means for controlling the write-in and readout of said field memory means according to the vertical and horizontal sync signals.

7. A circuit according to claim 1, wherein said preceding-coefficient means and said current-coefficient means include data adding means for adding the input still image video signal output from said A/D converter to the preceding data of the still image video signal in the immediately preceding field read out from said field memory means; and coefficient circuit means for multiplying the output of said data adding means by (L1)/L according to the control signal from said timing generating means and supplying the multiplication result to said recursive adding means.

8. A circuit according to claim 7, wherein the coefficient of said coefficient circuit means is selected according to the control signal from said timing generating means.

9. A circuit according to claim 8, wherein said timing generating means includes sync separation means for separating the input still image video signal into a vertical sync signal and a horizontal sync signal and supplying a preset control signal to select the coefficient of said coefficient means at a field frequency; and memory control means for controlling the write-in and readout of said field memory means according to the vertical and horizontal sync signals.

10. A noise reduction circuit for storing a still image video signal of at least one frame and recursively adding the same to reduce the noise component of the still image video signal, comprising:

an A/D converter for converting the input still image video signal into a digital signal; current-coefficient means for multiplying the digi tal signal converted by said A/D converter by l/t (ú denotes the reception order of the still image video signal); recursive adding means for sequentially and recur- sively adding a still image video signal of an immediately preceding frame to the input still image video signal to remove the noise component contained in the input still image video signal from the digital signal multiplied by l/t by means of said current-coefficient means; frame memory means for storing the output of at least one frame of said recursive adding means; i preceding-coefficient means for multiplying preceding data of the still image video signal of the immediately preceding frame read out from said frame memory means by U-1)/ú and then supplies the multipli- cation result to said recursive adding means; timing generation means for accessing said frame memory means at a preset timing in synchronism with the still image video signal and supplying a preset control signal for selecting the preceding data of said preceding- coefficient means to said precedingcoefficient means; and a D/A converter for converting the digital signal having the noise component removed and supplied from said recursive adding means into an analog signal.

11. A noise reduction circuit for storing a still image video signal of at least one frame and recursively adding the same to reduce the noise component of the still image video signal, comprising:

an A/D converter for converting the input still mage video signal into a digital signal; current-coefficient means for multiplying current data of the input still image video signal output from said A/D converter by (1-Kú) (ú denotes the reception order of the still image video signal); recursive adding means for sequentially and recursively adding a still image video signal of an immediately preceding frame to the input still image video 1 - 31 signal to remove the noise component contained in the input still image video signal from output of said current-coefficient; frame memory means for storing the output of at least one frame of said recursive adding means; preceding-coefficient means for multiplying preceding data of the still image video signal of the immediately preceding frame read out from said frame memory means by Kú and then supplies the multiplication result to said recursive adding means; timing generation means for accessing said frame memory means at a preset timing in synchronism with the still image video signal and supplying a preset control signal for selecting the preceding data and current data of said preceding-coefficient means and said current-coefficient means to said precedingcoefficient means and said current-coefficient means; and a D/A converter for converting the digital signal having the noise component removed and supplied from said recursive adding means into an analog signal.

12. A circuit according to claim 11, wherein each of said currentcoefficient means and said precedingcoefficient means includes at least two coefficient cir- cuit means, and said timing generation means generates a control signal for selecting said coefficient circuit means which multiplies the preceding data and current i data in said preceding coefficient means and said current-coefficient means by a preset value.

13. A circuit according to claim 12, wherein said current-coefficient means and said preceding-coefficient means respectively include first and second switching means for selecting a desired one of coefficients from said at least two coefficient circuit means according to the control signal generated from said timing generation means.

14. A circuit according to claim 11, wherein said (l-Kt) is 1/L, and said KZ is

i5. A circuit according to claim 13, wherein said timing generation means includes sync separation means for separating the input still image video signal into a is vertical sync signal and a horizontal sync signal and supplying a preset control signal to said first and second switching means at a frame frequency; and memory control means for controlling the write-in and readout of said frame memory means according to the vertical and horizontal sync signal s.

16. A circuit according to claim 10, wherein said preceding-coefficient means and said current-coefficient means include data adding means for adding the input still image video signal output from said A/D converter to the preceding data of the still image video signal in the immediately preceding frame read out from said frame memory means; and coefficient circuit means for multiplying the output of said data adding means by (t-l)/z according to the control signal from said timing generating means and supplying the multiplication result to said recursive adding means.

17. A circuit according to claim 16, wherein the coefficient of said coefficient circuit means is selected according to the control signal from said timing generating means.

18. A circuit according to claim 171 wherein said timing generating means includes sync separation means for separating the input still image video signal into a vertical sync signal and a horizontal sync signal and supplying a preset control signal to select the coef ficient of said coefficient means at a frame frequency; is and memory control means for controlling the write-in and readout of said frame memory means according to the vertical and horizontal sync signals.

19. A recursive noise reduction circuit, substan- tially as hereinbefore described with reference to Figs. 1 to 5 of the accompanying drawings.

Published 1990 at The Patent 0Mce, State House. 66 71 I-LghRolborn, London WC1R4TP- Further copies maybe obtainedfromThe Patent Ofrice. Sales Branch, St Mary Cray, Orpington, Kent BR5 3RD- Printed by Multiplex tecbnIques ltd. St Mary Cray, Kent, Con. L'S7