JPS61152171A - Digital ghost eliminating device - Google Patents

Abstract

PURPOSE:To obtain a sufficient ghost eliminating capacity with a small number of coefficient devices by adjusting the time difference between a television signal including ghost and a ghost signal by a variable delay circuit to eliminate the ghost with a digital transversal filter. CONSTITUTION:An input signal of an input terminal L1 is allowed to pass a transversal filter 212 consisting of unit time delay elements T, 2T, 4T, 8T, and 16T, a tape coefficient device 2121, and an adder 2124 after passing a variable delay circuit 211 which changes the delay time of the input signal. The value of the gain in the coefficient devide 2121 of the filter 212 and the delay time of the circuit 211 are stored in an equalizing unit memory 214. An adder 213 adds the signal, which is inputted to the input terminal I1 and passes the circuit 211 and the filter 212, and the input signal of an input terminal I2. Thus, the number of coefficient devices is reduced to eliminate the ghost enough.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a ghost removal device for automatically removing television ghosts, and more particularly to a digital ghost removal device that digitally performs ghost removal.

[Technical background of the invention]

Devices for automatically and digitally removing television ghosts using equalization circuits are known in the art. An example is shown in FIG.

The details of this configuration and operation are described in Reference 1 (Murakami et al. "Digitalized Ghost Automatic Eraser" Institute of Electronics and Communication Engineers Technical Research Report BMCJ 78-37, January 1978), but the outline is as follows. show.

This device is entirely digital, and a digital video signal containing ghosts is input to an equalization circuit 2 via an input terminal 1. As shown in FIG. 4, this equalization circuit 2 includes N+M unit time delay elements 201 (delay time T(set)), N+M+1 tap coefficient units 202 (digital multipliers), and each tap coefficient unit. Adder 203 and tap gain memory 204 that add the outputs of
The tap coefficient Gt (t) of this tap coefficient multiplier is set to an appropriate value by the control circuit 3, and the digital video signal from which the ghost has been removed is outputted to the output terminal 5.

The reference signal for removing ghosts is the differential waveform (b) of the trailing edge portion (6) of the vertical synchronization signal shown in FIG. The peak corresponding to the falling part of the trailing edge of the vertical synchronization signal is set as the time reference 0, and the sign of the differential value di here corresponds to the positive or negative of the residual ghost having the delay time iT. Therefore, the tap gain correction circuit 31 uses this differential value di to sequentially correct each tap gain according to the following equation.

Cf, new = C/, o 1 d-Δ, s g
n d i ・-------------
(2) (t'= -MNN, jkiO) Here, Clo, old is the tap gain before correction, Clo
, (16w is the tap gain after correction, Δ is a small positive correction coefficient, and the formula (2) is widely known as ZerOFOrC1ng method. Note that the center tap coefficient CO is C0
=1 ・−−−−−−−−−−−−−
−−−−−−−−−−(3) is fixed. Ghosts are removed by performing this sequential correction every time a vertical synchronization signal arrives (1/60 seconds). The sequence controller 4 controls the sequence of the control circuit 3 described above, and can be configured using, for example, a ROM.

There is also known a device for eliminating ghosts using a combination of fixed delay circuits and a transversal filter (Japanese Patent Laid-Open No. 158579/1983).

[Problems with background technology]

However, in the conventional digital ghost removal device as described above, a large number of coefficient units (multipliers) are required to perform sufficient ghost removal, and the general-purpose digital multipliers used for these coefficient units are expensive. Moreover, because of its large scale (one multiplier is one IC), a practical ghost removal device could not be obtained. on the other hand,
Although an analog equalization circuit using a CCD has been put to practical use as a ghost removal device, it has problems in terms of residual image and S/N ratio.

To explain the above problem more specifically, even if we use digital IC technology, which has made rapid progress in recent years,
At most, only about 10 multipliers can be integrated in C. This is because a multiplier with Bbtt)<Bbtt is required as a coefficient unit for a transversal filter for ghost removal, and at the latest technology level, 16bit
16bit CMO8 multiplier is 3.5-1)
5.0- (Reference 2: Yoshio Kaji
” A 45ns 16 X 16 CMO8Mul+
il) 1ier"IS8CC84WPM 8.1"
) Therefore, on a practical 7■X7- IC chip,
The CMOS multiplier of Bbit
(4) This is because approximately 9 pieces can be integrated from X7 3.5X5 8 8 . The ghost delay range that can be removed by the N-tap transparser/L/filter is NT (T is the sampling period 17' = 1/3
fsc1)/4fsc, (fsc (color subcarrier frequency 3.58MNZ)), so N=
10. If T = 70 ns to 100 ns, then NT = o, 7 μs to 1 μ −−−−−11111−−−−−−・(5), and this alone cannot be used as a transversal filter for ghost removal. was insufficient.

Therefore, the equalization circuit used in the ghost removal device that has already been put into practical use is described in Document 3 (Murakami et al. [Ghost Clean System] Toshiba Review Vo 1, 38 & 7, 1982).
June 2013), CCD4 Charge Cou
pled Device) ) 5 NX Bar 9 Lua
IA/#.

was used. However, since this is an analog signal processing device, it has led to an increase in unerased ghosts on the multiplication screen and a decrease in SIN.

Furthermore, the technique disclosed in Japanese Patent Application Laid-Open No. 56-158579 also has the problem that even if the ghost is removed at the stage of primary ghost removal, the J (ghost) remains.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and is a digital ghost removal method that does not require a large number of coefficient units, and has sufficient ghost removal performance to withstand practical use in terms of cost and hardware. The purpose of this invention is to provide a device and an essential digital equalization circuit for this device.

[Summary of the invention]

According to the present invention, even in a transversal filter having a large number of taps, only a few taps need to change the gain etc. to actually remove ghosts, and the other taps are necessary to adjust the time difference between the real signal and the ghost signal. We focus on the small points that exist, make adjustments, and use a digital transversal filter to actually remove ghosts.

If there are multiple ghosts, the ghosts are removed using the variable delay circuit and digital transversal filter as main components, and multiple digital equalization circuits each having a memory and an adder. The invention is a digital equalization circuit having the above configuration. The second invention uses this digital equalization circuit to convert a television signal including a ghost into a first one.
and a subtracter whose output is a signal that subtracts a second input from this input, and the output of the subtractor is input to the first input terminal of each digital equalization circuit, and each digital equalization The output of the circuit is sequentially input to the second input terminal of the digital equalization circuit in the next stage, and the output of the digital equalization circuit in the last stage is configured to be the second input to the subtracter. It is.

Further, in the third invention, a plurality of subtracters are used, the output of the subtracter in the previous stage is inputted to the second input terminal of the digital equalization circuit, and the output of this second output terminal is inputted to the subtracter in the subsequent stage. the second of
The first input of this subtracter is the output of the previous subtractor.

Furthermore, in the second and third aspects of the invention, by adding a digital equalization circuit), it is possible to obtain an apparatus with high ghost removal performance that can also remove biliary ghosts.

〔Effect of the invention〕

The present invention has a variable delay circuit that appropriately changes the time of the input signal to match it with the ghost signal, thereby providing a digital equalization circuit that requires fewer taps in the digital transversal filter. Moreover, since the ghost removal device of the present invention is constructed using the digital equalization circuit described above, the number of taps as a whole can be reduced.
It is possible to obtain a sufficiently practical digital ghost removal device that is low in cost, not very complicated in terms of hardware, and leaves little residue (8/N) to obtain a television signal.Using recent digital IC technology If used, the digital equalization circuit according to the present invention can be made into a single chip IC, so the cost will be less than that of a conventional CCD transversal filter, and there will be no problem. When a single digital equalization circuit cannot cope with the problem, it is sufficient to use at least as many digital equalization circuits as there are ghosts.However, especially in the case of ghost failure, a considerable improvement can be achieved by removing a small number of high-level ghosts. Since the effect can be obtained, it is not necessarily necessary to prepare as many equalization circuits as there are ghosts.
In many cases, it is sufficient to prepare only the number of visible ghosts. In other words, this equalization circuit can be used depending on the degree of ghost disturbance, so it is possible to remove ghosts with good cost performance depending on each user. equipment can be provided.

Further, the digital equalization circuit of the first invention has two input terminals.
Another advantage is that there is only one output terminal, which is a small number of pins.

Further, in the second aspect of the present invention, ghosts are removed in the form of feedback, and the ghost removal performance is particularly advantageous.

Furthermore, in the third aspect of the present invention, although the performance is not so great because it is a feedforward type, the number of input/output terminals of the digital equalization circuit used is two, and the overall configuration is simple. is obtained.

[Embodiments of the invention]

Hereinafter, the present invention will be specifically explained using the drawings.

FIG. 1 shows an embodiment of a digital equalization circuit, and FIG. 2 shows an embodiment of a digital ghost removal device constructed using this circuit (hereinafter referred to as an equalization unit). The digital video signal containing the ghost is input to one of the adders 29 in the equalization circuit. The output of the subtracter 4 is input to the output terminal 5 and the differentiation circuit 33 in the control circuit 3, and is also input to the input terminal check 1 of each equalization unit 21-24.

Output terminal 01 of equalization unit 2t' ((=4.3.2)
is equalization unit 2j (j=i-1, i=4.3.2)
is input to the other input terminal of the other. Equalization unit 21~
24 all have the same configuration, and the configuration is shown in FIG. 4. The input terminal 1) of the equalization unit 21 is the variable delay circuit 21
), and is connected to one input terminal of the switch S1 and the other input terminal of the switch S1 via a delay element D1 having a delay amount T. The output terminal of the switch S1 is connected to the input terminal of the switch S2, Delay element D2 having a delay amount port
is connected to the other input terminal of the switch S2.

Repeat this same process, S2, D3, D4, S4
, D5, and S5 are connected.

Here, each delay element f) (is a shift register or
It consists of 1° latches connected in series.

Therefore, the switch St'(t'=l, . . .
5) is the delay amount memory DL of the 1 equalization unit memory 214
By setting the value of , a variable delay circuit that provides an arbitrary delay (in T increments) from θ to 31T is configured. Signal lines are each connected to one input of a digital multiplier 2122, which is a tap coefficient multiplier, and the other input of the digital multiplier 2122 is connected to tap gain memories C1-C5 of the equalization unit memory 214. The output of each tap coefficient unit 2122 is sent to the adder 212
4 is added. That is, the output of adder 2124 is
It has the delay amount given by the variable delay circuit 21) as an offset, and is the output of a digital transversal filter with a variable tap count of 5 given by the transversal filter 212. The output of this adder 2124 is
In the adder 213, it is added to the output signal of the equalization unit 22 obtained from the other input terminal CHE 2 of the equalization unit 21, and is connected to the output terminal 01 of the equalization unit 21.

That is, the output signal obtained from the output terminal 1) of this equalization unit 21 is connected to the terminal as shown in the second sentence. “The control circuit 3 controls the equalization unit memory 214 of each equalization unit 21, 22, 23, and 24, and the output waveform memory U that receives the output dk of the differentiation circuit 33, and the judgment and calculation The chip selector 38 uses the input waveform memory 34, the RAM 35, and the micro precessor 37 that performs , RoM36 and equalization unit 2
1.22, 23.24. A chip select signal is applied to the chip select signal bus 63.

It is shown in Document 3 that ghosts can be removed by controlling the digital transversal filter 212 using the control circuit 3 as described above. The control will be explained according to the flowchart shown in FIG.

First, an equalization unit register value t' indicating that the equalization unit 21 is to be controlled is set to 1. (Block 70
1) oNext, the output signal yk of the leading edge of the vertical synchronization signal shown in FIG.
Load into output waveform memory (block 702) 6
Next, the maximum peak of the differential value dk shown in FIG. 5 Φ) and (d) is detected, and its sample timing is set as the time reference Tφ (block 703).

Next, in order to allocate the maximum ghost to the equalization unit 21, the maximum peak value dTφ10 of the differential value dk after the sample timing Tψ+5 is detected (block 704).
. Next, the delay amount of the variable delay circuit 21) of the equalization unit 21 is set to (Kl-2)T.

(Block 705) o Specifically, the chip selector 38 outputs a chip select signal to the equalization unit 21, the micro processor 37 outputs address information instructing the delay amount memory of the equalization unit memory 214, and the micro 1 converted to binary from the processor
A value of -2 is sent to the data bus 62. In this way, the delay amount memory (DL) value in the equalization unit memory 214 in the equalization unit 21 is converted into a binary number and set to 1-2, and based on that value, the variable delay circuit 21) switches 81 to S5 so that the delay amount becomes (Kl-2)T.
is set.

Next, the tap gain modification number register <e> is set to 1 (block 706). Next, just as in block 702, the differential value dk of the output signal yk is stored in the output waveform memory 34.
(block 707). Since the acquisition start timing at this time is the same, the maximum peak (time reference) is at the sample timing Tφ, as shown in FIG. Next, each tap gain 01 to C5 of the equalization unit 21 is modified according to the following formula (block 708).

Cj, new=cj, old+Δ, sgn dT
ψ+kt-a+j (6) j=1.2.3.4.5- Here, Cj, new is the j-th tap gain after modification,
Cj, Old is the j-th tap gain before correction, Δ is a small positive correction coefficient, sgn dTψ+5c1-a+j is
This is the sign of the sample value of the differential value d of the output signal y corresponding to 1+3+J at the sample timing Tψ10. Specifically, the tap gain Cj,ol read out from the equalization unit memory 214 to the microprocessor 37
d and the differential value dTψ1kl−a+j read out by the microprocessor 37 from the output waveform memory 34 as (
6), the microprocessor 37 calculates it, and the calculation result CJ % n eVf is written into the equalization unit memory 214.

Next, the tap gain modification number register (1) is incremented by 1, in this case to 2 (block 709), and then it is determined whether or not the predetermined number of modifications (NTAP) has been performed (block 71O). If block 707
Go back and modify the tap gain iteratively. Furthermore, if the process has been repeated a predetermined number of times, the equalization unit register (1) is increased by 1, in this case to 2, in order to move on to control the next equalization unit 22 (block 71). Next, it is determined whether or not a predetermined number of equalization units (in this case, 4) have been controlled (block 712).
The equalization unit 22) is controlled. Also, if it is being done, all controls will be stopped. (Block 713Σ In this way, the maximum ghost g of the delay time KIT shown in FIG.
1 is removed by the equalization unit 21, and the second largest ghost g2 with a delay time of 2T is removed by the equalization unit 22.

Note that the range of delay time that the equalization units 21 and 22 have is the AI (KIT-2T) shown in FIG. 5 (Q).

KIT+2T), A2 (2T+2 to K2T-2T%
T Since the equalization is performed centering around the noise peak), there is no problem with ghost removal performance.

Further, although the transversal filter in this embodiment is of a so-called output weighted type, the present invention is also effective for an input weighted type as shown in FIG. That is, it is also possible to use a transversal filter in which the output of the variable delay circuit 21) is weighted by each tap coefficient unit 2122, and then outputted via the delay time i-column 2124.

In addition, as a variable delay circuit, a RAM as shown in FIG.
may also be used.

It is known that RAM is used as a variable delay circuit, but in order to repeatedly count the address counter 21) 2 by the amount corresponding to the delay amount, the first half of each counter output is used to read the RAM 21) 1. The second half of the time is allocated for writing, and before the end of the read time, the output data of the RAM 21)1 is latched by the latch circuit k21)4 (to be synchronized with the clock, it is then latched) It is sufficient to latch it in synchronization with the clock on the circuit board 21)5.

The load generating circuit 21) 3 generates read/write pulses for the RAM 21) 1 and clocks for the latch circuit t(21) 5).

Each timing shown in FIG. 8 is shown in FIG. 9.

In this way, ghosts can be effectively removed by the digitized ghost removal circuit using the digital equalization circuit shown in the first to third embodiments.

FIG. 10 shows a second embodiment of the digital equalization circuit.

This is because the connection order of the digital transversal filter and the variable delay circuit is reversed in the first embodiment shown in FIG. 1, and its operation is the same as that of the above embodiment.

Figure 1) shows a third embodiment of the digital equalization circuit.

This latch 215 is connected after the adder 213 of the second embodiment shown in FIG.
5 is to align the delay time ζadd of the adder 213 with the clock time T. If this is not used, when equalization units are connected in multiple stages as shown in Figure 4,
The following inconveniences may occur.

That is, in general, the adder 213 has an operation execution time ζad
d, the cancellation signal passing through the N stages of equalization units undergoes a delay of N, ζadd. If this value exceeds the clock interval T, the above-mentioned problem will not occur if a latch is inserted later to align the delay time with the clock interval and provide a cancellation signal to the next equalization unit.

- However, 1 In this case, the delay amount increases by T as the equalization unit goes to the previous stage (the delay amount of the cancellation signal of the equalization unit 21 in FIG. 1 is equalized by the equalization unit 2
2 increases by 2T, 23 increases by 3T, and equalization unit 24 increases by 4T), the delay amount DL must be reduced by that amount. Further, this latch may be located between the adder 213 and the input terminal I2, or may be located at any of the positions simultaneously.

FIG. 12 shows a fourth embodiment of the digital equalization circuit, which has variable delay circuits on both sides of a transversal filter. This is also DL = DL 1+DI, 2
If the relationship is given, the same operation and effect as in FIG. 1 will be obtained. Further, one of the two delay circuits may be a fixed delay circuit.

Note that the number of taps of the digital transversal filter in each unit of the digital equalization circuit according to the present application, the amount of delay of the variable delay circuit, and the delay range thereof are not particularly limited.

Furthermore, the method of connecting each equalization unit is not limited; for example, as shown in FIG. 13, the equalization units in FIG. The present invention is effective even if each equalization unit in FIG. 13 is a feedforward connection, but the present invention is effective even if it is a feedback connection.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the digital equalization circuit of the present invention. FIG. 2 is a block diagram of an embodiment of the digital ghost removal device of the present invention. Figure 3 is a block diagram of a conventional ghost removal device.
The figure is a configuration diagram of a transversal filter.
FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention. FIG. 6 is an operation flowchart of the ghost removal device of FIG. 2; FIG. 7 is a configuration diagram of another embodiment of the digital transversal filter used in the present invention. FIG. 8 is a configuration diagram of another embodiment of the variable delay circuit used in the present invention. FIG. 9 is a timing diagram of the variable delay circuit of FIG. 8. FIG. 10 is a configuration diagram of a second embodiment of the digital equalization circuit of the present invention. 1) Figure 1 is a third configuration diagram of the digital equalization circuit of the present invention. FIG. 4 is a fourth configuration diagram of the digital equalization circuit of the present invention. FIG. 13 is a diagram showing another example of a connection method of a digital equalization circuit to which the present invention is applied. I 1 - - - - - - - First input terminal 21) - - - - Variable delay circuit 212 - - Digital transversal filter 213 - - - - Adder 214 - - ---・Memory 61 --- Output terminal agent Patent attorney Noriyuki Chika (and 1 other person) * 3
Decoy * + Illustration ('%,,. 噌 4 9茅 子 子 寥 7 q 寥 δ 因芥 9 对 10 fig. tt fig. T ri

Claims (6)

[Claims] (1) A digital transversal filter consisting of a variable delay circuit that changes the time for delaying an input signal, a plurality of unit time delay elements, a tap coefficient unit, and a first adder; and the taps of this transversal filter. a memory for storing gain values in the coefficient multiplier and delay times in the variable delay circuit; and a second input terminal with a signal entering the first input terminal and passing through the variable delay circuit and the digital transversal filter as the first input; and a second adder that takes the signal input to the input signal as its second input and calculates the sum of both signals. (2) The signal input to the first input terminal is input to a variable delay circuit, and the output of this variable delay circuit is input to a digital transversal filter. Digital equalization circuit. (3) The signal input to the first input terminal is input to a digital transversal filter, and the output of this transversal filter is input to a variable delay circuit. Digital equalization circuit. (4) The variable delay circuit consists of a first variable delay circuit and a second variable delay circuit, and the signal input to the first input terminal is input to the first variable delay circuit, and the signal input to the first input terminal is input to the first variable delay circuit. The output is input to a digital transversal filter,
Claim 1, characterized in that the output of this transversal filter is input to a second variable delay circuit.
The digital equalization circuit described in . (5) A subtracter whose first input is a television signal containing ghosts and whose output is a signal obtained by subtracting a second input from this input; and the output of this subtractor is input to each first input terminal. a digital equalization circuit whose output is input to the second input terminal of the next stage in sequence, and whose output from the last stage is the second input of the subtracter; a control circuit that controls an equalization circuit; the digital equalization circuit includes: a variable delay circuit that changes the delay time of an input signal; a plurality of unit time delay elements and tap coefficient units; and a first adder. a digital transversal filter comprising: a memory for storing a gain value in the tap coefficient unit of the transversal filter and a delay time in the variable delay circuit; A second adder which takes a signal passed through a filter as a first input, a signal input to a second input terminal as a second input, and calculates the sum of both signals. Device. (6) A multi-stage subtracter that sequentially outputs a signal obtained by subtracting the second input from the output of the previous stage in which the output of the previous stage becomes the first input of the subsequent stage, and the output of the previous stage of these subtractors is connected to the second input terminal. a plurality of digital equalization circuits in which the output of the second output terminal is input to the second output terminal as the second input of the subtracter in the subsequent stage, and control for controlling the digital equalization circuit by using the output of the subtractor in the final stage as the input. The digital equalization circuit is comprised of: a variable delay circuit that changes the time to which an input signal is delayed; a digital transversal filter that includes a plurality of unit time delay elements, a tap coefficient unit, and a first adder; a memory for storing the gain value in the tap coefficient unit and the delay time in the variable delay circuit of this transversal filter; and a second adder which takes a signal inputted to a second input terminal as its second input and calculates the sum of both signals.