JPH04249982A - Digital processing ghost elimination device - Google Patents

Abstract

PURPOSE:To realize the digital processing ghost elimination device brought into practical use through the reduction of a circuit scale. CONSTITUTION:An output of a subtractor 29 is given to a 1st input terminal I1 of equalization units 21, 22, 23, 24 connected in parallel. A variable delay circuit of each equalization unit delays an inputted signal by an equalization quantity in response to a delay time of ghost and the result is given to a transversal filter. An output of the transversal filter is added to an output from other equalization unit and an output of an adder at a first stage is given to a subtractor 29 as a ghost cancellation signal. The subtractor 29 subtracts the ghost cancel signal from a television signal to output an output from which ghost is eliminated. Thus, the ghost in the delay time of a wide range is eliminated with less number of taps.

Description

[Detailed description of the invention]

[Object of the invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ghost removal apparatus for automatically removing television ghosts, and more particularly to a digital ghost removal apparatus for digitally removing ghosts.

0002

BACKGROUND OF THE INVENTION Apparatus for automatically and digitally removing television ghosts using digital equalization circuits are known in the art. An example is shown in FIG.

[0003] Details of this configuration and operation can be found in Reference 1 (Murakami et al. ``Digitalized automatic ghost erasing device'' Institute of Electronics and Communication Engineers technical research report EMCJ78-37, November 1978)
The outline is shown below. This device is entirely digital, and a digital video signal containing ghosts is input to a digital equalization circuit 2 via an input terminal 1. This digital equalization circuit 2 is shown in FIG.
4, N+M unit delay elements 201 (
It consists of a delay time T [sec]), N+M+1 tap coefficient units 202 (digital multipliers), an adder 203 for adding together the outputs of each tap coefficient unit, and a tap gain memory 204. The tap coefficient of this tap coefficient machine (
C-M to CN) are set to appropriate values by the control circuit 3, and a digital video signal from which ghosts have been removed is outputted to the output terminal 5.

The reference signal for removing ghosts is the differential waveform (b) of the trailing edge portion (a) of the vertical synchronizing signal shown in FIG. ), the peak corresponding to the falling portion of the trailing edge of the vertical synchronization signal is set as time reference 0, and each peak di after this time reference is detected.

[0005]

The sign of this differential value di is the delay time iT
corresponds to the positive and negative residual ghosts. Therefore, the tap gain correction circuit 31 uses this differential value di to sequentially correct each tap gain according to the following equation.

[0007]

[0008] Here, Ci,old is the tap gain before modification, Ci,new is the tap gain after modification, Δ is a small positive modification coefficient, and equation (2) is expressed as Zero Force
This method is widely known as the ing method. Note that the center tap coefficient C0 is C0 = 1
...(3) is fixed. Ghosts are removed by performing this sequential correction every time a vertical synchronization signal arrives (1/60 seconds). The sequence controller 4 controls the sequence of the control circuit 3 described above, and can be configured using, for example, a ROM.

[0009] A device for eliminating ghosts using a combination of fixed delay circuits and a transversal filter is also known (Japanese Patent Laid-Open No. 158579/1983).

0010

[Problems to be Solved by the Invention] However, in the conventional digital ghost removal device as described above, in order to perform sufficient ghost removal, a very large number of coefficient units (multipliers) are required. A practical ghost removal device has not been obtained because the general-purpose digital multiplier used in the device is expensive and large-scale (one multiplier is one IC). On the other hand, although an analog equalization circuit using a CCD has been put to practical use as a ghost removal device, it has problems in terms of residual ghosting and S/N ratio.

To describe the above problem in more detail, even if digital IC technology, which has made rapid progress in recent years, is used, only about 10 multipliers can be integrated into one IC at most. This is because an 8 bit x 8 bit multiplier is required as a coefficient unit for a transversal filter for ghost removal, and at the latest technology level, a 16 bit multiplier is required.
t×16bit CMOS multiplier is 3.5mm×
5.0 mm (Reference 2: Yoshio Kaj
i ″A45ns 16 ×16CMOS M
ultiplier ″ISSCC84 WPM8
．． 1) Therefore, the practical chip size is 7mm x 7
There is an 8 bit x 8 bit CM on the mm IC chip.
The OS multiplier is

0012

This is because approximately nine pieces can be integrated.

The delay range of ghosts that can be removed by the N-tap transversal filter is NT (T is the sampling period, T = 1/3 fsc, 1/4 fsc, (fsc (color subcarrier frequency ≒ 3.58 MHz)). , N=10, T=70~100ns, NT
=0.7~1μs
...(5), and this alone was insufficient as a transversal filter for ghost removal. Therefore, the equalization circuit used in the ghost removal device that has already been put into practical use is described in Document 3 (Murakami et al. "Ghost Clean System" Toshiba Review No. 1.38 No. 7)
June 1982), CCD (Charge
(Coupled Device) used a transversal filter. However, since this is an analog signal processing device, the linearity of the coefficient unit (multiplier) and the overall S/N were insufficient. This drawback, when viewed as a ghost removal device, has led to an increase in ghosts remaining on the screen and a decrease in S/N.

[0015] Furthermore, the technique disclosed in Japanese Patent Application Laid-Open No. 56-158579 also has the problem that grandchild ghosts remain even if the ghosts are removed at the stage of primary ghost removal.

The present invention has been made in view of the above problems, and is a digitalization method that does not require a large number of coefficient units, is practical in terms of cost and hardware, and has sufficient ghost removal performance. An object of the present invention is to provide a ghost removal device.

[Configuration of the invention]

[Means for Solving the Problems] A digital ghost removal device according to the present invention includes a subtracter that subtracts and outputs a ghost cancellation signal from a television signal including a ghost;
It is constituted by a plurality of digital equalization circuits connected in parallel, and the output of the subtracter is inputted to each first input terminal of the digital equalization circuit, and the output of the subtracter is inputted to the second output terminal of each of the digital equalization circuits. Second to remove ghost
a group of digital equalization circuits that output the output of the digital equalization circuit and supply the ghost cancellation signal to the subtracter from a second output terminal of the digital equalization circuit in the first stage; The digital equalization circuit includes a variable delay circuit that changes the delay time of the signal input to the first input terminal and outputs the delayed signal, and an input terminal that controls the circuit. A plurality of commonly connected tap coefficient units, a plurality of first adders for adding the outputs of these coefficient units, and the first addition in the next stage sequentially by delaying the output of the tap coefficient unit by a unit time. an input-weighted digital transversal filter, which is composed of a plurality of unit time delay elements applied to the input circuit, and the output of the variable delay circuit is inputted to the input terminal; a memory for storing the delay time in the variable delay circuit; and a memory that stores the delay time in the variable delay circuit; It is equipped with a second adder that outputs from a terminal.

[0018]

In the present invention, the variable delay circuit of the digital equalization circuit adjusts the time difference between the television signal containing a ghost and the ghost signal. A plurality of ghosts having different delay times are removed by an input-weighted digital transversal filter of each digital equalization circuit. Second
The adder adds the output of the digital transversal filter and the second output of another digital equalization circuit and outputs the result. In this way, from the first stage digital equalization circuit,
A ghost cancellation signal is generated to eliminate multiple ghosts for a predetermined delay time. The subtracter subtracts the ghost cancellation signal from the input television signal to output a ghost-free output.

[0019]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital ghost removal device according to the present invention.

In FIG. 1, a digital video signal containing ghosts is input to one of the subtracters 29 in the equalization circuit. The output of the subtracter 29 is input to the output terminal 5 and the differentiation circuit 33 in the control circuit 3, and is also input to the first input terminal I1 of the digital equalization circuit (hereinafter referred to as equalization unit) 21, Equalization unit 2i (i=1,
2, 3), the first output terminal O1 of the equalization unit 2j
(j=i+1, i=1, 2, 3) first input terminal I1
Connect to. The second input terminal I2 of the equalization unit 24
is grounded and 0 is input. Also, the second output terminal O2 of the equalization unit 2i (i=4, 3, 2)
is equalization unit 2j (j=i-1, i=4,3,2)
is connected to the second input terminal I2 of the equalization unit 21
The output from the second output terminal O2 is inputted to the other input terminal of the subtracter 29 as a ghost cancellation signal.

The equalization units 21 to 24 all have the same configuration, and the configuration is shown in FIG. Equalization unit 2
The first input terminal I1 of the switch S1 is input to the variable delay circuit 211, and is connected to one input terminal of the switch S1 and the delay amount T.
is connected to the other input terminal of the switch S1 through a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element D1 having a delay element of The output terminal of the switch S1 is connected to the other input terminal of the switch S2 via the input terminal of the switch S2 and a delay element D2 having a delay amount of 2T. Hereafter, by repeating this same process, S2, D3,
S3, D4, S4, D5, and S5 are connected. Here, each delay element Di is a shift register or
It consists of i latches connected in series.

Therefore, the switch Si (i=1,...,5)
is set by the value of the delay amount memory DL of the equalization unit memory 214, thereby constructing a variable delay circuit that provides an arbitrary delay (in T increments) from 0 to 31T. The output of switch S5 is input to delay circuit 216. The purpose of this delay circuit 216 is to connect switches S1 to S5.
The purpose is to align the delay time of the signal given by the clock time T with the clock time T.

The output of the delay circuit 216 is output from the variable delay circuit 2
11 is connected to one input of a digital multiplier 2122 which is a respective tap coefficient unit of the weighting circuit 220 in the digital transversal filter 212, and the other input of the digital multiplier 2122 is connected to the equalization unit memory 214. are connected to the tap gain memories C1 to C5. The output of the multiplier 2122 is input to the adder of each tap of the tapped delay circuit 221, and each input signal is repeatedly delayed and added, and then output to the adder 213. In other words, the output of the final stage is output from the variable delay circuit 211.
It has the delay amount given by as an offset, and is the output of a digital filter with a variable number of taps of 5 given by the transversal filter 212.

The output of this transversal filter 212 is added to the output signal of the equalization unit 22 obtained from the second input terminal I2 of the equalization unit 21 in an adder 213 with a signal delayed in a delay circuit 218. The signal is input to the delay circuit 215. These two delay circuits 215,
The purpose of 218 is to align the delay time of the input signal from the input terminal and the output signal from transversal filter 212 to clock time T.

The output from the delay circuit 215 is connected to the second output terminal O2 of the equalization unit 21. That is, the output signal obtained from the second output terminal O2 of this equalization unit 21 is transmitted to each equalization unit 24, 23, 22,
21 and is connected to the other input terminal of the subtracter 29.

Furthermore, the variable delay circuit 2 of the equalization unit 21
The output of 11 becomes the input of the delay circuit 217, is delayed by 2T time, and is output to the first output terminal O1. The first output terminal O1 of the equalization unit 21 is connected to the first input terminal I1 of the equalization unit 22, and the output of the first output terminal O1 of the equalization unit 21 is connected to the first output terminal I1 of the equalization unit 21. By delaying the output by 2T time, the delay circuit 216 and the delay circuit 215 of the variable delay circuit of the equalization unit 22 are delayed by the delay circuit 218 of the equalization unit 21 and the digital transversal filter 212 of the equalization unit 21. When the maximum time delay (5T time) can be compensated for and one or more equalization units are connected, the minimum tap interval at the connection point can be set to T.

That is, from the output of the subtractor 29, let the delay time of the ghost removal signal from each tap of the I-th equalization unit be RT~(R+4)·T, and
If the minimum interval is between equalization units in the tier, then (I+1)
The delay time of the ghost removal signal of each tap in the stage is (R+
3)・T~(R+7)T. By the way, delay circuits 218 and 215 are included between the second input terminal I2 and the second output terminal O2 of the equalization unit, and the ghost removal signal of the I-th equalization unit is sent to the subtracter 29. It is delayed by (2I-1)·T time before it is input, and (I
The ghost removal signal of the equalization unit of the +1)th stage is (2
I+1)・T time delay. As a result, the delay time of the ghost removal signal from each tap of the I-th equalization unit input to the subtracter 29 is (R+2I-1)·T~(
R+2I+3)・T, and the delay time of the ghost removal signal from each tap of the (I+1)th equalization unit is:
(R+2I+4)·T to (R+2I+8)T, and ghosts can be continuously removed even at the connection points of the equalization units. Alternatively, the delay circuit 217 may be omitted and the adjustment may be performed using the variable delay circuit 211 at the subsequent stage.

In the embodiment, the minimum delay amount of the variable delay circuit 211 of the equalization units 24 to 21 is T, but the minimum delay amount of the variable delay circuit 211 is
Not necessarily. Next, in the equalization unit 21,

0
029]

In the case of [0030], N=S+M+Q
...If the relationship (7) is satisfied, and the delay amount of the variable delay circuit of each equalization unit is minimized, the range of the ghost removal signal from each equalization unit is

[0031]

##EQU1## The minimum delay between equalization units is T, and ghosts can be removed continuously. In addition, formula (7)
Instead of, N>S+M+Q
...(9) may be the relationship, and in this case it can be adjusted by a variable delay circuit.

Here, in the first embodiment, FIG.

[
0034

4, the delay circuit 218 in FIG. 2 is replaced by the delay circuit 230, and the delay circuit 21
Perform the same operation as in Figure 2 except that 7 is missing.

00
36]

This is the case. In FIG. 5, the delay circuit 217 in FIG. 2 is eliminated, and the input signal from the input terminal I2 is delayed by T in the delay circuit 218, and then supplied to the digital transversal filter 212, and the adder 231 in the transversal filter. The same operation as in Figure 2 is performed except that the addition is made in

[0038]

This is the case. 6, the delay circuit 217 is eliminated in FIG. 2, and the transversal filter 2
The operation is the same as in Fig. 2, except that the number of taps in 12 has become 8 taps, and the minimum delay amount of the variable delay circuit has become 6·T.

[0040]

This is the case.

Next, control of each equalization unit in FIG. 2 will be described. The control circuit 3 controls the equalization unit memories 214 of the equalization units 21, 22, 23, and 24, and performs judgment and calculations with the output waveform memory 34, which receives the output dk of the differentiation circuit 33. microprocessor 3
7, a ROM 36 that holds its program, a RAM 35 that holds various data under control, and equalization units 21, 22, 23, and 24 are connected to an address bus 6, respectively.
1 and a data bus 62. A control signal from the microprocessor 37 via the address bus 62 causes the chip selector 38 to select the output waveform memory 34,
RAM35, ROM36 and equalization units 21, 22, 2
A chip select signal is applied to the chips 3 and 24 by a chip select signal bus 63. It is shown in Document 3 that ghosts can be removed by controlling the general transversal filter shown in FIG. 14 using such a control circuit. The control of steps 23 and 24 will be shown according to the flowchart shown in FIG.

Normally, the shorter the delay time, the larger the ghost, so here we will describe a simple control that sequentially finds the largest ghost and allocates equalization units. However, if there are large and small ghosts regardless of the delay time, it is sufficient to detect the number of equalization units in order from the largest ghost, and then allocate equalization units in order from the ghost with the shortest delay time. Such control can also be easily realized using a microprocessor.

That is, the equalization unit register value i, which indicates that the equalization unit 21 is controlled, is set to 1 (
block 701). Next, the output signal yk of the leading edge of the vertical synchronization signal shown in FIG.
k to the output waveform memory 34 (block 702). Next, the differential value dk shown in FIGS. 3(b) and (d)
The maximum peak of is detected, and its sample timing is set as the time reference Tφ (block 703). Next, in order to allocate the maximum ghost to the equalization unit 21, the maximum peak value d of the differential value dk after the sample timing Tφ+5
Tφ+Ki (i=1, 2, 3, . . . ) is detected (block 704). Next, the delay amount of the variable delay circuit 211 of the equalization unit 21 is set to (K1-4)T (block 705). When i≧2, (Ki −Ki−1 −4
)・Set to T. Specifically, the chip selector 38
A chip select signal is output from the microprocessor 37 to the equalization unit memory 2.
14, and outputs the values of K1-5 converted into binary numbers from the microprocessor to the data bus 62. In this way, the delay amount memory (DL) value in the equalization unit memory 214 in the equalization unit 21 is set to the binary number K1-4,
Based on that value, the delay amount of the variable delay circuit 211 is set to (K
1-4) Switches S1 to S5 are set so that T is reached.

Next, the tap gain modification number register (m) is set to 1 (block 706). Next, block 7
02, the differential value dk of the output signal yk is taken into the output waveform memory 34 (block 707). Since the acquisition start timing at this time is the same, the maximum peak (time reference) is at the sample timing Tφ, as shown in FIG. Next, each tap gain C1 to C5 of the equalization unit 21 is modified according to the following formula (block 708).

[0046]

Here, Cj,new is the j-th tap gain after modification, Cj,old is the j-th tap gain before modification, Δ is a small positive modification coefficient, sgn dTφ+K
1-3+j is the sample timing Tφ+K1-3+j
is the sign of the sample value of the differential value d of the output signal y corresponding to . Specifically, equalization unit memory 2
14 to the microprocessor 37, and the differential value dTφ+K1-3 read from the output waveform memory 34 to the microprocessor 37.
+j according to equation (14), the microprocessor 37
The calculation result Cj,new may be written into the equalization unit memory 214.

Next, tap gain modification number register (m)
Increase by 1, in this case to 2 (block 709)
. Next, it is determined whether or not the tap gain has been modified a predetermined number of times (NTAP) (block 701). If the modification has not been performed the predetermined number of times, the process returns to block 707 and the tap gain is repeatedly modified. Also, if the equalization unit 2 has been used a predetermined number of times, the next equalization unit 2
2, the equalization unit register (i) is incremented by 1, in this case to 2 (block 711). Next, it is determined whether or not a predetermined number of equalization units (4 in this case) have been controlled (block 712). If control has not been performed, the process returns to block 702 and controls the next equalization unit (4).
In this case, the equalization unit 22) is controlled. If so, all controls are stopped (block 713). In this way, the delay time K1 shown in FIG.
The largest ghost g1 of T is removed by the equalization unit 21, and the second largest ghost g2 of T is removed by the delay time K2.
is removed in equalization unit 22.

Note that the range of delay times handled by the equalization units 21 and 22 is A1 [K1
T-2T, K1 T+2T], A2 [K2 T-2
T, K2 T+2T]. In addition, in the case where there are two ghosts, equalization units 23 and 24 are essentially unnecessary, but even if they exist, the equalization units 23 and 24 are used to control the maximum peak (in this case, the peak of noise) of the differential value d of the output signal y. Since equalization is performed at each center, there is no problem with ghost removal performance.

Further, the length of the variable delay line may be the maximum length of the delay time between adjacent ghosts, and in this embodiment, the maximum length is 143·T=(34×3+31+3+4
+3) Can remove ghosts up to a length of T.

The present invention is also effective even when a RAM as shown in FIG. 8 is used as the variable delay circuit. In addition, R
It is well known that AM is used as a variable delay circuit, but the address counter 2112 is repeatedly counted by the amount corresponding to the delay amount, the first half of each counter output is allocated to reading the RAM 2112, and the second half is used for writing. and the RA before the end of that lead's time.
In order to latch the output data of M2111 in the first latch circuit 2114 and synchronize it with the clock, it is necessary to subsequently latch it in the latch circuit 2115 in synchronization with the clock. R
A control generation circuit 2113 generates a read/write pulse for the AM 2111 and a clock for the second latch circuit 2115. FIG. 9 shows each timing in FIG. 8.

[0052] The digital ghost removal apparatus configured as described above in which a plurality of digital equalization circuits (equalization units) having the same circuit configuration are connected can effectively remove ghosts.

FIG. 10 shows another example of the digital equalization circuit. This is simply a reversal of the connection between the digital transversal filter and the variable delay circuit in FIG. The effect is the same.

FIG. 11 shows another example of a digital equalization circuit, which has variable delay circuits on both sides of a digital transversal filter. This also has similar operations and effects, except that the first variable delay circuit is used to delay the transversal filter of the equalization unit connected downstream.

Furthermore, it is clear that one of the two delay circuits may be a fixed delay circuit.

Further, the number of taps of the digital transversal filter in each unit of the digital equalization circuit in FIG. 1, the amount of delay of the variable delay circuit, and the delay range thereof are not particularly limited.

FIG. 12 is a block diagram showing a digital ghost removal apparatus according to another embodiment of the present invention. Figure 1
2, the same components as in FIG. The present invention does not limit the connection method of each equalization unit, and digital equalization circuits may be connected in parallel.

That is, as shown in FIG. 12, the equalization units 21, 22, 23, and 24 have their first input terminals I1 commonly connected. Each equalization unit 24, 23, 22
, 21 receives the output of the subtracter 29. The outputs from the second output terminals O2 of the equalization units 21, 22, 23 are output from the equalization units 22, 23, respectively.
, 24, and the output of the second output terminal O2 of the equalization unit 24 is input to one terminal of the subtracter 29. In the embodiment configured in this way, each equalization unit 21, 22, 23, 2
The delay amount of each variable delay circuit No. 4 is set according to the ghost delay time. As a result, each equalization unit 21, 22
, 23 and 24, outputs for removing delay time ghosts based on the delay amount of each variable delay circuit are created. This output is summed in each equalization unit,
It is applied from equalization unit 24 to subtracter 29 . In this way, the subtracter 29 subtracts the output of the equalization unit 24 from the video signal input via the input terminal 1, thereby outputting the ghost-free output to the output terminal 5.

In this manner, the same effects as the embodiment shown in FIG. 1 can be obtained in this embodiment as well.

Furthermore, in the digital ghost removal apparatus of the present invention, as shown in FIGS. 1 and 12, the equalization unit as a whole is connected in a feedback manner; however, the present invention is effective even if the equalization unit is connected in a feedforward manner. be.

Furthermore, in FIGS. 1 and 12, even if the main signal is also in the waveform equalization mode passing through the equalization unit,
The present invention is effective.

[0062]

As explained above, according to the present invention, the number of taps as a whole is small, the cost is low, the hardware is not so complicated, and the television has a good signal-to-noise ratio with few remaining parts. A fully practical digitized ghost removal device is obtained in which signals can be obtained. It uses an input-weighted digital transversal filter,
Each first adder can be configured as two inputs and one output, and has the advantage of being easy to configure. Furthermore, by adding a digital equalization circuit, a device with high ghost removal performance that can also remove grandchild ghosts can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital ghost removal device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of the digital equalization circuit in FIG. 1.

FIG. 3 is a diagram for explaining the operation of ghost removal.

FIG. 4 is a block diagram showing another digital equalization circuit.

FIG. 5 is a block diagram showing another digital equalization circuit.

FIG. 6 is a block diagram showing another digital equalization circuit.

FIG. 7 is an operation flowchart for explaining the operation of the embodiment in FIG. 1;

FIG. 8 is a circuit diagram showing another example of the variable delay circuit of the digital equalization circuit.

FIG. 9 is a timing chart for explaining the operation of FIG. 8;

FIG. 10 is a block diagram showing another digital equalization circuit.

FIG. 11 is a block diagram showing another digital equalization circuit.

FIG. 12 is a block diagram showing another embodiment of the digital ghost removal device of the present invention.

FIG. 13 is a block diagram of a conventional ghost removal device.

FIG. 14 is a circuit diagram of a conventional digital equalization circuit.

[Explanation of symbols]

I1...First input terminal I2...Second input terminal O1...First output terminal O2...Second output terminal 29...Subtractor 21, 22, 23, 24...Digital equalization circuit (equalization unit)

Claims (1)

[Claims] 1. A subtracter that subtracts and outputs a ghost cancellation signal from a television signal containing ghosts, and a plurality of digital equalization circuits connected in parallel, wherein the output of the subtracter is the same as that of the digital equalization circuit. Each first of the circuit
A second output for removing the ghost is output from the second output terminal of each of the digital equalization circuits, and a second output for removing the ghost is output from the second output terminal of the digital equalization circuit in the first stage. The digital equalization circuit includes a group of digital equalization circuits that provide a cancellation signal to the subtracter, and a control circuit that controls each of the digital equalization circuits based on the output of the subtracter, and the digital equalization circuit A variable delay circuit that changes the delay time of a signal input to a terminal and outputs the delayed signal, a plurality of tap coefficient units whose input terminals are commonly connected, and a plurality of tap coefficient units that add the outputs of these coefficient units. and a plurality of unit time delay elements that delay the output of the tap coefficient unit by a unit time and sequentially supply the output to the first adder at the next stage, and the output of the variable delay circuit is connected to the input terminal. an input-weighted digital transversal filter to be input; a memory for storing a gain value in the tap coefficient unit of the transversal filter and a delay time in the variable delay circuit; a second adder that adds the sum of the sum of the sum and the second output input to the input terminal of the digital ghost remover and outputs the sum from the second output terminal as the second output. .